LXR qemu/include/hw/misc/iotkit-secctl.h

   1/*
   2 * ARM IoT Kit security controller
   3 *
   4 * Copyright (c) 2018 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 or
   9 * (at your option) any later version.
  10 */
  11
  12/* This is a model of the security controller which is part of the
  13 * Arm IoT Kit and documented in
  14 * https://developer.arm.com/documentation/ecm0601256/latest
  15 *
  16 * QEMU interface:
  17 *  + sysbus MMIO region 0 is the "secure privilege control block" registers
  18 *  + sysbus MMIO region 1 is the "non-secure privilege control block" registers
  19 *  + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
  20 *    should RAZ/WI or bus error
  21 *  + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
  22 *  + named GPIO output "msc_irq" for the combined IRQ line from the MSCs
  23 * Controlling the 2 APB PPCs in the IoTKit:
  24 *  + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
  25 *  + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
  26 *  + named GPIO outputs apb_ppc{0,1}_irq_enable
  27 *  + named GPIO outputs apb_ppc{0,1}_irq_clear
  28 *  + named GPIO inputs apb_ppc{0,1}_irq_status
  29 * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
  30 * might provide:
  31 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  32 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  33 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  34 *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  35 *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  36 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  37 * might provide:
  38 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  39 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  40 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  41 *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  42 *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  43 * Controlling the (up to) 4 MPCs in the IoTKit/SSE:
  44 *  + named GPIO inputs mpc_status[0..3]
  45 * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  46 * might provide:
  47 *  + named GPIO inputs mpcexp_status[0..15]
  48 * Controlling each of the 16 expansion MSCs which a system using the IoTKit
  49 * might provide:
  50 *  + named GPIO inputs mscexp_status[0..15]
  51 *  + named GPIO outputs mscexp_clear[0..15]
  52 *  + named GPIO outputs mscexp_ns[0..15]
  53 */
  54
  55#ifndef IOTKIT_SECCTL_H
  56#define IOTKIT_SECCTL_H
  57
  58#include "hw/sysbus.h"
  59#include "qom/object.h"
  60
  61#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
  62OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSecCtl, IOTKIT_SECCTL)
  63
  64#define IOTS_APB_PPC0_NUM_PORTS 3
  65#define IOTS_APB_PPC1_NUM_PORTS 1
  66#define IOTS_PPC_NUM_PORTS 16
  67#define IOTS_NUM_APB_PPC 2
  68#define IOTS_NUM_APB_EXP_PPC 4
  69#define IOTS_NUM_AHB_EXP_PPC 4
  70#define IOTS_NUM_EXP_MPC 16
  71#define IOTS_NUM_MPC 4
  72#define IOTS_NUM_EXP_MSC 16
  73
  74
  75/* State and IRQ lines relating to a PPC. For the
  76 * PPCs in the IoTKit not all the IRQ lines are used.
  77 */
  78typedef struct IoTKitSecCtlPPC {
  79    qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
  80    qemu_irq ap[IOTS_PPC_NUM_PORTS];
  81    qemu_irq irq_enable;
  82    qemu_irq irq_clear;
  83
  84    uint32_t ns;
  85    uint32_t sp;
  86    uint32_t nsp;
  87
  88    /* Number of ports actually present */
  89    int numports;
  90    /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
  91    int irq_bit_offset;
  92    IoTKitSecCtl *parent;
  93} IoTKitSecCtlPPC;
  94
  95struct IoTKitSecCtl {
  96    /*< private >*/
  97    SysBusDevice parent_obj;
  98
  99    /*< public >*/
 100    qemu_irq sec_resp_cfg;
 101    qemu_irq nsc_cfg_irq;
 102
 103    MemoryRegion s_regs;
 104    MemoryRegion ns_regs;
 105
 106    uint32_t secppcintstat;
 107    uint32_t secppcinten;
 108    uint32_t secrespcfg;
 109    uint32_t nsccfg;
 110    uint32_t brginten;
 111    uint32_t mpcintstatus;
 112
 113    uint32_t secmscintstat;
 114    uint32_t secmscinten;
 115    uint32_t nsmscexp;
 116    qemu_irq mscexp_clear[IOTS_NUM_EXP_MSC];
 117    qemu_irq mscexp_ns[IOTS_NUM_EXP_MSC];
 118    qemu_irq msc_irq;
 119
 120    IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
 121    IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
 122    IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
 123
 124    uint32_t sse_version;
 125};
 126
 127#endif
 128