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22#ifndef HW_Q35_H
23#define HW_Q35_H
24
25#include "hw/pci/pci.h"
26#include "hw/pci/pcie_host.h"
27#include "hw/pci-host/pam.h"
28#include "qemu/units.h"
29#include "qemu/range.h"
30#include "qom/object.h"
31
32#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
33OBJECT_DECLARE_SIMPLE_TYPE(Q35PCIHost, Q35_HOST_DEVICE)
34
35#define TYPE_MCH_PCI_DEVICE "mch"
36OBJECT_DECLARE_SIMPLE_TYPE(MCHPCIState, MCH_PCI_DEVICE)
37
38struct MCHPCIState {
39
40 PCIDevice parent_obj;
41
42
43 MemoryRegion *ram_memory;
44 MemoryRegion *pci_address_space;
45 MemoryRegion *system_memory;
46 MemoryRegion *address_space_io;
47 PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT];
48 MemoryRegion smram_region, open_high_smram;
49 MemoryRegion smram, low_smram, high_smram;
50 MemoryRegion tseg_blackhole, tseg_window;
51 MemoryRegion smbase_blackhole, smbase_window;
52 bool has_smram_at_smbase;
53 Range pci_hole;
54 uint64_t below_4g_mem_size;
55 uint64_t above_4g_mem_size;
56 uint64_t pci_hole64_size;
57 uint32_t short_root_bus;
58 uint16_t ext_tseg_mbytes;
59};
60
61struct Q35PCIHost {
62
63 PCIExpressHost parent_obj;
64
65
66 bool pci_hole64_fix;
67 MCHPCIState mch;
68};
69
70#define Q35_MASK(bit, ms_bit, ls_bit) \
71((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
72
73
74
75
76
77#define MCH_HOST_PROP_RAM_MEM "ram-mem"
78#define MCH_HOST_PROP_PCI_MEM "pci-mem"
79#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
80#define MCH_HOST_PROP_IO_MEM "io-mem"
81
82
83#define MCH_HOST_BRIDGE "MCH"
84
85#define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
86#define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
87
88
89#define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
90
91#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
92#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2
93#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
94#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
95
96#define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB)
97#define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
98#define MCH_HOST_BRIDGE_F_SMBASE 0x9c
99#define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
100#define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
101#define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02
102
103#define MCH_HOST_BRIDGE_PCIEXBAR 0x60
104#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8
105#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
106#define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000)
107#define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28)
108#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
109#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
110#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
111#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
112#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
113#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
114#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
115#define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
116
117#define MCH_HOST_BRIDGE_PAM_NB 7
118#define MCH_HOST_BRIDGE_PAM_SIZE 7
119#define MCH_HOST_BRIDGE_PAM0 0x90
120#define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
121#define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000
122#define MCH_HOST_BRIDGE_PAM1 0x91
123#define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
124#define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
125#define MCH_HOST_BRIDGE_PAM2 0x92
126#define MCH_HOST_BRIDGE_PAM3 0x93
127#define MCH_HOST_BRIDGE_PAM4 0x94
128#define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
129#define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
130#define MCH_HOST_BRIDGE_PAM5 0x95
131#define MCH_HOST_BRIDGE_PAM6 0x96
132#define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
133#define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
134#define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
135#define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
136#define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
137#define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
138#define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
139#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
140#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
141
142#define MCH_HOST_BRIDGE_SMRAM 0x9d
143#define MCH_HOST_BRIDGE_SMRAM_SIZE 2
144#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
145#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
146#define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
147#define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
148#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
149#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2)
150#define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
151#define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
152#define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
153#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
154#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \
155 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
156#define MCH_HOST_BRIDGE_SMRAM_WMASK \
157 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \
158 MCH_HOST_BRIDGE_SMRAM_D_CLS | \
159 MCH_HOST_BRIDGE_SMRAM_D_LCK | \
160 MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
161#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
162 MCH_HOST_BRIDGE_SMRAM_D_CLS
163
164#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
165#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
166#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6))
167#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5))
168#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4))
169#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3))
170#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
171#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
172#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
173#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
174#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
175#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
176 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
177 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \
178 MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
179#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \
180 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
181 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
182 MCH_HOST_BRIDGE_ESMRAMC_T_EN)
183#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
184
185
186#define MCH_PCIE_DEV 1
187#define MCH_PCIE_FUNC 0
188
189uint64_t mch_mcfg_base(void);
190
191
192
193
194
195
196#define Q35_PSEUDO_BUS_PLATFORM (0xff)
197#define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
198
199#endif
200
