LXR qemu/include/hw/pci-host/spapr.h

   1/*
   2 * QEMU SPAPR PCI BUS definitions
   3 *
   4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PCI_HOST_SPAPR_H
  21#define PCI_HOST_SPAPR_H
  22
  23#include "hw/ppc/spapr.h"
  24#include "hw/pci/pci.h"
  25#include "hw/pci/pci_host.h"
  26#include "hw/ppc/xics.h"
  27#include "qom/object.h"
  28
  29#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
  30
  31OBJECT_DECLARE_SIMPLE_TYPE(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE)
  32
  33#define SPAPR_PCI_DMA_MAX_WINDOWS    2
  34
  35
  36typedef struct SpaprPciMsi {
  37    uint32_t first_irq;
  38    uint32_t num;
  39} SpaprPciMsi;
  40
  41typedef struct SpaprPciMsiMig {
  42    uint32_t key;
  43    SpaprPciMsi value;
  44} SpaprPciMsiMig;
  45
  46typedef struct SpaprPciLsi {
  47    uint32_t irq;
  48} SpaprPciLsi;
  49
  50typedef struct SpaprPhbPciNvGpuConfig SpaprPhbPciNvGpuConfig;
  51
  52struct SpaprPhbState {
  53    PCIHostState parent_obj;
  54
  55    uint32_t index;
  56    uint64_t buid;
  57    char *dtbusname;
  58    bool dr_enabled;
  59
  60    MemoryRegion memspace, iospace;
  61    hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
  62    uint64_t mem64_win_pciaddr;
  63    hwaddr io_win_addr, io_win_size;
  64    MemoryRegion mem32window, mem64window, iowindow, msiwindow;
  65
  66    uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
  67    hwaddr dma_win_addr, dma_win_size;
  68    AddressSpace iommu_as;
  69    MemoryRegion iommu_root;
  70
  71    SpaprPciLsi lsi_table[PCI_NUM_PINS];
  72
  73    GHashTable *msi;
  74    /* Temporary cache for migration purposes */
  75    int32_t msi_devs_num;
  76    SpaprPciMsiMig *msi_devs;
  77
  78    QLIST_ENTRY(SpaprPhbState) list;
  79
  80    bool ddw_enabled;
  81    uint64_t page_size_mask;
  82    uint64_t dma64_win_addr;
  83
  84    uint32_t numa_node;
  85
  86    bool pcie_ecs; /* Allow access to PCIe extended config space? */
  87
  88    /* Fields for migration compatibility hacks */
  89    bool pre_2_8_migration;
  90    uint32_t mig_liobn;
  91    hwaddr mig_mem_win_addr, mig_mem_win_size;
  92    hwaddr mig_io_win_addr, mig_io_win_size;
  93    hwaddr nv2_gpa_win_addr;
  94    hwaddr nv2_atsd_win_addr;
  95    SpaprPhbPciNvGpuConfig *nvgpus;
  96    bool pre_5_1_assoc;
  97};
  98
  99#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
 100#define SPAPR_PCI_MEM32_WIN_SIZE     \
 101    ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
 102#define SPAPR_PCI_MEM64_WIN_SIZE     0x10000000000ULL /* 1 TiB */
 103
 104/* All PCI outbound windows will be within this range */
 105#define SPAPR_PCI_BASE               (1ULL << 45) /* 32 TiB */
 106#define SPAPR_PCI_LIMIT              (1ULL << 46) /* 64 TiB */
 107
 108#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
 109                        SPAPR_PCI_MEM64_WIN_SIZE - 1)
 110
 111#define SPAPR_PCI_IO_WIN_SIZE        0x10000
 112
 113#define SPAPR_PCI_MSI_WINDOW         0x40000000000ULL
 114
 115#define SPAPR_PCI_NV2RAM64_WIN_BASE  SPAPR_PCI_LIMIT
 116#define SPAPR_PCI_NV2RAM64_WIN_SIZE  (2 * TiB) /* For up to 6 GPUs 256GB each */
 117
 118/* Max number of NVLinks per GPU in any physical box */
 119#define NVGPU_MAX_LINKS              3
 120
 121/*
 122 * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB
 123 * which is enough. We do not need DMA for ATSD so we put them at 128TiB.
 124 */
 125#define SPAPR_PCI_NV2ATSD_WIN_BASE   (128 * TiB)
 126#define SPAPR_PCI_NV2ATSD_WIN_SIZE   (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
 127                                      64 * KiB)
 128
 129int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
 130                 uint32_t intc_phandle, void *fdt, int *node_offset);
 131
 132void spapr_pci_rtas_init(void);
 133
 134SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid);
 135PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
 136                              uint32_t config_addr);
 137
 138/* DRC callbacks */
 139void spapr_phb_remove_pci_device_cb(DeviceState *dev);
 140int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 141                          void *fdt, int *fdt_start_offset, Error **errp);
 142
 143/* VFIO EEH hooks */
 144#ifdef CONFIG_LINUX
 145bool spapr_phb_eeh_available(SpaprPhbState *sphb);
 146int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 147                                  unsigned int addr, int option);
 148int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
 149int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
 150int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
 151void spapr_phb_vfio_reset(DeviceState *qdev);
 152void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
 153void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
 154void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
 155                                 Error **errp);
 156void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
 157void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
 158                                        SpaprPhbState *sphb);
 159#else
 160static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
 161{
 162    return false;
 163}
 164static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 165                                                unsigned int addr, int option)
 166{
 167    return RTAS_OUT_HW_ERROR;
 168}
 169static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
 170                                               int *state)
 171{
 172    return RTAS_OUT_HW_ERROR;
 173}
 174static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
 175{
 176    return RTAS_OUT_HW_ERROR;
 177}
 178static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
 179{
 180    return RTAS_OUT_HW_ERROR;
 181}
 182static inline void spapr_phb_vfio_reset(DeviceState *qdev)
 183{
 184}
 185static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
 186{
 187}
 188static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
 189{
 190}
 191static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
 192                                               int bus_off, Error **errp)
 193{
 194}
 195static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
 196                                                   void *fdt)
 197{
 198}
 199static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
 200                                                      int offset,
 201                                                      SpaprPhbState *sphb)
 202{
 203}
 204#endif
 205
 206void spapr_phb_dma_reset(SpaprPhbState *sphb);
 207
 208static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb)
 209{
 210    return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
 211}
 212
 213char *spapr_pci_fw_dev_name(PCIDevice *dev);
 214
 215#endif /* PCI_HOST_SPAPR_H */
 216