1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "exec/memory.h"
5#include "sysemu/dma.h"
6
7
8#include "hw/isa/isa.h"
9
10#include "hw/pci/pcie.h"
11#include "qom/object.h"
12
13extern bool pci_available;
14
15
16
17#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20#define PCI_FUNC(devfn) ((devfn) & 0x07)
21#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22#define PCI_BUS_MAX 256
23#define PCI_DEVFN_MAX 256
24#define PCI_SLOT_MAX 32
25#define PCI_FUNC_MAX 8
26
27
28#include "hw/pci/pci_ids.h"
29
30
31
32
33#define PCI_DEVICE_ID_IBM_440GX 0x027f
34#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
35
36
37#define PCI_VENDOR_ID_HITACHI 0x1054
38#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
39
40
41#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
46
47
48#define PCI_DEVICE_ID_REALTEK_8029 0x8029
49
50
51#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
52
53
54#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
55
56
57#define PCI_VENDOR_ID_QEMU 0x1234
58#define PCI_DEVICE_ID_QEMU_VGA 0x1111
59#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
60
61
62#define PCI_VENDOR_ID_VMWARE 0x15ad
63#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
64#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
65#define PCI_DEVICE_ID_VMWARE_NET 0x0720
66#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
67#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
68#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
69#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
70
71
72#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
73#define PCI_DEVICE_ID_INTEL_82557 0x1229
74#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
75
76
77#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
78#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
79#define PCI_SUBDEVICE_ID_QEMU 0x1100
80
81#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
82#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
83#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
84#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
85#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
86#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
87#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
88#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
89#define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
90#define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
91#define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
92
93#define PCI_VENDOR_ID_REDHAT 0x1b36
94#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
95#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
96#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
97#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
98#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
99#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
100#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
101#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
102#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
103#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
104#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
105#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
106#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
107#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
108#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
109#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
110#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
111#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
112
113#define FMT_PCIBUS PRIx64
114
115typedef uint64_t pcibus_t;
116
117struct PCIHostDeviceAddress {
118 unsigned int domain;
119 unsigned int bus;
120 unsigned int slot;
121 unsigned int function;
122};
123
124typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
125 uint32_t address, uint32_t data, int len);
126typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
127 uint32_t address, int len);
128typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
129 pcibus_t addr, pcibus_t size, int type);
130typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
131
132typedef struct PCIIORegion {
133 pcibus_t addr;
134#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
135 pcibus_t size;
136 uint8_t type;
137 MemoryRegion *memory;
138 MemoryRegion *address_space;
139} PCIIORegion;
140
141#define PCI_ROM_SLOT 6
142#define PCI_NUM_REGIONS 7
143
144enum {
145 QEMU_PCI_VGA_MEM,
146 QEMU_PCI_VGA_IO_LO,
147 QEMU_PCI_VGA_IO_HI,
148 QEMU_PCI_VGA_NUM_REGIONS,
149};
150
151#define QEMU_PCI_VGA_MEM_BASE 0xa0000
152#define QEMU_PCI_VGA_MEM_SIZE 0x20000
153#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
154#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
155#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
156#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
157
158#include "hw/pci/pci_regs.h"
159
160
161#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
162
163
164#define PCI_CONFIG_HEADER_SIZE 0x40
165
166#define PCI_CONFIG_SPACE_SIZE 0x100
167
168#define PCIE_CONFIG_SPACE_SIZE 0x1000
169
170#define PCI_NUM_PINS 4
171
172
173enum {
174 QEMU_PCI_CAP_MSI = 0x1,
175 QEMU_PCI_CAP_MSIX = 0x2,
176 QEMU_PCI_CAP_EXPRESS = 0x4,
177
178
179#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
180 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
181
182
183#define QEMU_PCI_CAP_SERR_BITNR 4
184 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
185
186#define QEMU_PCI_SHPC_BITNR 5
187 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
188#define QEMU_PCI_SLOTID_BITNR 6
189 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
190
191#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
192 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
193
194#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
195 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
196#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
197 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
198};
199
200#define TYPE_PCI_DEVICE "pci-device"
201typedef struct PCIDeviceClass PCIDeviceClass;
202DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
203 PCI_DEVICE, TYPE_PCI_DEVICE)
204
205
206#define INTERFACE_PCIE_DEVICE "pci-express-device"
207
208
209#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
210
211typedef struct PCIINTxRoute {
212 enum {
213 PCI_INTX_ENABLED,
214 PCI_INTX_INVERTED,
215 PCI_INTX_DISABLED,
216 } mode;
217 int irq;
218} PCIINTxRoute;
219
220struct PCIDeviceClass {
221 DeviceClass parent_class;
222
223 void (*realize)(PCIDevice *dev, Error **errp);
224 PCIUnregisterFunc *exit;
225 PCIConfigReadFunc *config_read;
226 PCIConfigWriteFunc *config_write;
227
228 uint16_t vendor_id;
229 uint16_t device_id;
230 uint8_t revision;
231 uint16_t class_id;
232 uint16_t subsystem_vendor_id;
233 uint16_t subsystem_id;
234
235
236
237
238
239
240 bool is_bridge;
241
242
243 const char *romfile;
244};
245
246typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
247typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
248 MSIMessage msg);
249typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
250typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
251 unsigned int vector_start,
252 unsigned int vector_end);
253
254enum PCIReqIDType {
255 PCI_REQ_ID_INVALID = 0,
256 PCI_REQ_ID_BDF,
257 PCI_REQ_ID_SECONDARY_BUS,
258 PCI_REQ_ID_MAX,
259};
260typedef enum PCIReqIDType PCIReqIDType;
261
262struct PCIReqIDCache {
263 PCIDevice *dev;
264 PCIReqIDType type;
265};
266typedef struct PCIReqIDCache PCIReqIDCache;
267
268struct PCIDevice {
269 DeviceState qdev;
270 bool partially_hotplugged;
271 bool has_power;
272
273
274 uint8_t *config;
275
276
277
278 uint8_t *cmask;
279
280
281 uint8_t *wmask;
282
283
284 uint8_t *w1cmask;
285
286
287 uint8_t *used;
288
289
290 int32_t devfn;
291
292
293
294
295 PCIReqIDCache requester_id_cache;
296 char name[64];
297 PCIIORegion io_regions[PCI_NUM_REGIONS];
298 AddressSpace bus_master_as;
299 MemoryRegion bus_master_container_region;
300 MemoryRegion bus_master_enable_region;
301
302
303 PCIConfigReadFunc *config_read;
304 PCIConfigWriteFunc *config_write;
305
306
307 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
308 bool has_vga;
309
310
311 uint8_t irq_state;
312
313
314 uint32_t cap_present;
315
316
317 uint8_t msix_cap;
318
319
320 int msix_entries_nr;
321
322
323 uint8_t *msix_table;
324 uint8_t *msix_pba;
325
326 MemoryRegion msix_exclusive_bar;
327
328 MemoryRegion msix_table_mmio;
329 MemoryRegion msix_pba_mmio;
330
331 unsigned *msix_entry_used;
332
333 bool msix_function_masked;
334
335 int32_t version_id;
336
337
338 uint8_t msi_cap;
339
340
341 PCIExpressDevice exp;
342
343
344 SHPCDevice *shpc;
345
346
347 char *romfile;
348 uint32_t romsize;
349 bool has_rom;
350 MemoryRegion rom;
351 uint32_t rom_bar;
352
353
354 PCIINTxRoutingNotifier intx_routing_notifier;
355
356
357 MSIVectorUseNotifier msix_vector_use_notifier;
358 MSIVectorReleaseNotifier msix_vector_release_notifier;
359 MSIVectorPollNotifier msix_vector_poll_notifier;
360
361
362 char *failover_pair_id;
363 uint32_t acpi_index;
364};
365
366void pci_register_bar(PCIDevice *pci_dev, int region_num,
367 uint8_t attr, MemoryRegion *memory);
368void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
369 MemoryRegion *io_lo, MemoryRegion *io_hi);
370void pci_unregister_vga(PCIDevice *pci_dev);
371pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
372
373int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
374 uint8_t offset, uint8_t size,
375 Error **errp);
376
377void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
378
379uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
380
381
382uint32_t pci_default_read_config(PCIDevice *d,
383 uint32_t address, int len);
384void pci_default_write_config(PCIDevice *d,
385 uint32_t address, uint32_t val, int len);
386void pci_device_save(PCIDevice *s, QEMUFile *f);
387int pci_device_load(PCIDevice *s, QEMUFile *f);
388MemoryRegion *pci_address_space(PCIDevice *dev);
389MemoryRegion *pci_address_space_io(PCIDevice *dev);
390
391
392
393
394
395int pci_bar(PCIDevice *d, int reg);
396
397typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
398typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
399typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
400
401#define TYPE_PCI_BUS "PCI"
402OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
403#define TYPE_PCIE_BUS "PCIE"
404
405typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
406typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
407typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
408
409bool pci_bus_is_express(PCIBus *bus);
410
411void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
412 const char *name,
413 MemoryRegion *address_space_mem,
414 MemoryRegion *address_space_io,
415 uint8_t devfn_min, const char *typename);
416PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
417 MemoryRegion *address_space_mem,
418 MemoryRegion *address_space_io,
419 uint8_t devfn_min, const char *typename);
420void pci_root_bus_cleanup(PCIBus *bus);
421void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
422 void *irq_opaque, int nirq);
423void pci_bus_irqs_cleanup(PCIBus *bus);
424int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
425
426static inline int pci_swizzle(int slot, int pin)
427{
428 return (slot + pin) % PCI_NUM_PINS;
429}
430int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
431PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
432 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
433 void *irq_opaque,
434 MemoryRegion *address_space_mem,
435 MemoryRegion *address_space_io,
436 uint8_t devfn_min, int nirq,
437 const char *typename);
438void pci_unregister_root_bus(PCIBus *bus);
439void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
440PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
441bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
442void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
443void pci_device_set_intx_routing_notifier(PCIDevice *dev,
444 PCIINTxRoutingNotifier notifier);
445void pci_device_reset(PCIDevice *dev);
446
447PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
448 const char *default_model,
449 const char *default_devaddr);
450
451PCIDevice *pci_vga_init(PCIBus *bus);
452
453static inline PCIBus *pci_get_bus(const PCIDevice *dev)
454{
455 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
456}
457int pci_bus_num(PCIBus *s);
458void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
459static inline int pci_dev_bus_num(const PCIDevice *dev)
460{
461 return pci_bus_num(pci_get_bus(dev));
462}
463
464int pci_bus_numa_node(PCIBus *bus);
465void pci_for_each_device(PCIBus *bus, int bus_num,
466 pci_bus_dev_fn fn,
467 void *opaque);
468void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
469 pci_bus_dev_fn fn,
470 void *opaque);
471void pci_for_each_device_under_bus(PCIBus *bus,
472 pci_bus_dev_fn fn, void *opaque);
473void pci_for_each_device_under_bus_reverse(PCIBus *bus,
474 pci_bus_dev_fn fn,
475 void *opaque);
476void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
477 pci_bus_fn end, void *parent_state);
478PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
479
480
481static inline
482void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
483{
484 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
485}
486
487PCIBus *pci_device_root_bus(const PCIDevice *d);
488const char *pci_root_bus_path(PCIDevice *dev);
489bool pci_bus_bypass_iommu(PCIBus *bus);
490PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
491int pci_qdev_find_device(const char *id, PCIDevice **pdev);
492void pci_bus_get_w64_range(PCIBus *bus, Range *range);
493
494void pci_device_deassert_intx(PCIDevice *dev);
495
496typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
497
498AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
499void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
500
501static inline void
502pci_set_byte(uint8_t *config, uint8_t val)
503{
504 *config = val;
505}
506
507static inline uint8_t
508pci_get_byte(const uint8_t *config)
509{
510 return *config;
511}
512
513static inline void
514pci_set_word(uint8_t *config, uint16_t val)
515{
516 stw_le_p(config, val);
517}
518
519static inline uint16_t
520pci_get_word(const uint8_t *config)
521{
522 return lduw_le_p(config);
523}
524
525static inline void
526pci_set_long(uint8_t *config, uint32_t val)
527{
528 stl_le_p(config, val);
529}
530
531static inline uint32_t
532pci_get_long(const uint8_t *config)
533{
534 return ldl_le_p(config);
535}
536
537
538
539
540
541
542
543
544static inline void
545pci_set_quad(uint8_t *config, uint64_t val)
546{
547 stq_le_p(config, val);
548}
549
550static inline uint64_t
551pci_get_quad(const uint8_t *config)
552{
553 return ldq_le_p(config);
554}
555
556static inline void
557pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
558{
559 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
560}
561
562static inline void
563pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
564{
565 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
566}
567
568static inline void
569pci_config_set_revision(uint8_t *pci_config, uint8_t val)
570{
571 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
572}
573
574static inline void
575pci_config_set_class(uint8_t *pci_config, uint16_t val)
576{
577 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
578}
579
580static inline void
581pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
582{
583 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
584}
585
586static inline void
587pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
588{
589 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
590}
591
592
593
594
595
596
597
598static inline uint8_t
599pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
600{
601 uint8_t val = pci_get_byte(config);
602 pci_set_byte(config, val & ~mask);
603 return val & mask;
604}
605
606static inline uint8_t
607pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
608{
609 uint8_t val = pci_get_byte(config);
610 pci_set_byte(config, val | mask);
611 return val & mask;
612}
613
614static inline uint16_t
615pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
616{
617 uint16_t val = pci_get_word(config);
618 pci_set_word(config, val & ~mask);
619 return val & mask;
620}
621
622static inline uint16_t
623pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
624{
625 uint16_t val = pci_get_word(config);
626 pci_set_word(config, val | mask);
627 return val & mask;
628}
629
630static inline uint32_t
631pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
632{
633 uint32_t val = pci_get_long(config);
634 pci_set_long(config, val & ~mask);
635 return val & mask;
636}
637
638static inline uint32_t
639pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
640{
641 uint32_t val = pci_get_long(config);
642 pci_set_long(config, val | mask);
643 return val & mask;
644}
645
646static inline uint64_t
647pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
648{
649 uint64_t val = pci_get_quad(config);
650 pci_set_quad(config, val & ~mask);
651 return val & mask;
652}
653
654static inline uint64_t
655pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
656{
657 uint64_t val = pci_get_quad(config);
658 pci_set_quad(config, val | mask);
659 return val & mask;
660}
661
662
663static inline void
664pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
665{
666 uint8_t val = pci_get_byte(config);
667 uint8_t rval = reg << ctz32(mask);
668 pci_set_byte(config, (~mask & val) | (mask & rval));
669}
670
671static inline uint8_t
672pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
673{
674 uint8_t val = pci_get_byte(config);
675 return (val & mask) >> ctz32(mask);
676}
677
678static inline void
679pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
680{
681 uint16_t val = pci_get_word(config);
682 uint16_t rval = reg << ctz32(mask);
683 pci_set_word(config, (~mask & val) | (mask & rval));
684}
685
686static inline uint16_t
687pci_get_word_by_mask(uint8_t *config, uint16_t mask)
688{
689 uint16_t val = pci_get_word(config);
690 return (val & mask) >> ctz32(mask);
691}
692
693static inline void
694pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
695{
696 uint32_t val = pci_get_long(config);
697 uint32_t rval = reg << ctz32(mask);
698 pci_set_long(config, (~mask & val) | (mask & rval));
699}
700
701static inline uint32_t
702pci_get_long_by_mask(uint8_t *config, uint32_t mask)
703{
704 uint32_t val = pci_get_long(config);
705 return (val & mask) >> ctz32(mask);
706}
707
708static inline void
709pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
710{
711 uint64_t val = pci_get_quad(config);
712 uint64_t rval = reg << ctz32(mask);
713 pci_set_quad(config, (~mask & val) | (mask & rval));
714}
715
716static inline uint64_t
717pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
718{
719 uint64_t val = pci_get_quad(config);
720 return (val & mask) >> ctz32(mask);
721}
722
723PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
724 const char *name);
725PCIDevice *pci_new(int devfn, const char *name);
726bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
727
728PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
729 bool multifunction,
730 const char *name);
731PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
732
733void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
734
735qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
736void pci_set_irq(PCIDevice *pci_dev, int level);
737
738static inline void pci_irq_assert(PCIDevice *pci_dev)
739{
740 pci_set_irq(pci_dev, 1);
741}
742
743static inline void pci_irq_deassert(PCIDevice *pci_dev)
744{
745 pci_set_irq(pci_dev, 0);
746}
747
748
749
750
751
752static inline void pci_irq_pulse(PCIDevice *pci_dev)
753{
754 pci_irq_assert(pci_dev);
755 pci_irq_deassert(pci_dev);
756}
757
758static inline int pci_is_express(const PCIDevice *d)
759{
760 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
761}
762
763static inline int pci_is_express_downstream_port(const PCIDevice *d)
764{
765 uint8_t type;
766
767 if (!pci_is_express(d) || !d->exp.exp_cap) {
768 return 0;
769 }
770
771 type = pcie_cap_get_type(d);
772
773 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
774}
775
776static inline uint32_t pci_config_size(const PCIDevice *d)
777{
778 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
779}
780
781static inline uint16_t pci_get_bdf(PCIDevice *dev)
782{
783 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
784}
785
786uint16_t pci_requester_id(PCIDevice *dev);
787
788
789static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
790{
791 return &dev->bus_master_as;
792}
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
808 void *buf, dma_addr_t len,
809 DMADirection dir)
810{
811 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
812}
813
814
815
816
817
818
819
820
821
822
823
824
825
826static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
827 void *buf, dma_addr_t len)
828{
829 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
830}
831
832
833
834
835
836
837
838
839
840
841
842
843
844static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
845 const void *buf, dma_addr_t len)
846{
847 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
848}
849
850#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
851 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
852 dma_addr_t addr) \
853 { \
854 return ld##_l##_dma(pci_get_address_space(dev), addr); \
855 } \
856 static inline void st##_s##_pci_dma(PCIDevice *dev, \
857 dma_addr_t addr, uint##_bits##_t val) \
858 { \
859 st##_s##_dma(pci_get_address_space(dev), addr, val); \
860 }
861
862PCI_DMA_DEFINE_LDST(ub, b, 8);
863PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
864PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
865PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
866PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
867PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
868PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
869
870#undef PCI_DMA_DEFINE_LDST
871
872static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
873 dma_addr_t *plen, DMADirection dir)
874{
875 void *buf;
876
877 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
878 return buf;
879}
880
881static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
882 DMADirection dir, dma_addr_t access_len)
883{
884 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
885}
886
887static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
888 int alloc_hint)
889{
890 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
891}
892
893extern const VMStateDescription vmstate_pci_device;
894
895#define VMSTATE_PCI_DEVICE(_field, _state) { \
896 .name = (stringify(_field)), \
897 .size = sizeof(PCIDevice), \
898 .vmsd = &vmstate_pci_device, \
899 .flags = VMS_STRUCT, \
900 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
901}
902
903#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
904 .name = (stringify(_field)), \
905 .size = sizeof(PCIDevice), \
906 .vmsd = &vmstate_pci_device, \
907 .flags = VMS_STRUCT|VMS_POINTER, \
908 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
909}
910
911MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
912void pci_set_power(PCIDevice *pci_dev, bool state);
913
914#endif
915