LXR qemu/include/hw/ppc/pnv

   1/*
   2 * QEMU PowerPC PowerNV XSCOM bus definitions
   3 *
   4 * Copyright (c) 2016, IBM Corporation.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_PNV_XSCOM_H
  21#define PPC_PNV_XSCOM_H
  22
  23#include "qom/object.h"
  24
  25typedef struct PnvXScomInterface PnvXScomInterface;
  26
  27#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
  28#define PNV_XSCOM_INTERFACE(obj) \
  29    INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
  30typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass;
  31DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE,
  32                       TYPE_PNV_XSCOM_INTERFACE)
  33
  34struct PnvXScomInterfaceClass {
  35    InterfaceClass parent;
  36    int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
  37};
  38
  39/*
  40 * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
  41 *
  42 *   GPIO        0x1100xxxx
  43 *   SCOM        0x1101xxxx
  44 *   OHA         0x1102xxxx
  45 *   CLOCK CTL   0x1103xxxx
  46 *   FIR         0x1104xxxx
  47 *   THERM       0x1105xxxx
  48 *   <reserved>  0x1106xxxx
  49 *               ..
  50 *               0x110Exxxx
  51 *   PCB SLAVE   0x110Fxxxx
  52 */
  53
  54#define PNV_XSCOM_EX_CORE_BASE    0x10000000ull
  55
  56#define PNV_XSCOM_EX_BASE(core) \
  57    (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
  58#define PNV_XSCOM_EX_SIZE         0x100000
  59
  60#define PNV_XSCOM_LPC_BASE        0xb0020
  61#define PNV_XSCOM_LPC_SIZE        0x4
  62
  63#define PNV_XSCOM_PSIHB_BASE      0x2010900
  64#define PNV_XSCOM_PSIHB_SIZE      0x20
  65
  66#define PNV_XSCOM_OCC_BASE        0x0066000
  67#define PNV_XSCOM_OCC_SIZE        0x6000
  68
  69#define PNV_XSCOM_PBA_BASE        0x2013f00
  70#define PNV_XSCOM_PBA_SIZE        0x40
  71
  72#define PNV_XSCOM_PBCQ_NEST_BASE  0x2012000
  73#define PNV_XSCOM_PBCQ_NEST_SIZE  0x46
  74
  75#define PNV_XSCOM_PBCQ_PCI_BASE   0x9012000
  76#define PNV_XSCOM_PBCQ_PCI_SIZE   0x15
  77
  78#define PNV_XSCOM_PBCQ_SPCI_BASE  0x9013c00
  79#define PNV_XSCOM_PBCQ_SPCI_SIZE  0x5
  80
  81/*
  82 * Layout of the XSCOM PCB addresses (POWER 9)
  83 */
  84#define PNV9_XSCOM_EC_BASE(core) \
  85    ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
  86#define PNV9_XSCOM_EC_SIZE        0x100000
  87
  88#define PNV9_XSCOM_EQ_BASE(core) \
  89    ((uint64_t)(((core) & 0x1C) + 0x40) << 22)
  90#define PNV9_XSCOM_EQ_SIZE        0x100000
  91
  92#define PNV9_XSCOM_OCC_BASE       PNV_XSCOM_OCC_BASE
  93#define PNV9_XSCOM_OCC_SIZE       0x8000
  94
  95#define PNV9_XSCOM_PBA_BASE       0x5012b00
  96#define PNV9_XSCOM_PBA_SIZE       0x40
  97
  98#define PNV9_XSCOM_PSIHB_BASE     0x5012900
  99#define PNV9_XSCOM_PSIHB_SIZE     0x100
 100
 101#define PNV9_XSCOM_XIVE_BASE      0x5013000
 102#define PNV9_XSCOM_XIVE_SIZE      0x300
 103
 104#define PNV9_XSCOM_PEC_NEST_BASE  0x4010c00
 105#define PNV9_XSCOM_PEC_NEST_SIZE  0x100
 106
 107#define PNV9_XSCOM_PEC_PCI_BASE   0xd010800
 108#define PNV9_XSCOM_PEC_PCI_SIZE   0x200
 109
 110/* XSCOM PCI "pass-through" window to PHB SCOM */
 111#define PNV9_XSCOM_PEC_PCI_STK0   0x100
 112#define PNV9_XSCOM_PEC_PCI_STK1   0x140
 113#define PNV9_XSCOM_PEC_PCI_STK2   0x180
 114
 115/*
 116 * Layout of the XSCOM PCB addresses (POWER 10)
 117 */
 118#define PNV10_XSCOM_EQ_CHIPLET(core)  (0x20 + ((core) >> 2))
 119#define PNV10_XSCOM_EQ(chiplet)       ((chiplet) << 24)
 120#define PNV10_XSCOM_EC(proc)                    \
 121    ((0x2 << 16) | ((1 << (3 - (proc))) << 12))
 122
 123#define PNV10_XSCOM_EQ_BASE(core)     \
 124    ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
 125#define PNV10_XSCOM_EQ_SIZE        0x100000
 126
 127#define PNV10_XSCOM_EC_BASE(core) \
 128    ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
 129#define PNV10_XSCOM_EC_SIZE        0x100000
 130
 131#define PNV10_XSCOM_PSIHB_BASE     0x3011D00
 132#define PNV10_XSCOM_PSIHB_SIZE     0x100
 133
 134void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
 135int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
 136                 uint64_t xscom_base, uint64_t xscom_size,
 137                 const char *compat, int compat_size);
 138
 139void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
 140                             MemoryRegion *mr);
 141void pnv_xscom_region_init(MemoryRegion *mr,
 142                           Object *owner,
 143                           const MemoryRegionOps *ops,
 144                           void *opaque,
 145                           const char *name,
 146                           uint64_t size);
 147
 148#endif /* PPC_PNV_XSCOM_H */
 149