1#ifndef HW_PPC_H
2#define HW_PPC_H
3
4#include "target/ppc/cpu-qom.h"
5
6void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
7PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
8int ppc_cpu_pir(PowerPCCPU *cpu);
9
10
11typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
12typedef struct clk_setup_t clk_setup_t;
13struct clk_setup_t {
14 clk_setup_cb cb;
15 void *opaque;
16};
17static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
18{
19 if (clk->cb != NULL)
20 (*clk->cb)(clk->opaque, freq);
21}
22
23struct ppc_tb_t {
24
25 int64_t tb_offset;
26 int64_t atb_offset;
27 int64_t vtb_offset;
28 uint32_t tb_freq;
29
30 uint64_t decr_next;
31 uint32_t decr_freq;
32 QEMUTimer *decr_timer;
33
34 uint64_t hdecr_next;
35 QEMUTimer *hdecr_timer;
36 int64_t purr_offset;
37 void *opaque;
38 uint32_t flags;
39};
40
41
42#define PPC_TIMER_BOOKE (1 << 0)
43#define PPC_TIMER_E500 (1 << 1)
44#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2)
45
46
47
48#define PPC_DECR_ZERO_TRIGGERED (1 << 3)
49
50
51#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4)
52
53
54
55uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
56clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
57
58typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
59typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
60int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
61 int (*dcr_write_error)(int dcrn));
62int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
63 dcr_read_cb drc_read, dcr_write_cb dcr_write);
64clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
65 unsigned int decr_excp);
66
67
68void ppc40x_core_reset(PowerPCCPU *cpu);
69void ppc40x_chip_reset(PowerPCCPU *cpu);
70void ppc40x_system_reset(PowerPCCPU *cpu);
71
72#if defined(CONFIG_USER_ONLY)
73static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
74static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
75static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
76static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
77static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
78static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
79static inline void ppc_irq_reset(PowerPCCPU *cpu) {}
80#else
81void ppc40x_irq_init(PowerPCCPU *cpu);
82void ppce500_irq_init(PowerPCCPU *cpu);
83void ppc6xx_irq_init(PowerPCCPU *cpu);
84void ppc970_irq_init(PowerPCCPU *cpu);
85void ppcPOWER7_irq_init(PowerPCCPU *cpu);
86void ppcPOWER9_irq_init(PowerPCCPU *cpu);
87void ppc_irq_reset(PowerPCCPU *cpu);
88#endif
89
90
91enum {
92 ARCH_PREP = 0,
93 ARCH_MAC99,
94 ARCH_HEATHROW,
95 ARCH_MAC99_U3,
96};
97
98#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
99#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
100#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
101#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
102#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
103#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
104#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
105#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
106#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
107#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
108#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
109#define FW_CFG_PPC_VIACONFIG (FW_CFG_ARCH_LOCAL + 0x0b)
110
111#define PPC_SERIAL_MM_BAUDBASE 399193
112
113
114void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
115#endif
116