LXR qemu/include/hw/riscv/boot.h

   1/*
   2 * QEMU RISC-V Boot Helper
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms and conditions of the GNU General Public License,
   9 * version 2 or later, as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef RISCV_BOOT_H
  21#define RISCV_BOOT_H
  22
  23#include "exec/cpu-defs.h"
  24#include "hw/loader.h"
  25#include "hw/riscv/riscv_hart.h"
  26
  27#define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
  28#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
  29#define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
  30#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
  31
  32bool riscv_is_32bit(RISCVHartArrayState *harts);
  33
  34char *riscv_plic_hart_config_string(int hart_count);
  35
  36target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
  37                                          target_ulong firmware_end_addr);
  38target_ulong riscv_find_and_load_firmware(MachineState *machine,
  39                                          const char *default_machine_firmware,
  40                                          hwaddr firmware_load_addr,
  41                                          symbol_fn_t sym_cb);
  42char *riscv_find_firmware(const char *firmware_filename);
  43target_ulong riscv_load_firmware(const char *firmware_filename,
  44                                 hwaddr firmware_load_addr,
  45                                 symbol_fn_t sym_cb);
  46target_ulong riscv_load_kernel(const char *kernel_filename,
  47                               target_ulong firmware_end_addr,
  48                               symbol_fn_t sym_cb);
  49hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
  50                         uint64_t kernel_entry, hwaddr *start);
  51uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
  52void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
  53                               hwaddr saddr,
  54                               hwaddr rom_base, hwaddr rom_size,
  55                               uint64_t kernel_entry,
  56                               uint32_t fdt_load_addr, void *fdt);
  57void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
  58                                  hwaddr rom_size,
  59                                  uint32_t reset_vec_size,
  60                                  uint64_t kernel_entry);
  61
  62#endif /* RISCV_BOOT_H */
  63