LXR qemu/include/hw/ssi/npcm7xx

   1/*
   2 * Nuvoton NPCM7xx Flash Interface Unit (FIU)
   3 *
   4 * Copyright 2020 Google LLC
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14 * for more details.
  15 */
  16#ifndef NPCM7XX_FIU_H
  17#define NPCM7XX_FIU_H
  18
  19#include "hw/ssi/ssi.h"
  20#include "hw/sysbus.h"
  21
  22/*
  23 * Number of registers in our device state structure. Don't change this without
  24 * incrementing the version_id in the vmstate.
  25 */
  26#define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t))
  27
  28typedef struct NPCM7xxFIUState NPCM7xxFIUState;
  29
  30/**
  31 * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
  32 * @direct_access: Memory region for direct flash access.
  33 * @fiu: Pointer to flash controller shared state.
  34 */
  35typedef struct NPCM7xxFIUFlash {
  36    MemoryRegion direct_access;
  37    NPCM7xxFIUState *fiu;
  38} NPCM7xxFIUFlash;
  39
  40/**
  41 * NPCM7xxFIUState - Device state for one Flash Interface Unit.
  42 * @parent: System bus device.
  43 * @mmio: Memory region for register access.
  44 * @cs_count: Number of flash chips that may be connected to this module.
  45 * @active_cs: Currently active chip select, or -1 if no chip is selected.
  46 * @cs_lines: GPIO lines that may be wired to flash chips.
  47 * @flash: Array of @cs_count per-flash-chip state objects.
  48 * @spi: The SPI bus mastered by this controller.
  49 * @regs: Register contents.
  50 *
  51 * Each FIU has a shared bank of registers, and controls up to four chip
  52 * selects. Each chip select has a dedicated memory region which may be used to
  53 * read and write the flash connected to that chip select as if it were memory.
  54 */
  55struct NPCM7xxFIUState {
  56    SysBusDevice parent;
  57
  58    MemoryRegion mmio;
  59
  60    int32_t cs_count;
  61    int32_t active_cs;
  62    qemu_irq *cs_lines;
  63    NPCM7xxFIUFlash *flash;
  64
  65    SSIBus *spi;
  66
  67    uint32_t regs[NPCM7XX_FIU_NR_REGS];
  68};
  69
  70#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
  71#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
  72
  73#endif /* NPCM7XX_FIU_H */
  74