LXR qemu/include/hw/timer/a9gtimer.h

   1/*
   2 * Global peripheral timer block for ARM A9MP
   3 *
   4 * (C) 2013 Xilinx Inc.
   5 *
   6 * Written by François LEGAL
   7 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version
  12 * 2 of the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License along
  20 * with this program; if not, see <http://www.gnu.org/licenses/>.
  21 */
  22
  23#ifndef A9GTIMER_H
  24#define A9GTIMER_H
  25
  26#include "hw/sysbus.h"
  27#include "qom/object.h"
  28
  29#define A9_GTIMER_MAX_CPUS 4
  30
  31#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
  32OBJECT_DECLARE_SIMPLE_TYPE(A9GTimerState, A9_GTIMER)
  33
  34#define R_COUNTER_LO                0x00
  35#define R_COUNTER_HI                0x04
  36
  37#define R_CONTROL                   0x08
  38#define R_CONTROL_TIMER_ENABLE      (1 << 0)
  39#define R_CONTROL_COMP_ENABLE       (1 << 1)
  40#define R_CONTROL_IRQ_ENABLE        (1 << 2)
  41#define R_CONTROL_AUTO_INCREMENT    (1 << 3)
  42#define R_CONTROL_PRESCALER_SHIFT   8
  43#define R_CONTROL_PRESCALER_LEN     8
  44#define R_CONTROL_PRESCALER_MASK    (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
  45                                     R_CONTROL_PRESCALER_SHIFT)
  46
  47#define R_CONTROL_BANKED            (R_CONTROL_COMP_ENABLE | \
  48                                     R_CONTROL_IRQ_ENABLE | \
  49                                     R_CONTROL_AUTO_INCREMENT)
  50#define R_CONTROL_NEEDS_SYNC        (R_CONTROL_TIMER_ENABLE | \
  51                                     R_CONTROL_PRESCALER_MASK)
  52
  53#define R_INTERRUPT_STATUS          0x0C
  54#define R_COMPARATOR_LO             0x10
  55#define R_COMPARATOR_HI             0x14
  56#define R_AUTO_INCREMENT            0x18
  57
  58typedef struct A9GTimerPerCPU A9GTimerPerCPU;
  59
  60struct A9GTimerPerCPU {
  61    A9GTimerState *parent;
  62
  63    uint32_t control; /* only per cpu banked bits valid */
  64    uint64_t compare;
  65    uint32_t status;
  66    uint32_t inc;
  67
  68    MemoryRegion iomem;
  69    qemu_irq irq; /* PPI interrupts */
  70};
  71
  72struct A9GTimerState {
  73    /*< private >*/
  74    SysBusDevice parent_obj;
  75    /*< public >*/
  76
  77    MemoryRegion iomem;
  78    /* static props */
  79    uint32_t num_cpu;
  80
  81    QEMUTimer *timer;
  82
  83    uint64_t counter; /* current timer value */
  84
  85    uint64_t ref_counter;
  86    uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
  87    uint32_t control; /* only non per cpu banked bits valid */
  88
  89    A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
  90};
  91
  92typedef struct A9GTimerUpdate {
  93    uint64_t now;
  94    uint64_t new;
  95} A9GTimerUpdate;
  96
  97#endif /* A9GTIMER_H */
  98