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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qemu.h"
23#include "user-internals.h"
24#include "cpu_loop-common.h"
25#include "signal-common.h"
26#include "qemu/guest-random.h"
27#include "semihosting/common-semi.h"
28#include "target/arm/syndrome.h"
29
30#define get_user_code_u32(x, gaddr, env) \
31 ({ abi_long __r = get_user_u32((x), (gaddr)); \
32 if (!__r && bswap_code(arm_sctlr_b(env))) { \
33 (x) = bswap32(x); \
34 } \
35 __r; \
36 })
37
38#define get_user_code_u16(x, gaddr, env) \
39 ({ abi_long __r = get_user_u16((x), (gaddr)); \
40 if (!__r && bswap_code(arm_sctlr_b(env))) { \
41 (x) = bswap16(x); \
42 } \
43 __r; \
44 })
45
46#define get_user_data_u32(x, gaddr, env) \
47 ({ abi_long __r = get_user_u32((x), (gaddr)); \
48 if (!__r && arm_cpu_bswap_data(env)) { \
49 (x) = bswap32(x); \
50 } \
51 __r; \
52 })
53
54#define get_user_data_u16(x, gaddr, env) \
55 ({ abi_long __r = get_user_u16((x), (gaddr)); \
56 if (!__r && arm_cpu_bswap_data(env)) { \
57 (x) = bswap16(x); \
58 } \
59 __r; \
60 })
61
62#define put_user_data_u32(x, gaddr, env) \
63 ({ typeof(x) __x = (x); \
64 if (arm_cpu_bswap_data(env)) { \
65 __x = bswap32(__x); \
66 } \
67 put_user_u32(__x, (gaddr)); \
68 })
69
70#define put_user_data_u16(x, gaddr, env) \
71 ({ typeof(x) __x = (x); \
72 if (arm_cpu_bswap_data(env)) { \
73 __x = bswap16(__x); \
74 } \
75 put_user_u16(__x, (gaddr)); \
76 })
77
78
79void cpu_loop(CPUARMState *env)
80{
81 CPUState *cs = env_cpu(env);
82 int trapnr, ec, fsc, si_code, si_signo;
83 abi_long ret;
84
85 for (;;) {
86 cpu_exec_start(cs);
87 trapnr = cpu_exec(cs);
88 cpu_exec_end(cs);
89 process_queued_cpu_work(cs);
90
91 switch (trapnr) {
92 case EXCP_SWI:
93 ret = do_syscall(env,
94 env->xregs[8],
95 env->xregs[0],
96 env->xregs[1],
97 env->xregs[2],
98 env->xregs[3],
99 env->xregs[4],
100 env->xregs[5],
101 0, 0);
102 if (ret == -TARGET_ERESTARTSYS) {
103 env->pc -= 4;
104 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
105 env->xregs[0] = ret;
106 }
107 break;
108 case EXCP_INTERRUPT:
109
110 break;
111 case EXCP_UDEF:
112 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
113 break;
114 case EXCP_PREFETCH_ABORT:
115 case EXCP_DATA_ABORT:
116
117 ec = syn_get_ec(env->exception.syndrome);
118 assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
119
120
121 fsc = extract32(env->exception.syndrome, 0, 6);
122 switch (fsc) {
123 case 0x04 ... 0x07:
124 si_signo = TARGET_SIGSEGV;
125 si_code = TARGET_SEGV_MAPERR;
126 break;
127 case 0x09 ... 0x0b:
128 case 0x0d ... 0x0f:
129 si_signo = TARGET_SIGSEGV;
130 si_code = TARGET_SEGV_ACCERR;
131 break;
132 case 0x11:
133 si_signo = TARGET_SIGSEGV;
134 si_code = TARGET_SEGV_MTESERR;
135 break;
136 case 0x21:
137 si_signo = TARGET_SIGBUS;
138 si_code = TARGET_BUS_ADRALN;
139 break;
140 default:
141 g_assert_not_reached();
142 }
143 force_sig_fault(si_signo, si_code, env->exception.vaddress);
144 break;
145 case EXCP_DEBUG:
146 case EXCP_BKPT:
147 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
148 break;
149 case EXCP_SEMIHOST:
150 env->xregs[0] = do_common_semihosting(cs);
151 env->pc += 4;
152 break;
153 case EXCP_YIELD:
154
155 break;
156 case EXCP_ATOMIC:
157 cpu_exec_step_atomic(cs);
158 break;
159 default:
160 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
161 abort();
162 }
163
164
165 if (unlikely(env->cp15.tfsr_el[0])) {
166 env->cp15.tfsr_el[0] = 0;
167 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
168 }
169
170 process_pending_signals(env);
171
172
173
174 env->exclusive_addr = -1;
175 }
176}
177
178void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
179{
180 ARMCPU *cpu = env_archcpu(env);
181 CPUState *cs = env_cpu(env);
182 TaskState *ts = cs->opaque;
183 struct image_info *info = ts->info;
184 int i;
185
186 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
187 fprintf(stderr,
188 "The selected ARM CPU does not support 64 bit mode\n");
189 exit(EXIT_FAILURE);
190 }
191
192 for (i = 0; i < 31; i++) {
193 env->xregs[i] = regs->regs[i];
194 }
195 env->pc = regs->pc;
196 env->xregs[31] = regs->sp;
197#ifdef TARGET_WORDS_BIGENDIAN
198 env->cp15.sctlr_el[1] |= SCTLR_E0E;
199 for (i = 1; i < 4; ++i) {
200 env->cp15.sctlr_el[i] |= SCTLR_EE;
201 }
202 arm_rebuild_hflags(env);
203#endif
204
205 if (cpu_isar_feature(aa64_pauth, cpu)) {
206 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
207 }
208
209 ts->stack_base = info->start_stack;
210 ts->heap_base = info->brk;
211
212 ts->heap_limit = 0;
213}
214