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21#include "qemu/osdep.h"
22#include "fpa11.h"
23#include "fpu/softfloat.h"
24#include "fpopcode.h"
25#include "fpsr.h"
26
27
28
29const floatx80 floatx80Constant[] = {
30 { 0x0000000000000000ULL, 0x0000},
31 { 0x8000000000000000ULL, 0x3fff},
32 { 0x8000000000000000ULL, 0x4000},
33 { 0xc000000000000000ULL, 0x4000},
34 { 0x8000000000000000ULL, 0x4001},
35 { 0xa000000000000000ULL, 0x4001},
36 { 0x8000000000000000ULL, 0x3ffe},
37 { 0xa000000000000000ULL, 0x4002}
38};
39
40const float64 float64Constant[] = {
41 const_float64(0x0000000000000000ULL),
42 const_float64(0x3ff0000000000000ULL),
43 const_float64(0x4000000000000000ULL),
44 const_float64(0x4008000000000000ULL),
45 const_float64(0x4010000000000000ULL),
46 const_float64(0x4014000000000000ULL),
47 const_float64(0x3fe0000000000000ULL),
48 const_float64(0x4024000000000000ULL)
49};
50
51const float32 float32Constant[] = {
52 const_float32(0x00000000),
53 const_float32(0x3f800000),
54 const_float32(0x40000000),
55 const_float32(0x40400000),
56 const_float32(0x40800000),
57 const_float32(0x40a00000),
58 const_float32(0x3f000000),
59 const_float32(0x41200000)
60};
61
62unsigned int getRegisterCount(const unsigned int opcode)
63{
64 unsigned int nRc;
65
66 switch (opcode & MASK_REGISTER_COUNT)
67 {
68 case 0x00000000: nRc = 4; break;
69 case 0x00008000: nRc = 1; break;
70 case 0x00400000: nRc = 2; break;
71 case 0x00408000: nRc = 3; break;
72 default: nRc = 0;
73 }
74
75 return(nRc);
76}
77
78unsigned int getDestinationSize(const unsigned int opcode)
79{
80 unsigned int nRc;
81
82 switch (opcode & MASK_DESTINATION_SIZE)
83 {
84 case 0x00000000: nRc = typeSingle; break;
85 case 0x00000080: nRc = typeDouble; break;
86 case 0x00080000: nRc = typeExtended; break;
87 default: nRc = typeNone;
88 }
89
90 return(nRc);
91}
92