1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include "qemu/osdep.h"
21#include "qemu.h"
22#include "user-internals.h"
23#include "cpu_loop-common.h"
24#include "signal-common.h"
25
26static abi_ulong hppa_lws(CPUHPPAState *env)
27{
28 CPUState *cs = env_cpu(env);
29 uint32_t which = env->gr[20];
30 abi_ulong addr = env->gr[26];
31 abi_ulong old = env->gr[25];
32 abi_ulong new = env->gr[24];
33 abi_ulong size, ret;
34
35 switch (which) {
36 default:
37 return -TARGET_ENOSYS;
38
39 case 0:
40 if ((addr & 3) || !access_ok(cs, VERIFY_WRITE, addr, 4)) {
41 return -TARGET_EFAULT;
42 }
43 old = tswap32(old);
44 new = tswap32(new);
45 ret = qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new);
46 ret = tswap32(ret);
47 break;
48
49 case 2:
50 size = env->gr[23];
51 if (size >= 4) {
52 return -TARGET_ENOSYS;
53 }
54 if (((addr | old | new) & ((1 << size) - 1))
55 || !access_ok(cs, VERIFY_WRITE, addr, 1 << size)
56 || !access_ok(cs, VERIFY_READ, old, 1 << size)
57 || !access_ok(cs, VERIFY_READ, new, 1 << size)) {
58 return -TARGET_EFAULT;
59 }
60
61
62 switch (size) {
63 case 0:
64 old = *(uint8_t *)g2h(cs, old);
65 new = *(uint8_t *)g2h(cs, new);
66 ret = qatomic_cmpxchg((uint8_t *)g2h(cs, addr), old, new);
67 ret = ret != old;
68 break;
69 case 1:
70 old = *(uint16_t *)g2h(cs, old);
71 new = *(uint16_t *)g2h(cs, new);
72 ret = qatomic_cmpxchg((uint16_t *)g2h(cs, addr), old, new);
73 ret = ret != old;
74 break;
75 case 2:
76 old = *(uint32_t *)g2h(cs, old);
77 new = *(uint32_t *)g2h(cs, new);
78 ret = qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new);
79 ret = ret != old;
80 break;
81 case 3:
82 {
83 uint64_t o64, n64, r64;
84 o64 = *(uint64_t *)g2h(cs, old);
85 n64 = *(uint64_t *)g2h(cs, new);
86#ifdef CONFIG_ATOMIC64
87 r64 = qatomic_cmpxchg__nocheck((aligned_uint64_t *)g2h(cs, addr),
88 o64, n64);
89 ret = r64 != o64;
90#else
91 start_exclusive();
92 r64 = *(uint64_t *)g2h(cs, addr);
93 ret = 1;
94 if (r64 == o64) {
95 *(uint64_t *)g2h(cs, addr) = n64;
96 ret = 0;
97 }
98 end_exclusive();
99#endif
100 }
101 break;
102 }
103 break;
104 }
105
106 env->gr[28] = ret;
107 return 0;
108}
109
110void cpu_loop(CPUHPPAState *env)
111{
112 CPUState *cs = env_cpu(env);
113 target_siginfo_t info;
114 abi_ulong ret;
115 int trapnr;
116
117 while (1) {
118 cpu_exec_start(cs);
119 trapnr = cpu_exec(cs);
120 cpu_exec_end(cs);
121 process_queued_cpu_work(cs);
122
123 switch (trapnr) {
124 case EXCP_SYSCALL:
125 ret = do_syscall(env, env->gr[20],
126 env->gr[26], env->gr[25],
127 env->gr[24], env->gr[23],
128 env->gr[22], env->gr[21], 0, 0);
129 switch (ret) {
130 default:
131 env->gr[28] = ret;
132
133 env->iaoq_f = env->gr[31];
134 env->iaoq_b = env->gr[31] + 4;
135 break;
136 case -TARGET_ERESTARTSYS:
137 case -TARGET_QEMU_ESIGRETURN:
138 break;
139 }
140 break;
141 case EXCP_SYSCALL_LWS:
142 env->gr[21] = hppa_lws(env);
143
144 env->iaoq_f = env->gr[31];
145 env->iaoq_b = env->gr[31] + 4;
146 break;
147 case EXCP_ILL:
148 case EXCP_PRIV_OPR:
149 case EXCP_PRIV_REG:
150 info.si_signo = TARGET_SIGILL;
151 info.si_errno = 0;
152 info.si_code = TARGET_ILL_ILLOPN;
153 info._sifields._sigfault._addr = env->iaoq_f;
154 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
155 break;
156 case EXCP_OVERFLOW:
157 case EXCP_COND:
158 case EXCP_ASSIST:
159 info.si_signo = TARGET_SIGFPE;
160 info.si_errno = 0;
161 info.si_code = 0;
162 info._sifields._sigfault._addr = env->iaoq_f;
163 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
164 break;
165 case EXCP_DEBUG:
166 info.si_signo = TARGET_SIGTRAP;
167 info.si_errno = 0;
168 info.si_code = TARGET_TRAP_BRKPT;
169 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
170 break;
171 case EXCP_INTERRUPT:
172
173 break;
174 default:
175 g_assert_not_reached();
176 }
177 process_pending_signals(env);
178 }
179}
180
181void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
182{
183 int i;
184 for (i = 1; i < 32; i++) {
185 env->gr[i] = regs->gr[i];
186 }
187 env->iaoq_f = regs->iaoq[0];
188 env->iaoq_b = regs->iaoq[1];
189}
190