1\xD0 \xFE\xED&\x9A8(\x92\xD0xlnx,microblaze&edk131memory@50000000,memory8Paliases</axi/axi-ethernet@82780000F/axi/serial@83e00000chosenN console=ttyS0,115200 W/axi/serial@83e00000cpusccpu@0i\xEB\xC2xlnx,microblaze-8.10.ayP\x8A_\xFF\xFF\xFF\x9B \xAD,cpu\xBAP\xCB_\xFF\xFF\xFF\xDC \xEEµblaze,8.10.a8\xFB\xEB\xC2!6K_}\x92\x9D\xA8\xB3 \xC2\xD7\xEF9Odx\x92\xA6\xB9\xD1\xE9)virtex65I\\xEB\xC2f y\x8C\x9B\xA6\xB1\xBC\xD4\xEB3G[o \x89microblaze_0\x97\xA9\xC0\xD3\xE6#9To\x87\x99\xA2\xB1\xC0\xCF\xD8\xF18HUfz\x96\xA3\xB3\xC3\xD6\xE3\xF6 2axi(xlnx,axi-interconnect-1.02.asimple-bus$axi-ethernet@82780000+2xlnx,axi-ethernet-2.01.axlnx,axi-ethernet-1.00.a,network?P[ 35"m8\x82xx\x81\x8E\x9E\xB0\xBE0B00001\xCB\xD7\xE2\xF3+6GWhmdiophy@7marvell,88e1111 ,ethernet-phy8raxi-dma@84600000xlnx,axi-dma-3.00.a?P8\x84`z\xE2)virtex6\x91\xA3\xB9\xCB\xE1\xF6 $ ? ] rrserial@83e00000i\xF5\xE1=xlnx,axi-uart16550-1.01.axlnx,xps-uart16550-2.00.ans16550a \x8C%\x80,serial?P8\x83\xE0 \x9A \xA5 \xAF}x@)virtex6 \xC8 \xDF \xF5 4 5system-timer@83c00000i\xF5\xE1,xlnx,axi-timer-1.01.axlnx,xps-timer-1.00.a?P8\x83\xC0 6. )virtex6 7? 8P 9a 10u 11\x87interrupt-controller@81800000 12\x99*xlnx,axi-intc-1.01.axlnx,xps-intc-1.00.a 13\xAA8\x81\x80 14\xBF 15\xD1rflash@86000000 16\xE6xlnx,axi-emc-1.01.acfi-flash8\x86 17\xF1')virtex6*Ln\x90\xAC\xBF\xCE\xDE\xED \xFD + ;Ne|\x93\xAA\xBC \xD6 \xF0 AXI4LITE : Taxi4 l \x83 \x9A \xB1 \xC8\xFB\xD0 \xDC:\x98 \xF0:\x98:\x98\xFB\xD0,:\x98@:\x98T:\x98h\x88\xB8|X\x90X\xA4X\xB8X\xCCX\xE0X\xF4X\x88\xB80DXa\xA8na\xA8\x84a\xA8\x9Aa\xA8\xB02\xC8\xC2:\x98\xD4:\x98\xE6:\x98\xF8p 18.\xE0.\xE0..\xE0@.\xE0S.\xE0f.\xE0y.\xE0partition@0\x8Cfpga8partition@100000\x8Cboot8partition@140000\x8Cbootenv8partition@160000\x8Cconfig8partition@180000\x8Cimage8\xA0partition@b80000\x8Cspare8\xB8 #address-cells#size-cellscompatiblemodeldevice_typeregethernet0serial0bootargsstdout-path#cpusclock-frequencyd-cache-baseaddrd-cache-highaddrd-cache-line-sized-cache-sizei-cache-baseaddri-cache-highaddri-cache-line-sizei-cache-sizetimebase-frequencyxlnx,addr-tag-bitsxlnx,allow-dcache-wrxlnx,allow-icache-wrxlnx,area-optimizedxlnx,branch-target-cache-sizexlnx,cache-byte-sizexlnx,d-axixlnx,d-lmbxlnx,d-plbxlnx,data-sizexlnx,dcache-addr-tagxlnx,dcache-always-usedxlnx,dcache-byte-sizexlnx,dcache-data-widthxlnx,dcache-force-tag-lutramxlnx,dcache-interfacexlnx,dcache-line-lenxlnx,dcache-use-fslxlnx,dcache-use-writebackxlnx,dcache-victimsxlnx,debug-enabledxlnx,div-zero-exceptionxlnx,dynamic-bus-sizingxlnx,ecc-use-ce-exceptionxlnx,edge-is-positivexlnx,endiannessxlnx,familyxlnx,fault-tolerantxlnx,fpu-exceptionxlnx,freqxlnx,fsl-data-sizexlnx,fsl-exceptionxlnx,fsl-linksxlnx,i-axixlnx,i-lmbxlnx,i-plbxlnx,icache-always-usedxlnx,icache-data-widthxlnx,icache-force-tag-lutramxlnx,icache-interfacexlnx,icache-line-lenxlnx,icache-streamsxlnx,icache-use-fslxlnx,icache-victimsxlnx,ill-opcode-exceptionxlnx,instancexlnx,interconnectxlnx,interrupt-is-edgexlnx,mmu-dtlb-sizexlnx,mmu-itlb-sizexlnx,mmu-privileged-instrxlnx,mmu-tlb-accessxlnx,mmu-zonesxlnx,number-of-pc-brkxlnx,number-of-rd-addr-brkxlnx,number-of-wr-addr-brkxlnx,opcode-0x0-illegalxlnx,optimizationxlnx,pvrxlnx,pvr-user1xlnx,pvr-user2xlnx,reset-msrxlnx,scoxlnx,stream-interconnectxlnx,unaligned-exceptionsxlnx,use-barrelxlnx,use-branch-target-cachexlnx,use-dcachexlnx,use-divxlnx,use-ext-brkxlnx,use-ext-nm-brkxlnx,use-extended-fsl-instrxlnx,use-fpuxlnx,use-hw-mulxlnx,use-icachexlnx,use-interruptxlnx,use-mmuxlnx,use-msr-instrxlnx,use-pcmp-instrxlnx,use-stack-protectionrangesaxistream-connectedinterrupt-parentinterruptslocal-mac-addressphy-handlexlnx,avbxlnx,halfdupxlnx,include-ioxlnx,mcast-extendxlnx,phy-typexlnx,phyaddrxlnx,rxcsumxlnx,rxmemxlnx,rxvlan-strpxlnx,rxvlan-tagxlnx,rxvlan-tranxlnx,statsxlnx,txcsumxlnx,txmemxlnx,txvlan-strpxlnx,txvlan-tagxlnx,txvlan-tranxlnx,typephandlexlnx,dlytmr-resolutionxlnx,include-mm2sxlnx,include-mm2s-drexlnx,include-s2mmxlnx,include-s2mm-drexlnx,mm2s-burst-sizexlnx,prmry-is-aclk-asyncxlnx,s2mm-burst-sizexlnx,sg-include-desc-queuexlnx,sg-include-stscntrl-strmxlnx,sg-length-widthxlnx,sg-use-stsapp-lengthcurrent-speedreg-offsetreg-shiftxlnx,external-xin-clk-hzxlnx,has-external-rclkxlnx,has-external-xinxlnx,is-a-16550xlnx,use-modem-portsxlnx,use-user-portsxlnx,count-widthxlnx,gen0-assertxlnx,gen1-assertxlnx,one-timer-onlyxlnx,trig0-assertxlnx,trig1-assert#interrupt-cellsinterrupt-controllerxlnx,kind-of-intrxlnx,num-intr-inputsbank-widthxlnx,axi-clk-period-psxlnx,include-datawidth-matching-0xlnx,include-datawidth-matching-1xlnx,include-datawidth-matching-2xlnx,include-datawidth-matching-3xlnx,include-negedge-ioregsxlnx,max-mem-widthxlnx,mem0-typexlnx,mem0-widthxlnx,mem1-typexlnx,mem1-widthxlnx,mem2-typexlnx,mem2-widthxlnx,mem3-typexlnx,mem3-widthxlnx,num-banks-memxlnx,parity-type-mem-0xlnx,parity-type-mem-1xlnx,parity-type-mem-2xlnx,parity-type-mem-3xlnx,s-axi-en-regxlnx,s-axi-mem-addr-widthxlnx,s-axi-mem-data-widthxlnx,s-axi-mem-id-widthxlnx,s-axi-mem-protocolxlnx,s-axi-reg-addr-widthxlnx,s-axi-reg-data-widthxlnx,s-axi-reg-protocolxlnx,synch-pipedelay-0xlnx,synch-pipedelay-1xlnx,synch-pipedelay-2xlnx,synch-pipedelay-3xlnx,tavdv-ps-mem-0xlnx,tavdv-ps-mem-1xlnx,tavdv-ps-mem-2xlnx,tavdv-ps-mem-3xlnx,tcedv-ps-mem-0xlnx,tcedv-ps-mem-1xlnx,tcedv-ps-mem-2xlnx,tcedv-ps-mem-3xlnx,thzce-ps-mem-0xlnx,thzce-ps-mem-1xlnx,thzce-ps-mem-2xlnx,thzce-ps-mem-3xlnx,thzoe-ps-mem-0xlnx,thzoe-ps-mem-1xlnx,thzoe-ps-mem-2xlnx,thzoe-ps-mem-3xlnx,tlzwe-ps-mem-0xlnx,tlzwe-ps-mem-1xlnx,tlzwe-ps-mem-2xlnx,tlzwe-ps-mem-3xlnx,tpacc-ps-flash-0xlnx,tpacc-ps-flash-1xlnx,tpacc-ps-flash-2xlnx,tpacc-ps-flash-3xlnx,twc-ps-mem-0xlnx,twc-ps-mem-1xlnx,twc-ps-mem-2xlnx,twc-ps-mem-3xlnx,twp-ps-mem-0xlnx,twp-ps-mem-1xlnx,twp-ps-mem-2xlnx,twp-ps-mem-3xlnx,twph-ps-mem-0xlnx,twph-ps-mem-1xlnx,twph-ps-mem-2xlnx,twph-ps-mem-3label