1\xD0 \xFE\xED\xE18\xB4(-|xlnx,microblaze&testingmemory@90000000,memory8\x90chosen<console=ttyUL0,115200E/plb/serial@84000000cpusQcpu@0W\xB9\xAC\xA0xlnx,microblaze-7.10.dg\x90x\x97\xFF\xFF\xFF\x89\x9B,cpu\xA8\x90\xB9\x97\xFF\xFF\xFF\xCA\xDCµblaze,7.10.d8\xE9\xB9\xAC\xA0\xFC$9Mbmx\x83 \x92\xA7\xBF\xD5\xEA\xFE)AY ospartan3adsp{\x8E \xA1\xB4\xC3\xCE\xD9\xE4\xFC% ?microblaze_0M_v\x8E\xA1\xB4\xC8\xD7\xED#;DSbqz\x94\xA4\xB4\xC1\xD2\xE6/BObplbxlnx,plb-v46-1.03.asimple-busvethernet@81000000xlnx,xps-ethernetlite-2.00.a,network}\x8E\x998\x81\xAB ospartan3adsp\xB7\xC9flash@a0000000\xDB"xlnx,xps-mch-emc-2.00.acfi-flash8\xA0 ospartan3adsp\xE6*Ln\x8A\xA0\xB3\xC6 \xDD>\x80\xF8 ':Tn\x81\x9B\xB5\xC8\xE2\xFC)9 I Y i|\x8E\xA1\xB2\xC3\xD4\xE5\xFC * Ap U:\x98 i:\x98 }:\x98 \x91p \xA5:\x98 \xB9:\x98 \xCD:\x98 \xE1a\xA8 \xF5X 2 X 3X 41a\xA8 5EX 6YX 7mX 8\x81\x88 9\x95 10\xA9 11\xBD 12\xD1p 13\xE3:\x98 14\xF5:\x98:\x98\xAF\xC8+.\xE0=.\xE0O.\xE0at\x88\x9B\xAF\xC2\xD6\xE9gpio@81400000xlnx,xps-gpio-1.00.a}\x8E8\x81@\xFD 1 ospartan3adspEUlz\x8A\x97\xFF\xFF\xFF\xFF\xA8\xFF\xFF\xFF\xFFserial@84000000W\xB9\xAC\xA0xlnx,xps-uartlite-1.00.a\xBB\xC2,serial}\x8E\xC98\x84\xD5\xC2\xE3 ospartan3adsp\xF2 debug@84400000xlnx,mdm-1.00.d8\x84@ ospartan3adspM " 4 D Rinterrupt-controller@81800000 gxlnx,xps-intc-1.00.a x8\x81\x80 \x8D 15 \x9F \xB4timer@83c00000xlnx,xps-timer-1.00.a}\x8E8\x83\xC0 \xC2 ospartan3adsp \xD3 \xE4 \xF5 #address-cells#size-cellscompatiblemodeldevice_typeregbootargsstdout-path#cpusclock-frequencyd-cache-baseaddrd-cache-highaddrd-cache-line-sized-cache-sizei-cache-baseaddri-cache-highaddri-cache-line-sizei-cache-sizetimebase-frequencyxlnx,addr-tag-bitsxlnx,allow-dcache-wrxlnx,allow-icache-wrxlnx,area-optimizedxlnx,cache-byte-sizexlnx,d-lmbxlnx,d-opbxlnx,d-plbxlnx,data-sizexlnx,dcache-addr-tagxlnx,dcache-always-usedxlnx,dcache-byte-sizexlnx,dcache-line-lenxlnx,dcache-use-fslxlnx,debug-enabledxlnx,div-zero-exceptionxlnx,dopb-bus-exceptionxlnx,dynamic-bus-sizingxlnx,edge-is-positivexlnx,familyxlnx,fpu-exceptionxlnx,fsl-data-sizexlnx,fsl-exceptionxlnx,fsl-linksxlnx,i-lmbxlnx,i-opbxlnx,i-plbxlnx,icache-always-usedxlnx,icache-line-lenxlnx,icache-use-fslxlnx,ill-opcode-exceptionxlnx,instancexlnx,interconnectxlnx,interrupt-is-edgexlnx,iopb-bus-exceptionxlnx,mmu-dtlb-sizexlnx,mmu-itlb-sizexlnx,mmu-tlb-accessxlnx,mmu-zonesxlnx,number-of-pc-brkxlnx,number-of-rd-addr-brkxlnx,number-of-wr-addr-brkxlnx,opcode-0x0-illegalxlnx,pvrxlnx,pvr-user1xlnx,pvr-user2xlnx,reset-msrxlnx,scoxlnx,unaligned-exceptionsxlnx,use-barrelxlnx,use-dcachexlnx,use-divxlnx,use-ext-brkxlnx,use-ext-nm-brkxlnx,use-extended-fsl-instrxlnx,use-fpuxlnx,use-hw-mulxlnx,use-icachexlnx,use-interruptxlnx,use-mmuxlnx,use-msr-instrxlnx,use-pcmp-instrrangesinterrupt-parentinterruptslocal-mac-addressxlnx,duplexxlnx,rx-ping-pongxlnx,tx-ping-pongbank-widthxlnx,include-datawidth-matching-0xlnx,include-datawidth-matching-1xlnx,include-datawidth-matching-2xlnx,include-datawidth-matching-3xlnx,include-negedge-ioregsxlnx,include-plb-ipifxlnx,include-wrbufxlnx,max-mem-widthxlnx,mch-native-dwidthxlnx,mch-plb-clk-period-psxlnx,mch-splb-awidthxlnx,mch0-accessbuf-depthxlnx,mch0-protocolxlnx,mch0-rddatabuf-depthxlnx,mch1-accessbuf-depthxlnx,mch1-protocolxlnx,mch1-rddatabuf-depthxlnx,mch2-accessbuf-depthxlnx,mch2-protocolxlnx,mch2-rddatabuf-depthxlnx,mch3-accessbuf-depthxlnx,mch3-protocolxlnx,mch3-rddatabuf-depthxlnx,mem0-widthxlnx,mem1-widthxlnx,mem2-widthxlnx,mem3-widthxlnx,num-banks-memxlnx,num-channelsxlnx,priority-modexlnx,synch-mem-0xlnx,synch-mem-1xlnx,synch-mem-2xlnx,synch-mem-3xlnx,synch-pipedelay-0xlnx,synch-pipedelay-1xlnx,synch-pipedelay-2xlnx,synch-pipedelay-3xlnx,tavdv-ps-mem-0xlnx,tavdv-ps-mem-1xlnx,tavdv-ps-mem-2xlnx,tavdv-ps-mem-3xlnx,tcedv-ps-mem-0xlnx,tcedv-ps-mem-1xlnx,tcedv-ps-mem-2xlnx,tcedv-ps-mem-3xlnx,thzce-ps-mem-0xlnx,thzce-ps-mem-1xlnx,thzce-ps-mem-2xlnx,thzce-ps-mem-3xlnx,thzoe-ps-mem-0xlnx,thzoe-ps-mem-1xlnx,thzoe-ps-mem-2xlnx,thzoe-ps-mem-3xlnx,tlzwe-ps-mem-0xlnx,tlzwe-ps-mem-1xlnx,tlzwe-ps-mem-2xlnx,tlzwe-ps-mem-3xlnx,twc-ps-mem-0xlnx,twc-ps-mem-1xlnx,twc-ps-mem-2xlnx,twc-ps-mem-3xlnx,twp-ps-mem-0xlnx,twp-ps-mem-1xlnx,twp-ps-mem-2xlnx,twp-ps-mem-3xlnx,xcl0-linesizexlnx,xcl0-writexferxlnx,xcl1-linesizexlnx,xcl1-writexferxlnx,xcl2-linesizexlnx,xcl2-writexferxlnx,xcl3-linesizexlnx,xcl3-writexferxlnx,all-inputsxlnx,all-inputs-2xlnx,dout-defaultxlnx,dout-default-2xlnx,gpio-widthxlnx,interrupt-presentxlnx,is-bidirxlnx,is-bidir-2xlnx,is-dualxlnx,tri-defaultxlnx,tri-default-2current-speedport-numberxlnx,baudratexlnx,data-bitsxlnx,odd-parityxlnx,use-parityxlnx,jtag-chainxlnx,mb-dbg-portsxlnx,uart-widthxlnx,use-uartxlnx,write-fsl-ports#interrupt-cellsinterrupt-controllerxlnx,kind-of-intrxlnx,num-intr-inputslinux,phandlexlnx,count-widthxlnx,gen0-assertxlnx,gen1-assertxlnx,one-timer-onlyxlnx,trig0-assertxlnx,trig1-assert