qemu/target/arm/cpu.c
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   1/*
   2 * QEMU ARM CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see
  18 * <http://www.gnu.org/licenses/gpl-2.0.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qemu/qemu-print.h"
  23#include "qemu-common.h"
  24#include "target/arm/idau.h"
  25#include "qemu/module.h"
  26#include "qapi/error.h"
  27#include "qapi/visitor.h"
  28#include "cpu.h"
  29#include "internals.h"
  30#include "exec/exec-all.h"
  31#include "hw/qdev-properties.h"
  32#if !defined(CONFIG_USER_ONLY)
  33#include "hw/loader.h"
  34#include "hw/boards.h"
  35#endif
  36#include "sysemu/sysemu.h"
  37#include "sysemu/tcg.h"
  38#include "sysemu/hw_accel.h"
  39#include "kvm_arm.h"
  40#include "disas/capstone.h"
  41#include "fpu/softfloat.h"
  42
  43static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  44{
  45    ARMCPU *cpu = ARM_CPU(cs);
  46    CPUARMState *env = &cpu->env;
  47
  48    if (is_a64(env)) {
  49        env->pc = value;
  50        env->thumb = 0;
  51    } else {
  52        env->regs[15] = value & ~1;
  53        env->thumb = value & 1;
  54    }
  55}
  56
  57static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  58{
  59    ARMCPU *cpu = ARM_CPU(cs);
  60    CPUARMState *env = &cpu->env;
  61
  62    /*
  63     * It's OK to look at env for the current mode here, because it's
  64     * never possible for an AArch64 TB to chain to an AArch32 TB.
  65     */
  66    if (is_a64(env)) {
  67        env->pc = tb->pc;
  68    } else {
  69        env->regs[15] = tb->pc;
  70    }
  71}
  72
  73static bool arm_cpu_has_work(CPUState *cs)
  74{
  75    ARMCPU *cpu = ARM_CPU(cs);
  76
  77    return (cpu->power_state != PSCI_OFF)
  78        && cs->interrupt_request &
  79        (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  80         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  81         | CPU_INTERRUPT_EXITTB);
  82}
  83
  84void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  85                                 void *opaque)
  86{
  87    ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  88
  89    entry->hook = hook;
  90    entry->opaque = opaque;
  91
  92    QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
  93}
  94
  95void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  96                                 void *opaque)
  97{
  98    ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  99
 100    entry->hook = hook;
 101    entry->opaque = opaque;
 102
 103    QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
 104}
 105
 106static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
 107{
 108    /* Reset a single ARMCPRegInfo register */
 109    ARMCPRegInfo *ri = value;
 110    ARMCPU *cpu = opaque;
 111
 112    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
 113        return;
 114    }
 115
 116    if (ri->resetfn) {
 117        ri->resetfn(&cpu->env, ri);
 118        return;
 119    }
 120
 121    /* A zero offset is never possible as it would be regs[0]
 122     * so we use it to indicate that reset is being handled elsewhere.
 123     * This is basically only used for fields in non-core coprocessors
 124     * (like the pxa2xx ones).
 125     */
 126    if (!ri->fieldoffset) {
 127        return;
 128    }
 129
 130    if (cpreg_field_is_64bit(ri)) {
 131        CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
 132    } else {
 133        CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
 134    }
 135}
 136
 137static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
 138{
 139    /* Purely an assertion check: we've already done reset once,
 140     * so now check that running the reset for the cpreg doesn't
 141     * change its value. This traps bugs where two different cpregs
 142     * both try to reset the same state field but to different values.
 143     */
 144    ARMCPRegInfo *ri = value;
 145    ARMCPU *cpu = opaque;
 146    uint64_t oldvalue, newvalue;
 147
 148    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 149        return;
 150    }
 151
 152    oldvalue = read_raw_cp_reg(&cpu->env, ri);
 153    cp_reg_reset(key, value, opaque);
 154    newvalue = read_raw_cp_reg(&cpu->env, ri);
 155    assert(oldvalue == newvalue);
 156}
 157
 158/* CPUClass::reset() */
 159static void arm_cpu_reset(CPUState *s)
 160{
 161    ARMCPU *cpu = ARM_CPU(s);
 162    ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 163    CPUARMState *env = &cpu->env;
 164
 165    acc->parent_reset(s);
 166
 167    memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 168
 169    g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 170    g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 171
 172    env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 173    env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
 174    env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
 175    env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
 176
 177    cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
 178    s->halted = cpu->start_powered_off;
 179
 180    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 181        env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 182    }
 183
 184    if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 185        /* 64 bit CPUs always start in 64 bit mode */
 186        env->aarch64 = 1;
 187#if defined(CONFIG_USER_ONLY)
 188        env->pstate = PSTATE_MODE_EL0t;
 189        /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 190        env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 191        /* Enable all PAC keys.  */
 192        env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
 193                                  SCTLR_EnDA | SCTLR_EnDB);
 194        /* Enable all PAC instructions */
 195        env->cp15.hcr_el2 |= HCR_API;
 196        env->cp15.scr_el3 |= SCR_API;
 197        /* and to the FP/Neon instructions */
 198        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 199        /* and to the SVE instructions */
 200        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
 201        env->cp15.cptr_el[3] |= CPTR_EZ;
 202        /* with maximum vector length */
 203        env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
 204        env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
 205        env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
 206        /*
 207         * Enable TBI0 and TBI1.  While the real kernel only enables TBI0,
 208         * turning on both here will produce smaller code and otherwise
 209         * make no difference to the user-level emulation.
 210         */
 211        env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
 212#else
 213        /* Reset into the highest available EL */
 214        if (arm_feature(env, ARM_FEATURE_EL3)) {
 215            env->pstate = PSTATE_MODE_EL3h;
 216        } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 217            env->pstate = PSTATE_MODE_EL2h;
 218        } else {
 219            env->pstate = PSTATE_MODE_EL1h;
 220        }
 221        env->pc = cpu->rvbar;
 222#endif
 223    } else {
 224#if defined(CONFIG_USER_ONLY)
 225        /* Userspace expects access to cp10 and cp11 for FP/Neon */
 226        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 227#endif
 228    }
 229
 230#if defined(CONFIG_USER_ONLY)
 231    env->uncached_cpsr = ARM_CPU_MODE_USR;
 232    /* For user mode we must enable access to coprocessors */
 233    env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 234    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 235        env->cp15.c15_cpar = 3;
 236    } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 237        env->cp15.c15_cpar = 1;
 238    }
 239#else
 240
 241    /*
 242     * If the highest available EL is EL2, AArch32 will start in Hyp
 243     * mode; otherwise it starts in SVC. Note that if we start in
 244     * AArch64 then these values in the uncached_cpsr will be ignored.
 245     */
 246    if (arm_feature(env, ARM_FEATURE_EL2) &&
 247        !arm_feature(env, ARM_FEATURE_EL3)) {
 248        env->uncached_cpsr = ARM_CPU_MODE_HYP;
 249    } else {
 250        env->uncached_cpsr = ARM_CPU_MODE_SVC;
 251    }
 252    env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 253
 254    if (arm_feature(env, ARM_FEATURE_M)) {
 255        uint32_t initial_msp; /* Loaded from 0x0 */
 256        uint32_t initial_pc; /* Loaded from 0x4 */
 257        uint8_t *rom;
 258        uint32_t vecbase;
 259
 260        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 261            env->v7m.secure = true;
 262        } else {
 263            /* This bit resets to 0 if security is supported, but 1 if
 264             * it is not. The bit is not present in v7M, but we set it
 265             * here so we can avoid having to make checks on it conditional
 266             * on ARM_FEATURE_V8 (we don't let the guest see the bit).
 267             */
 268            env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
 269            /*
 270             * Set NSACR to indicate "NS access permitted to everything";
 271             * this avoids having to have all the tests of it being
 272             * conditional on ARM_FEATURE_M_SECURITY. Note also that from
 273             * v8.1M the guest-visible value of NSACR in a CPU without the
 274             * Security Extension is 0xcff.
 275             */
 276            env->v7m.nsacr = 0xcff;
 277        }
 278
 279        /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
 280         * that it resets to 1, so QEMU always does that rather than making
 281         * it dependent on CPU model. In v8M it is RES1.
 282         */
 283        env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
 284        env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
 285        if (arm_feature(env, ARM_FEATURE_V8)) {
 286            /* in v8M the NONBASETHRDENA bit [0] is RES1 */
 287            env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 288            env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 289        }
 290        if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
 291            env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 292            env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 293        }
 294
 295        if (arm_feature(env, ARM_FEATURE_VFP)) {
 296            env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
 297            env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
 298                R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
 299        }
 300        /* Unlike A/R profile, M profile defines the reset LR value */
 301        env->regs[14] = 0xffffffff;
 302
 303        env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
 304
 305        /* Load the initial SP and PC from offset 0 and 4 in the vector table */
 306        vecbase = env->v7m.vecbase[env->v7m.secure];
 307        rom = rom_ptr(vecbase, 8);
 308        if (rom) {
 309            /* Address zero is covered by ROM which hasn't yet been
 310             * copied into physical memory.
 311             */
 312            initial_msp = ldl_p(rom);
 313            initial_pc = ldl_p(rom + 4);
 314        } else {
 315            /* Address zero not covered by a ROM blob, or the ROM blob
 316             * is in non-modifiable memory and this is a second reset after
 317             * it got copied into memory. In the latter case, rom_ptr
 318             * will return a NULL pointer and we should use ldl_phys instead.
 319             */
 320            initial_msp = ldl_phys(s->as, vecbase);
 321            initial_pc = ldl_phys(s->as, vecbase + 4);
 322        }
 323
 324        env->regs[13] = initial_msp & 0xFFFFFFFC;
 325        env->regs[15] = initial_pc & ~1;
 326        env->thumb = initial_pc & 1;
 327    }
 328
 329    /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 330     * executing as AArch32 then check if highvecs are enabled and
 331     * adjust the PC accordingly.
 332     */
 333    if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 334        env->regs[15] = 0xFFFF0000;
 335    }
 336
 337    /* M profile requires that reset clears the exclusive monitor;
 338     * A profile does not, but clearing it makes more sense than having it
 339     * set with an exclusive access on address zero.
 340     */
 341    arm_clear_exclusive(env);
 342
 343    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 344#endif
 345
 346    if (arm_feature(env, ARM_FEATURE_PMSA)) {
 347        if (cpu->pmsav7_dregion > 0) {
 348            if (arm_feature(env, ARM_FEATURE_V8)) {
 349                memset(env->pmsav8.rbar[M_REG_NS], 0,
 350                       sizeof(*env->pmsav8.rbar[M_REG_NS])
 351                       * cpu->pmsav7_dregion);
 352                memset(env->pmsav8.rlar[M_REG_NS], 0,
 353                       sizeof(*env->pmsav8.rlar[M_REG_NS])
 354                       * cpu->pmsav7_dregion);
 355                if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 356                    memset(env->pmsav8.rbar[M_REG_S], 0,
 357                           sizeof(*env->pmsav8.rbar[M_REG_S])
 358                           * cpu->pmsav7_dregion);
 359                    memset(env->pmsav8.rlar[M_REG_S], 0,
 360                           sizeof(*env->pmsav8.rlar[M_REG_S])
 361                           * cpu->pmsav7_dregion);
 362                }
 363            } else if (arm_feature(env, ARM_FEATURE_V7)) {
 364                memset(env->pmsav7.drbar, 0,
 365                       sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
 366                memset(env->pmsav7.drsr, 0,
 367                       sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
 368                memset(env->pmsav7.dracr, 0,
 369                       sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
 370            }
 371        }
 372        env->pmsav7.rnr[M_REG_NS] = 0;
 373        env->pmsav7.rnr[M_REG_S] = 0;
 374        env->pmsav8.mair0[M_REG_NS] = 0;
 375        env->pmsav8.mair0[M_REG_S] = 0;
 376        env->pmsav8.mair1[M_REG_NS] = 0;
 377        env->pmsav8.mair1[M_REG_S] = 0;
 378    }
 379
 380    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 381        if (cpu->sau_sregion > 0) {
 382            memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
 383            memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
 384        }
 385        env->sau.rnr = 0;
 386        /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
 387         * the Cortex-M33 does.
 388         */
 389        env->sau.ctrl = 0;
 390    }
 391
 392    set_flush_to_zero(1, &env->vfp.standard_fp_status);
 393    set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 394    set_default_nan_mode(1, &env->vfp.standard_fp_status);
 395    set_float_detect_tininess(float_tininess_before_rounding,
 396                              &env->vfp.fp_status);
 397    set_float_detect_tininess(float_tininess_before_rounding,
 398                              &env->vfp.standard_fp_status);
 399    set_float_detect_tininess(float_tininess_before_rounding,
 400                              &env->vfp.fp_status_f16);
 401#ifndef CONFIG_USER_ONLY
 402    if (kvm_enabled()) {
 403        kvm_arm_reset_vcpu(cpu);
 404    }
 405#endif
 406
 407    hw_breakpoint_update_all(cpu);
 408    hw_watchpoint_update_all(cpu);
 409}
 410
 411bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 412{
 413    CPUClass *cc = CPU_GET_CLASS(cs);
 414    CPUARMState *env = cs->env_ptr;
 415    uint32_t cur_el = arm_current_el(env);
 416    bool secure = arm_is_secure(env);
 417    uint32_t target_el;
 418    uint32_t excp_idx;
 419    bool ret = false;
 420
 421    if (interrupt_request & CPU_INTERRUPT_FIQ) {
 422        excp_idx = EXCP_FIQ;
 423        target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 424        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 425            cs->exception_index = excp_idx;
 426            env->exception.target_el = target_el;
 427            cc->do_interrupt(cs);
 428            ret = true;
 429        }
 430    }
 431    if (interrupt_request & CPU_INTERRUPT_HARD) {
 432        excp_idx = EXCP_IRQ;
 433        target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 434        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 435            cs->exception_index = excp_idx;
 436            env->exception.target_el = target_el;
 437            cc->do_interrupt(cs);
 438            ret = true;
 439        }
 440    }
 441    if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 442        excp_idx = EXCP_VIRQ;
 443        target_el = 1;
 444        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 445            cs->exception_index = excp_idx;
 446            env->exception.target_el = target_el;
 447            cc->do_interrupt(cs);
 448            ret = true;
 449        }
 450    }
 451    if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 452        excp_idx = EXCP_VFIQ;
 453        target_el = 1;
 454        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 455            cs->exception_index = excp_idx;
 456            env->exception.target_el = target_el;
 457            cc->do_interrupt(cs);
 458            ret = true;
 459        }
 460    }
 461
 462    return ret;
 463}
 464
 465#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 466static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 467{
 468    CPUClass *cc = CPU_GET_CLASS(cs);
 469    ARMCPU *cpu = ARM_CPU(cs);
 470    CPUARMState *env = &cpu->env;
 471    bool ret = false;
 472
 473    /* ARMv7-M interrupt masking works differently than -A or -R.
 474     * There is no FIQ/IRQ distinction. Instead of I and F bits
 475     * masking FIQ and IRQ interrupts, an exception is taken only
 476     * if it is higher priority than the current execution priority
 477     * (which depends on state like BASEPRI, FAULTMASK and the
 478     * currently active exception).
 479     */
 480    if (interrupt_request & CPU_INTERRUPT_HARD
 481        && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 482        cs->exception_index = EXCP_IRQ;
 483        cc->do_interrupt(cs);
 484        ret = true;
 485    }
 486    return ret;
 487}
 488#endif
 489
 490void arm_cpu_update_virq(ARMCPU *cpu)
 491{
 492    /*
 493     * Update the interrupt level for VIRQ, which is the logical OR of
 494     * the HCR_EL2.VI bit and the input line level from the GIC.
 495     */
 496    CPUARMState *env = &cpu->env;
 497    CPUState *cs = CPU(cpu);
 498
 499    bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
 500        (env->irq_line_state & CPU_INTERRUPT_VIRQ);
 501
 502    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
 503        if (new_state) {
 504            cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
 505        } else {
 506            cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
 507        }
 508    }
 509}
 510
 511void arm_cpu_update_vfiq(ARMCPU *cpu)
 512{
 513    /*
 514     * Update the interrupt level for VFIQ, which is the logical OR of
 515     * the HCR_EL2.VF bit and the input line level from the GIC.
 516     */
 517    CPUARMState *env = &cpu->env;
 518    CPUState *cs = CPU(cpu);
 519
 520    bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
 521        (env->irq_line_state & CPU_INTERRUPT_VFIQ);
 522
 523    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
 524        if (new_state) {
 525            cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
 526        } else {
 527            cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
 528        }
 529    }
 530}
 531
 532#ifndef CONFIG_USER_ONLY
 533static void arm_cpu_set_irq(void *opaque, int irq, int level)
 534{
 535    ARMCPU *cpu = opaque;
 536    CPUARMState *env = &cpu->env;
 537    CPUState *cs = CPU(cpu);
 538    static const int mask[] = {
 539        [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 540        [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 541        [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 542        [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 543    };
 544
 545    if (level) {
 546        env->irq_line_state |= mask[irq];
 547    } else {
 548        env->irq_line_state &= ~mask[irq];
 549    }
 550
 551    switch (irq) {
 552    case ARM_CPU_VIRQ:
 553        assert(arm_feature(env, ARM_FEATURE_EL2));
 554        arm_cpu_update_virq(cpu);
 555        break;
 556    case ARM_CPU_VFIQ:
 557        assert(arm_feature(env, ARM_FEATURE_EL2));
 558        arm_cpu_update_vfiq(cpu);
 559        break;
 560    case ARM_CPU_IRQ:
 561    case ARM_CPU_FIQ:
 562        if (level) {
 563            cpu_interrupt(cs, mask[irq]);
 564        } else {
 565            cpu_reset_interrupt(cs, mask[irq]);
 566        }
 567        break;
 568    default:
 569        g_assert_not_reached();
 570    }
 571}
 572
 573static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 574{
 575#ifdef CONFIG_KVM
 576    ARMCPU *cpu = opaque;
 577    CPUARMState *env = &cpu->env;
 578    CPUState *cs = CPU(cpu);
 579    int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 580    uint32_t linestate_bit;
 581
 582    switch (irq) {
 583    case ARM_CPU_IRQ:
 584        kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 585        linestate_bit = CPU_INTERRUPT_HARD;
 586        break;
 587    case ARM_CPU_FIQ:
 588        kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 589        linestate_bit = CPU_INTERRUPT_FIQ;
 590        break;
 591    default:
 592        g_assert_not_reached();
 593    }
 594
 595    if (level) {
 596        env->irq_line_state |= linestate_bit;
 597    } else {
 598        env->irq_line_state &= ~linestate_bit;
 599    }
 600
 601    kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 602    kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 603#endif
 604}
 605
 606static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 607{
 608    ARMCPU *cpu = ARM_CPU(cs);
 609    CPUARMState *env = &cpu->env;
 610
 611    cpu_synchronize_state(cs);
 612    return arm_cpu_data_is_big_endian(env);
 613}
 614
 615#endif
 616
 617static inline void set_feature(CPUARMState *env, int feature)
 618{
 619    env->features |= 1ULL << feature;
 620}
 621
 622static inline void unset_feature(CPUARMState *env, int feature)
 623{
 624    env->features &= ~(1ULL << feature);
 625}
 626
 627static int
 628print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 629{
 630  return print_insn_arm(pc | 1, info);
 631}
 632
 633static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 634{
 635    ARMCPU *ac = ARM_CPU(cpu);
 636    CPUARMState *env = &ac->env;
 637    bool sctlr_b;
 638
 639    if (is_a64(env)) {
 640        /* We might not be compiled with the A64 disassembler
 641         * because it needs a C++ compiler. Leave print_insn
 642         * unset in this case to use the caller default behaviour.
 643         */
 644#if defined(CONFIG_ARM_A64_DIS)
 645        info->print_insn = print_insn_arm_a64;
 646#endif
 647        info->cap_arch = CS_ARCH_ARM64;
 648        info->cap_insn_unit = 4;
 649        info->cap_insn_split = 4;
 650    } else {
 651        int cap_mode;
 652        if (env->thumb) {
 653            info->print_insn = print_insn_thumb1;
 654            info->cap_insn_unit = 2;
 655            info->cap_insn_split = 4;
 656            cap_mode = CS_MODE_THUMB;
 657        } else {
 658            info->print_insn = print_insn_arm;
 659            info->cap_insn_unit = 4;
 660            info->cap_insn_split = 4;
 661            cap_mode = CS_MODE_ARM;
 662        }
 663        if (arm_feature(env, ARM_FEATURE_V8)) {
 664            cap_mode |= CS_MODE_V8;
 665        }
 666        if (arm_feature(env, ARM_FEATURE_M)) {
 667            cap_mode |= CS_MODE_MCLASS;
 668        }
 669        info->cap_arch = CS_ARCH_ARM;
 670        info->cap_mode = cap_mode;
 671    }
 672
 673    sctlr_b = arm_sctlr_b(env);
 674    if (bswap_code(sctlr_b)) {
 675#ifdef TARGET_WORDS_BIGENDIAN
 676        info->endian = BFD_ENDIAN_LITTLE;
 677#else
 678        info->endian = BFD_ENDIAN_BIG;
 679#endif
 680    }
 681    info->flags &= ~INSN_ARM_BE32;
 682#ifndef CONFIG_USER_ONLY
 683    if (sctlr_b) {
 684        info->flags |= INSN_ARM_BE32;
 685    }
 686#endif
 687}
 688
 689#ifdef TARGET_AARCH64
 690
 691static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 692{
 693    ARMCPU *cpu = ARM_CPU(cs);
 694    CPUARMState *env = &cpu->env;
 695    uint32_t psr = pstate_read(env);
 696    int i;
 697    int el = arm_current_el(env);
 698    const char *ns_status;
 699
 700    qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
 701    for (i = 0; i < 32; i++) {
 702        if (i == 31) {
 703            qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
 704        } else {
 705            qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
 706                         (i + 2) % 3 ? " " : "\n");
 707        }
 708    }
 709
 710    if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
 711        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
 712    } else {
 713        ns_status = "";
 714    }
 715    qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
 716                 psr,
 717                 psr & PSTATE_N ? 'N' : '-',
 718                 psr & PSTATE_Z ? 'Z' : '-',
 719                 psr & PSTATE_C ? 'C' : '-',
 720                 psr & PSTATE_V ? 'V' : '-',
 721                 ns_status,
 722                 el,
 723                 psr & PSTATE_SP ? 'h' : 't');
 724
 725    if (cpu_isar_feature(aa64_bti, cpu)) {
 726        qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
 727    }
 728    if (!(flags & CPU_DUMP_FPU)) {
 729        qemu_fprintf(f, "\n");
 730        return;
 731    }
 732    if (fp_exception_el(env, el) != 0) {
 733        qemu_fprintf(f, "    FPU disabled\n");
 734        return;
 735    }
 736    qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
 737                 vfp_get_fpcr(env), vfp_get_fpsr(env));
 738
 739    if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
 740        int j, zcr_len = sve_zcr_len_for_el(env, el);
 741
 742        for (i = 0; i <= FFR_PRED_NUM; i++) {
 743            bool eol;
 744            if (i == FFR_PRED_NUM) {
 745                qemu_fprintf(f, "FFR=");
 746                /* It's last, so end the line.  */
 747                eol = true;
 748            } else {
 749                qemu_fprintf(f, "P%02d=", i);
 750                switch (zcr_len) {
 751                case 0:
 752                    eol = i % 8 == 7;
 753                    break;
 754                case 1:
 755                    eol = i % 6 == 5;
 756                    break;
 757                case 2:
 758                case 3:
 759                    eol = i % 3 == 2;
 760                    break;
 761                default:
 762                    /* More than one quadword per predicate.  */
 763                    eol = true;
 764                    break;
 765                }
 766            }
 767            for (j = zcr_len / 4; j >= 0; j--) {
 768                int digits;
 769                if (j * 4 + 4 <= zcr_len + 1) {
 770                    digits = 16;
 771                } else {
 772                    digits = (zcr_len % 4 + 1) * 4;
 773                }
 774                qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
 775                             env->vfp.pregs[i].p[j],
 776                             j ? ":" : eol ? "\n" : " ");
 777            }
 778        }
 779
 780        for (i = 0; i < 32; i++) {
 781            if (zcr_len == 0) {
 782                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
 783                             i, env->vfp.zregs[i].d[1],
 784                             env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
 785            } else if (zcr_len == 1) {
 786                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
 787                             ":%016" PRIx64 ":%016" PRIx64 "\n",
 788                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
 789                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
 790            } else {
 791                for (j = zcr_len; j >= 0; j--) {
 792                    bool odd = (zcr_len - j) % 2 != 0;
 793                    if (j == zcr_len) {
 794                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
 795                    } else if (!odd) {
 796                        if (j > 0) {
 797                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
 798                        } else {
 799                            qemu_fprintf(f, "     [%x]=", j);
 800                        }
 801                    }
 802                    qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
 803                                 env->vfp.zregs[i].d[j * 2 + 1],
 804                                 env->vfp.zregs[i].d[j * 2],
 805                                 odd || j == 0 ? "\n" : ":");
 806                }
 807            }
 808        }
 809    } else {
 810        for (i = 0; i < 32; i++) {
 811            uint64_t *q = aa64_vfp_qreg(env, i);
 812            qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
 813                         i, q[1], q[0], (i & 1 ? "\n" : " "));
 814        }
 815    }
 816}
 817
 818#else
 819
 820static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 821{
 822    g_assert_not_reached();
 823}
 824
 825#endif
 826
 827static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 828{
 829    ARMCPU *cpu = ARM_CPU(cs);
 830    CPUARMState *env = &cpu->env;
 831    int i;
 832
 833    if (is_a64(env)) {
 834        aarch64_cpu_dump_state(cs, f, flags);
 835        return;
 836    }
 837
 838    for (i = 0; i < 16; i++) {
 839        qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
 840        if ((i % 4) == 3) {
 841            qemu_fprintf(f, "\n");
 842        } else {
 843            qemu_fprintf(f, " ");
 844        }
 845    }
 846
 847    if (arm_feature(env, ARM_FEATURE_M)) {
 848        uint32_t xpsr = xpsr_read(env);
 849        const char *mode;
 850        const char *ns_status = "";
 851
 852        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 853            ns_status = env->v7m.secure ? "S " : "NS ";
 854        }
 855
 856        if (xpsr & XPSR_EXCP) {
 857            mode = "handler";
 858        } else {
 859            if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
 860                mode = "unpriv-thread";
 861            } else {
 862                mode = "priv-thread";
 863            }
 864        }
 865
 866        qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
 867                     xpsr,
 868                     xpsr & XPSR_N ? 'N' : '-',
 869                     xpsr & XPSR_Z ? 'Z' : '-',
 870                     xpsr & XPSR_C ? 'C' : '-',
 871                     xpsr & XPSR_V ? 'V' : '-',
 872                     xpsr & XPSR_T ? 'T' : 'A',
 873                     ns_status,
 874                     mode);
 875    } else {
 876        uint32_t psr = cpsr_read(env);
 877        const char *ns_status = "";
 878
 879        if (arm_feature(env, ARM_FEATURE_EL3) &&
 880            (psr & CPSR_M) != ARM_CPU_MODE_MON) {
 881            ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
 882        }
 883
 884        qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
 885                     psr,
 886                     psr & CPSR_N ? 'N' : '-',
 887                     psr & CPSR_Z ? 'Z' : '-',
 888                     psr & CPSR_C ? 'C' : '-',
 889                     psr & CPSR_V ? 'V' : '-',
 890                     psr & CPSR_T ? 'T' : 'A',
 891                     ns_status,
 892                     aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
 893    }
 894
 895    if (flags & CPU_DUMP_FPU) {
 896        int numvfpregs = 0;
 897        if (arm_feature(env, ARM_FEATURE_VFP)) {
 898            numvfpregs += 16;
 899        }
 900        if (arm_feature(env, ARM_FEATURE_VFP3)) {
 901            numvfpregs += 16;
 902        }
 903        for (i = 0; i < numvfpregs; i++) {
 904            uint64_t v = *aa32_vfp_dreg(env, i);
 905            qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
 906                         i * 2, (uint32_t)v,
 907                         i * 2 + 1, (uint32_t)(v >> 32),
 908                         i, v);
 909        }
 910        qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
 911    }
 912}
 913
 914uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
 915{
 916    uint32_t Aff1 = idx / clustersz;
 917    uint32_t Aff0 = idx % clustersz;
 918    return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 919}
 920
 921static void cpreg_hashtable_data_destroy(gpointer data)
 922{
 923    /*
 924     * Destroy function for cpu->cp_regs hashtable data entries.
 925     * We must free the name string because it was g_strdup()ed in
 926     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
 927     * from r->name because we know we definitely allocated it.
 928     */
 929    ARMCPRegInfo *r = data;
 930
 931    g_free((void *)r->name);
 932    g_free(r);
 933}
 934
 935static void arm_cpu_initfn(Object *obj)
 936{
 937    ARMCPU *cpu = ARM_CPU(obj);
 938
 939    cpu_set_cpustate_pointers(cpu);
 940    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 941                                         g_free, cpreg_hashtable_data_destroy);
 942
 943    QLIST_INIT(&cpu->pre_el_change_hooks);
 944    QLIST_INIT(&cpu->el_change_hooks);
 945
 946#ifndef CONFIG_USER_ONLY
 947    /* Our inbound IRQ and FIQ lines */
 948    if (kvm_enabled()) {
 949        /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 950         * the same interface as non-KVM CPUs.
 951         */
 952        qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 953    } else {
 954        qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 955    }
 956
 957    qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 958                       ARRAY_SIZE(cpu->gt_timer_outputs));
 959
 960    qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
 961                             "gicv3-maintenance-interrupt", 1);
 962    qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
 963                             "pmu-interrupt", 1);
 964#endif
 965
 966    /* DTB consumers generally don't in fact care what the 'compatible'
 967     * string is, so always provide some string and trust that a hypothetical
 968     * picky DTB consumer will also provide a helpful error message.
 969     */
 970    cpu->dtb_compatible = "qemu,unknown";
 971    cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 972    cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 973
 974    if (tcg_enabled()) {
 975        cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 976    }
 977}
 978
 979static Property arm_cpu_reset_cbar_property =
 980            DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 981
 982static Property arm_cpu_reset_hivecs_property =
 983            DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 984
 985static Property arm_cpu_rvbar_property =
 986            DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 987
 988static Property arm_cpu_has_el2_property =
 989            DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
 990
 991static Property arm_cpu_has_el3_property =
 992            DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 993
 994static Property arm_cpu_cfgend_property =
 995            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 996
 997/* use property name "pmu" to match other archs and virt tools */
 998static Property arm_cpu_has_pmu_property =
 999            DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
1000
1001static Property arm_cpu_has_vfp_property =
1002            DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1003
1004static Property arm_cpu_has_neon_property =
1005            DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1006
1007static Property arm_cpu_has_dsp_property =
1008            DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1009
1010static Property arm_cpu_has_mpu_property =
1011            DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1012
1013/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1014 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1015 * the right value for that particular CPU type, and we don't want
1016 * to override that with an incorrect constant value.
1017 */
1018static Property arm_cpu_pmsav7_dregion_property =
1019            DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1020                                           pmsav7_dregion,
1021                                           qdev_prop_uint32, uint32_t);
1022
1023static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
1024                               void *opaque, Error **errp)
1025{
1026    ARMCPU *cpu = ARM_CPU(obj);
1027
1028    visit_type_uint32(v, name, &cpu->init_svtor, errp);
1029}
1030
1031static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
1032                               void *opaque, Error **errp)
1033{
1034    ARMCPU *cpu = ARM_CPU(obj);
1035
1036    visit_type_uint32(v, name, &cpu->init_svtor, errp);
1037}
1038
1039void arm_cpu_post_init(Object *obj)
1040{
1041    ARMCPU *cpu = ARM_CPU(obj);
1042
1043    /* M profile implies PMSA. We have to do this here rather than
1044     * in realize with the other feature-implication checks because
1045     * we look at the PMSA bit to see if we should add some properties.
1046     */
1047    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1048        set_feature(&cpu->env, ARM_FEATURE_PMSA);
1049    }
1050    /* Similarly for the VFP feature bits */
1051    if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
1052        set_feature(&cpu->env, ARM_FEATURE_VFP3);
1053    }
1054    if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
1055        set_feature(&cpu->env, ARM_FEATURE_VFP);
1056    }
1057
1058    if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1059        arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1060        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
1061                                 &error_abort);
1062    }
1063
1064    if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1065        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
1066                                 &error_abort);
1067    }
1068
1069    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1070        qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
1071                                 &error_abort);
1072    }
1073
1074    if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1075        /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
1076         * prevent "has_el3" from existing on CPUs which cannot support EL3.
1077         */
1078        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
1079                                 &error_abort);
1080
1081#ifndef CONFIG_USER_ONLY
1082        object_property_add_link(obj, "secure-memory",
1083                                 TYPE_MEMORY_REGION,
1084                                 (Object **)&cpu->secure_memory,
1085                                 qdev_prop_allow_set_link_before_realize,
1086                                 OBJ_PROP_LINK_STRONG,
1087                                 &error_abort);
1088#endif
1089    }
1090
1091    if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1092        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
1093                                 &error_abort);
1094    }
1095
1096    if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1097        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
1098                                 &error_abort);
1099    }
1100
1101    /*
1102     * Allow user to turn off VFP and Neon support, but only for TCG --
1103     * KVM does not currently allow us to lie to the guest about its
1104     * ID/feature registers, so the guest always sees what the host has.
1105     */
1106    if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1107        cpu->has_vfp = true;
1108        if (!kvm_enabled()) {
1109            qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property,
1110                                     &error_abort);
1111        }
1112    }
1113
1114    if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1115        cpu->has_neon = true;
1116        if (!kvm_enabled()) {
1117            qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property,
1118                                     &error_abort);
1119        }
1120    }
1121
1122    if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1123        arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1124        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property,
1125                                 &error_abort);
1126    }
1127
1128    if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1129        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
1130                                 &error_abort);
1131        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1132            qdev_property_add_static(DEVICE(obj),
1133                                     &arm_cpu_pmsav7_dregion_property,
1134                                     &error_abort);
1135        }
1136    }
1137
1138    if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1139        object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1140                                 qdev_prop_allow_set_link_before_realize,
1141                                 OBJ_PROP_LINK_STRONG,
1142                                 &error_abort);
1143        /*
1144         * M profile: initial value of the Secure VTOR. We can't just use
1145         * a simple DEFINE_PROP_UINT32 for this because we want to permit
1146         * the property to be set after realize.
1147         */
1148        object_property_add(obj, "init-svtor", "uint32",
1149                            arm_get_init_svtor, arm_set_init_svtor,
1150                            NULL, NULL, &error_abort);
1151    }
1152
1153    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
1154                             &error_abort);
1155}
1156
1157static void arm_cpu_finalizefn(Object *obj)
1158{
1159    ARMCPU *cpu = ARM_CPU(obj);
1160    ARMELChangeHook *hook, *next;
1161
1162    g_hash_table_destroy(cpu->cp_regs);
1163
1164    QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1165        QLIST_REMOVE(hook, node);
1166        g_free(hook);
1167    }
1168    QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1169        QLIST_REMOVE(hook, node);
1170        g_free(hook);
1171    }
1172#ifndef CONFIG_USER_ONLY
1173    if (cpu->pmu_timer) {
1174        timer_del(cpu->pmu_timer);
1175        timer_deinit(cpu->pmu_timer);
1176        timer_free(cpu->pmu_timer);
1177    }
1178#endif
1179}
1180
1181static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1182{
1183    CPUState *cs = CPU(dev);
1184    ARMCPU *cpu = ARM_CPU(dev);
1185    ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1186    CPUARMState *env = &cpu->env;
1187    int pagebits;
1188    Error *local_err = NULL;
1189    bool no_aa32 = false;
1190
1191    /* If we needed to query the host kernel for the CPU features
1192     * then it's possible that might have failed in the initfn, but
1193     * this is the first point where we can report it.
1194     */
1195    if (cpu->host_cpu_probe_failed) {
1196        if (!kvm_enabled()) {
1197            error_setg(errp, "The 'host' CPU type can only be used with KVM");
1198        } else {
1199            error_setg(errp, "Failed to retrieve host CPU features");
1200        }
1201        return;
1202    }
1203
1204#ifndef CONFIG_USER_ONLY
1205    /* The NVIC and M-profile CPU are two halves of a single piece of
1206     * hardware; trying to use one without the other is a command line
1207     * error and will result in segfaults if not caught here.
1208     */
1209    if (arm_feature(env, ARM_FEATURE_M)) {
1210        if (!env->nvic) {
1211            error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1212            return;
1213        }
1214    } else {
1215        if (env->nvic) {
1216            error_setg(errp, "This board can only be used with Cortex-M CPUs");
1217            return;
1218        }
1219    }
1220
1221    cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1222                                           arm_gt_ptimer_cb, cpu);
1223    cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1224                                           arm_gt_vtimer_cb, cpu);
1225    cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1226                                          arm_gt_htimer_cb, cpu);
1227    cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1228                                          arm_gt_stimer_cb, cpu);
1229#endif
1230
1231    cpu_exec_realizefn(cs, &local_err);
1232    if (local_err != NULL) {
1233        error_propagate(errp, local_err);
1234        return;
1235    }
1236
1237    if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1238        cpu->has_vfp != cpu->has_neon) {
1239        /*
1240         * This is an architectural requirement for AArch64; AArch32 is
1241         * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1242         */
1243        error_setg(errp,
1244                   "AArch64 CPUs must have both VFP and Neon or neither");
1245        return;
1246    }
1247
1248    if (!cpu->has_vfp) {
1249        uint64_t t;
1250        uint32_t u;
1251
1252        unset_feature(env, ARM_FEATURE_VFP);
1253        unset_feature(env, ARM_FEATURE_VFP3);
1254        unset_feature(env, ARM_FEATURE_VFP4);
1255
1256        t = cpu->isar.id_aa64isar1;
1257        t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1258        cpu->isar.id_aa64isar1 = t;
1259
1260        t = cpu->isar.id_aa64pfr0;
1261        t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1262        cpu->isar.id_aa64pfr0 = t;
1263
1264        u = cpu->isar.id_isar6;
1265        u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1266        cpu->isar.id_isar6 = u;
1267
1268        u = cpu->isar.mvfr0;
1269        u = FIELD_DP32(u, MVFR0, FPSP, 0);
1270        u = FIELD_DP32(u, MVFR0, FPDP, 0);
1271        u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1272        u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1273        u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1274        u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1275        u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1276        cpu->isar.mvfr0 = u;
1277
1278        u = cpu->isar.mvfr1;
1279        u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1280        u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1281        u = FIELD_DP32(u, MVFR1, FPHP, 0);
1282        cpu->isar.mvfr1 = u;
1283
1284        u = cpu->isar.mvfr2;
1285        u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1286        cpu->isar.mvfr2 = u;
1287    }
1288
1289    if (!cpu->has_neon) {
1290        uint64_t t;
1291        uint32_t u;
1292
1293        unset_feature(env, ARM_FEATURE_NEON);
1294
1295        t = cpu->isar.id_aa64isar0;
1296        t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1297        cpu->isar.id_aa64isar0 = t;
1298
1299        t = cpu->isar.id_aa64isar1;
1300        t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1301        cpu->isar.id_aa64isar1 = t;
1302
1303        t = cpu->isar.id_aa64pfr0;
1304        t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1305        cpu->isar.id_aa64pfr0 = t;
1306
1307        u = cpu->isar.id_isar5;
1308        u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1309        u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1310        cpu->isar.id_isar5 = u;
1311
1312        u = cpu->isar.id_isar6;
1313        u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1314        u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1315        cpu->isar.id_isar6 = u;
1316
1317        u = cpu->isar.mvfr1;
1318        u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1319        u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1320        u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1321        u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1322        u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1323        cpu->isar.mvfr1 = u;
1324
1325        u = cpu->isar.mvfr2;
1326        u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1327        cpu->isar.mvfr2 = u;
1328    }
1329
1330    if (!cpu->has_neon && !cpu->has_vfp) {
1331        uint64_t t;
1332        uint32_t u;
1333
1334        t = cpu->isar.id_aa64isar0;
1335        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1336        cpu->isar.id_aa64isar0 = t;
1337
1338        t = cpu->isar.id_aa64isar1;
1339        t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1340        cpu->isar.id_aa64isar1 = t;
1341
1342        u = cpu->isar.mvfr0;
1343        u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1344        cpu->isar.mvfr0 = u;
1345    }
1346
1347    if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1348        uint32_t u;
1349
1350        unset_feature(env, ARM_FEATURE_THUMB_DSP);
1351
1352        u = cpu->isar.id_isar1;
1353        u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1354        cpu->isar.id_isar1 = u;
1355
1356        u = cpu->isar.id_isar2;
1357        u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1358        u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1359        cpu->isar.id_isar2 = u;
1360
1361        u = cpu->isar.id_isar3;
1362        u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1363        u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1364        cpu->isar.id_isar3 = u;
1365    }
1366
1367    /* Some features automatically imply others: */
1368    if (arm_feature(env, ARM_FEATURE_V8)) {
1369        if (arm_feature(env, ARM_FEATURE_M)) {
1370            set_feature(env, ARM_FEATURE_V7);
1371        } else {
1372            set_feature(env, ARM_FEATURE_V7VE);
1373        }
1374    }
1375
1376    /*
1377     * There exist AArch64 cpus without AArch32 support.  When KVM
1378     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1379     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1380     * As a general principle, we also do not make ID register
1381     * consistency checks anywhere unless using TCG, because only
1382     * for TCG would a consistency-check failure be a QEMU bug.
1383     */
1384    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1385        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1386    }
1387
1388    if (arm_feature(env, ARM_FEATURE_V7VE)) {
1389        /* v7 Virtualization Extensions. In real hardware this implies
1390         * EL2 and also the presence of the Security Extensions.
1391         * For QEMU, for backwards-compatibility we implement some
1392         * CPUs or CPU configs which have no actual EL2 or EL3 but do
1393         * include the various other features that V7VE implies.
1394         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1395         * Security Extensions is ARM_FEATURE_EL3.
1396         */
1397        assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
1398        set_feature(env, ARM_FEATURE_LPAE);
1399        set_feature(env, ARM_FEATURE_V7);
1400    }
1401    if (arm_feature(env, ARM_FEATURE_V7)) {
1402        set_feature(env, ARM_FEATURE_VAPA);
1403        set_feature(env, ARM_FEATURE_THUMB2);
1404        set_feature(env, ARM_FEATURE_MPIDR);
1405        if (!arm_feature(env, ARM_FEATURE_M)) {
1406            set_feature(env, ARM_FEATURE_V6K);
1407        } else {
1408            set_feature(env, ARM_FEATURE_V6);
1409        }
1410
1411        /* Always define VBAR for V7 CPUs even if it doesn't exist in
1412         * non-EL3 configs. This is needed by some legacy boards.
1413         */
1414        set_feature(env, ARM_FEATURE_VBAR);
1415    }
1416    if (arm_feature(env, ARM_FEATURE_V6K)) {
1417        set_feature(env, ARM_FEATURE_V6);
1418        set_feature(env, ARM_FEATURE_MVFR);
1419    }
1420    if (arm_feature(env, ARM_FEATURE_V6)) {
1421        set_feature(env, ARM_FEATURE_V5);
1422        if (!arm_feature(env, ARM_FEATURE_M)) {
1423            assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
1424            set_feature(env, ARM_FEATURE_AUXCR);
1425        }
1426    }
1427    if (arm_feature(env, ARM_FEATURE_V5)) {
1428        set_feature(env, ARM_FEATURE_V4T);
1429    }
1430    if (arm_feature(env, ARM_FEATURE_LPAE)) {
1431        set_feature(env, ARM_FEATURE_V7MP);
1432        set_feature(env, ARM_FEATURE_PXN);
1433    }
1434    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1435        set_feature(env, ARM_FEATURE_CBAR);
1436    }
1437    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1438        !arm_feature(env, ARM_FEATURE_M)) {
1439        set_feature(env, ARM_FEATURE_THUMB_DSP);
1440    }
1441
1442    /*
1443     * We rely on no XScale CPU having VFP so we can use the same bits in the
1444     * TB flags field for VECSTRIDE and XSCALE_CPAR.
1445     */
1446    assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
1447             arm_feature(env, ARM_FEATURE_XSCALE)));
1448
1449    if (arm_feature(env, ARM_FEATURE_V7) &&
1450        !arm_feature(env, ARM_FEATURE_M) &&
1451        !arm_feature(env, ARM_FEATURE_PMSA)) {
1452        /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1453         * can use 4K pages.
1454         */
1455        pagebits = 12;
1456    } else {
1457        /* For CPUs which might have tiny 1K pages, or which have an
1458         * MPU and might have small region sizes, stick with 1K pages.
1459         */
1460        pagebits = 10;
1461    }
1462    if (!set_preferred_target_page_bits(pagebits)) {
1463        /* This can only ever happen for hotplugging a CPU, or if
1464         * the board code incorrectly creates a CPU which it has
1465         * promised via minimum_page_size that it will not.
1466         */
1467        error_setg(errp, "This CPU requires a smaller page size than the "
1468                   "system is using");
1469        return;
1470    }
1471
1472    /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1473     * We don't support setting cluster ID ([16..23]) (known as Aff2
1474     * in later ARM ARM versions), or any of the higher affinity level fields,
1475     * so these bits always RAZ.
1476     */
1477    if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1478        cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1479                                               ARM_DEFAULT_CPUS_PER_CLUSTER);
1480    }
1481
1482    if (cpu->reset_hivecs) {
1483            cpu->reset_sctlr |= (1 << 13);
1484    }
1485
1486    if (cpu->cfgend) {
1487        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1488            cpu->reset_sctlr |= SCTLR_EE;
1489        } else {
1490            cpu->reset_sctlr |= SCTLR_B;
1491        }
1492    }
1493
1494    if (!cpu->has_el3) {
1495        /* If the has_el3 CPU property is disabled then we need to disable the
1496         * feature.
1497         */
1498        unset_feature(env, ARM_FEATURE_EL3);
1499
1500        /* Disable the security extension feature bits in the processor feature
1501         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1502         */
1503        cpu->id_pfr1 &= ~0xf0;
1504        cpu->isar.id_aa64pfr0 &= ~0xf000;
1505    }
1506
1507    if (!cpu->has_el2) {
1508        unset_feature(env, ARM_FEATURE_EL2);
1509    }
1510
1511    if (!cpu->has_pmu) {
1512        unset_feature(env, ARM_FEATURE_PMU);
1513    }
1514    if (arm_feature(env, ARM_FEATURE_PMU)) {
1515        pmu_init(cpu);
1516
1517        if (!kvm_enabled()) {
1518            arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1519            arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1520        }
1521
1522#ifndef CONFIG_USER_ONLY
1523        cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1524                cpu);
1525#endif
1526    } else {
1527        cpu->id_aa64dfr0 &= ~0xf00;
1528        cpu->id_dfr0 &= ~(0xf << 24);
1529        cpu->pmceid0 = 0;
1530        cpu->pmceid1 = 0;
1531    }
1532
1533    if (!arm_feature(env, ARM_FEATURE_EL2)) {
1534        /* Disable the hypervisor feature bits in the processor feature
1535         * registers if we don't have EL2. These are id_pfr1[15:12] and
1536         * id_aa64pfr0_el1[11:8].
1537         */
1538        cpu->isar.id_aa64pfr0 &= ~0xf00;
1539        cpu->id_pfr1 &= ~0xf000;
1540    }
1541
1542    /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1543     * to false or by setting pmsav7-dregion to 0.
1544     */
1545    if (!cpu->has_mpu) {
1546        cpu->pmsav7_dregion = 0;
1547    }
1548    if (cpu->pmsav7_dregion == 0) {
1549        cpu->has_mpu = false;
1550    }
1551
1552    if (arm_feature(env, ARM_FEATURE_PMSA) &&
1553        arm_feature(env, ARM_FEATURE_V7)) {
1554        uint32_t nr = cpu->pmsav7_dregion;
1555
1556        if (nr > 0xff) {
1557            error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1558            return;
1559        }
1560
1561        if (nr) {
1562            if (arm_feature(env, ARM_FEATURE_V8)) {
1563                /* PMSAv8 */
1564                env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1565                env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1566                if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1567                    env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1568                    env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1569                }
1570            } else {
1571                env->pmsav7.drbar = g_new0(uint32_t, nr);
1572                env->pmsav7.drsr = g_new0(uint32_t, nr);
1573                env->pmsav7.dracr = g_new0(uint32_t, nr);
1574            }
1575        }
1576    }
1577
1578    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1579        uint32_t nr = cpu->sau_sregion;
1580
1581        if (nr > 0xff) {
1582            error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1583            return;
1584        }
1585
1586        if (nr) {
1587            env->sau.rbar = g_new0(uint32_t, nr);
1588            env->sau.rlar = g_new0(uint32_t, nr);
1589        }
1590    }
1591
1592    if (arm_feature(env, ARM_FEATURE_EL3)) {
1593        set_feature(env, ARM_FEATURE_VBAR);
1594    }
1595
1596    register_cp_regs_for_features(cpu);
1597    arm_cpu_register_gdb_regs_for_features(cpu);
1598
1599    init_cpreg_list(cpu);
1600
1601#ifndef CONFIG_USER_ONLY
1602    MachineState *ms = MACHINE(qdev_get_machine());
1603    unsigned int smp_cpus = ms->smp.cpus;
1604
1605    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1606        cs->num_ases = 2;
1607
1608        if (!cpu->secure_memory) {
1609            cpu->secure_memory = cs->memory;
1610        }
1611        cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1612                               cpu->secure_memory);
1613    } else {
1614        cs->num_ases = 1;
1615    }
1616    cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1617
1618    /* No core_count specified, default to smp_cpus. */
1619    if (cpu->core_count == -1) {
1620        cpu->core_count = smp_cpus;
1621    }
1622#endif
1623
1624    qemu_init_vcpu(cs);
1625    cpu_reset(cs);
1626
1627    acc->parent_realize(dev, errp);
1628}
1629
1630static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1631{
1632    ObjectClass *oc;
1633    char *typename;
1634    char **cpuname;
1635    const char *cpunamestr;
1636
1637    cpuname = g_strsplit(cpu_model, ",", 1);
1638    cpunamestr = cpuname[0];
1639#ifdef CONFIG_USER_ONLY
1640    /* For backwards compatibility usermode emulation allows "-cpu any",
1641     * which has the same semantics as "-cpu max".
1642     */
1643    if (!strcmp(cpunamestr, "any")) {
1644        cpunamestr = "max";
1645    }
1646#endif
1647    typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1648    oc = object_class_by_name(typename);
1649    g_strfreev(cpuname);
1650    g_free(typename);
1651    if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1652        object_class_is_abstract(oc)) {
1653        return NULL;
1654    }
1655    return oc;
1656}
1657
1658/* CPU models. These are not needed for the AArch64 linux-user build. */
1659#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1660
1661static void arm926_initfn(Object *obj)
1662{
1663    ARMCPU *cpu = ARM_CPU(obj);
1664
1665    cpu->dtb_compatible = "arm,arm926";
1666    set_feature(&cpu->env, ARM_FEATURE_V5);
1667    set_feature(&cpu->env, ARM_FEATURE_VFP);
1668    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1669    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1670    cpu->midr = 0x41069265;
1671    cpu->reset_fpsid = 0x41011090;
1672    cpu->ctr = 0x1dd20d2;
1673    cpu->reset_sctlr = 0x00090078;
1674
1675    /*
1676     * ARMv5 does not have the ID_ISAR registers, but we can still
1677     * set the field to indicate Jazelle support within QEMU.
1678     */
1679    cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1680    /*
1681     * Similarly, we need to set MVFR0 fields to enable double precision
1682     * and short vector support even though ARMv5 doesn't have this register.
1683     */
1684    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1685    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1686}
1687
1688static void arm946_initfn(Object *obj)
1689{
1690    ARMCPU *cpu = ARM_CPU(obj);
1691
1692    cpu->dtb_compatible = "arm,arm946";
1693    set_feature(&cpu->env, ARM_FEATURE_V5);
1694    set_feature(&cpu->env, ARM_FEATURE_PMSA);
1695    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1696    cpu->midr = 0x41059461;
1697    cpu->ctr = 0x0f004006;
1698    cpu->reset_sctlr = 0x00000078;
1699}
1700
1701static void arm1026_initfn(Object *obj)
1702{
1703    ARMCPU *cpu = ARM_CPU(obj);
1704
1705    cpu->dtb_compatible = "arm,arm1026";
1706    set_feature(&cpu->env, ARM_FEATURE_V5);
1707    set_feature(&cpu->env, ARM_FEATURE_VFP);
1708    set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1709    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1710    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1711    cpu->midr = 0x4106a262;
1712    cpu->reset_fpsid = 0x410110a0;
1713    cpu->ctr = 0x1dd20d2;
1714    cpu->reset_sctlr = 0x00090078;
1715    cpu->reset_auxcr = 1;
1716
1717    /*
1718     * ARMv5 does not have the ID_ISAR registers, but we can still
1719     * set the field to indicate Jazelle support within QEMU.
1720     */
1721    cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1722    /*
1723     * Similarly, we need to set MVFR0 fields to enable double precision
1724     * and short vector support even though ARMv5 doesn't have this register.
1725     */
1726    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1727    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1728
1729    {
1730        /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1731        ARMCPRegInfo ifar = {
1732            .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1733            .access = PL1_RW,
1734            .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1735            .resetvalue = 0
1736        };
1737        define_one_arm_cp_reg(cpu, &ifar);
1738    }
1739}
1740
1741static void arm1136_r2_initfn(Object *obj)
1742{
1743    ARMCPU *cpu = ARM_CPU(obj);
1744    /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1745     * older core than plain "arm1136". In particular this does not
1746     * have the v6K features.
1747     * These ID register values are correct for 1136 but may be wrong
1748     * for 1136_r2 (in particular r0p2 does not actually implement most
1749     * of the ID registers).
1750     */
1751
1752    cpu->dtb_compatible = "arm,arm1136";
1753    set_feature(&cpu->env, ARM_FEATURE_V6);
1754    set_feature(&cpu->env, ARM_FEATURE_VFP);
1755    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1756    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1757    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1758    cpu->midr = 0x4107b362;
1759    cpu->reset_fpsid = 0x410120b4;
1760    cpu->isar.mvfr0 = 0x11111111;
1761    cpu->isar.mvfr1 = 0x00000000;
1762    cpu->ctr = 0x1dd20d2;
1763    cpu->reset_sctlr = 0x00050078;
1764    cpu->id_pfr0 = 0x111;
1765    cpu->id_pfr1 = 0x1;
1766    cpu->id_dfr0 = 0x2;
1767    cpu->id_afr0 = 0x3;
1768    cpu->id_mmfr0 = 0x01130003;
1769    cpu->id_mmfr1 = 0x10030302;
1770    cpu->id_mmfr2 = 0x01222110;
1771    cpu->isar.id_isar0 = 0x00140011;
1772    cpu->isar.id_isar1 = 0x12002111;
1773    cpu->isar.id_isar2 = 0x11231111;
1774    cpu->isar.id_isar3 = 0x01102131;
1775    cpu->isar.id_isar4 = 0x141;
1776    cpu->reset_auxcr = 7;
1777}
1778
1779static void arm1136_initfn(Object *obj)
1780{
1781    ARMCPU *cpu = ARM_CPU(obj);
1782
1783    cpu->dtb_compatible = "arm,arm1136";
1784    set_feature(&cpu->env, ARM_FEATURE_V6K);
1785    set_feature(&cpu->env, ARM_FEATURE_V6);
1786    set_feature(&cpu->env, ARM_FEATURE_VFP);
1787    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1788    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1789    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1790    cpu->midr = 0x4117b363;
1791    cpu->reset_fpsid = 0x410120b4;
1792    cpu->isar.mvfr0 = 0x11111111;
1793    cpu->isar.mvfr1 = 0x00000000;
1794    cpu->ctr = 0x1dd20d2;
1795    cpu->reset_sctlr = 0x00050078;
1796    cpu->id_pfr0 = 0x111;
1797    cpu->id_pfr1 = 0x1;
1798    cpu->id_dfr0 = 0x2;
1799    cpu->id_afr0 = 0x3;
1800    cpu->id_mmfr0 = 0x01130003;
1801    cpu->id_mmfr1 = 0x10030302;
1802    cpu->id_mmfr2 = 0x01222110;
1803    cpu->isar.id_isar0 = 0x00140011;
1804    cpu->isar.id_isar1 = 0x12002111;
1805    cpu->isar.id_isar2 = 0x11231111;
1806    cpu->isar.id_isar3 = 0x01102131;
1807    cpu->isar.id_isar4 = 0x141;
1808    cpu->reset_auxcr = 7;
1809}
1810
1811static void arm1176_initfn(Object *obj)
1812{
1813    ARMCPU *cpu = ARM_CPU(obj);
1814
1815    cpu->dtb_compatible = "arm,arm1176";
1816    set_feature(&cpu->env, ARM_FEATURE_V6K);
1817    set_feature(&cpu->env, ARM_FEATURE_VFP);
1818    set_feature(&cpu->env, ARM_FEATURE_VAPA);
1819    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1820    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1821    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1822    set_feature(&cpu->env, ARM_FEATURE_EL3);
1823    cpu->midr = 0x410fb767;
1824    cpu->reset_fpsid = 0x410120b5;
1825    cpu->isar.mvfr0 = 0x11111111;
1826    cpu->isar.mvfr1 = 0x00000000;
1827    cpu->ctr = 0x1dd20d2;
1828    cpu->reset_sctlr = 0x00050078;
1829    cpu->id_pfr0 = 0x111;
1830    cpu->id_pfr1 = 0x11;
1831    cpu->id_dfr0 = 0x33;
1832    cpu->id_afr0 = 0;
1833    cpu->id_mmfr0 = 0x01130003;
1834    cpu->id_mmfr1 = 0x10030302;
1835    cpu->id_mmfr2 = 0x01222100;
1836    cpu->isar.id_isar0 = 0x0140011;
1837    cpu->isar.id_isar1 = 0x12002111;
1838    cpu->isar.id_isar2 = 0x11231121;
1839    cpu->isar.id_isar3 = 0x01102131;
1840    cpu->isar.id_isar4 = 0x01141;
1841    cpu->reset_auxcr = 7;
1842}
1843
1844static void arm11mpcore_initfn(Object *obj)
1845{
1846    ARMCPU *cpu = ARM_CPU(obj);
1847
1848    cpu->dtb_compatible = "arm,arm11mpcore";
1849    set_feature(&cpu->env, ARM_FEATURE_V6K);
1850    set_feature(&cpu->env, ARM_FEATURE_VFP);
1851    set_feature(&cpu->env, ARM_FEATURE_VAPA);
1852    set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1853    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1854    cpu->midr = 0x410fb022;
1855    cpu->reset_fpsid = 0x410120b4;
1856    cpu->isar.mvfr0 = 0x11111111;
1857    cpu->isar.mvfr1 = 0x00000000;
1858    cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1859    cpu->id_pfr0 = 0x111;
1860    cpu->id_pfr1 = 0x1;
1861    cpu->id_dfr0 = 0;
1862    cpu->id_afr0 = 0x2;
1863    cpu->id_mmfr0 = 0x01100103;
1864    cpu->id_mmfr1 = 0x10020302;
1865    cpu->id_mmfr2 = 0x01222000;
1866    cpu->isar.id_isar0 = 0x00100011;
1867    cpu->isar.id_isar1 = 0x12002111;
1868    cpu->isar.id_isar2 = 0x11221011;
1869    cpu->isar.id_isar3 = 0x01102131;
1870    cpu->isar.id_isar4 = 0x141;
1871    cpu->reset_auxcr = 1;
1872}
1873
1874static void cortex_m0_initfn(Object *obj)
1875{
1876    ARMCPU *cpu = ARM_CPU(obj);
1877    set_feature(&cpu->env, ARM_FEATURE_V6);
1878    set_feature(&cpu->env, ARM_FEATURE_M);
1879
1880    cpu->midr = 0x410cc200;
1881}
1882
1883static void cortex_m3_initfn(Object *obj)
1884{
1885    ARMCPU *cpu = ARM_CPU(obj);
1886    set_feature(&cpu->env, ARM_FEATURE_V7);
1887    set_feature(&cpu->env, ARM_FEATURE_M);
1888    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1889    cpu->midr = 0x410fc231;
1890    cpu->pmsav7_dregion = 8;
1891    cpu->id_pfr0 = 0x00000030;
1892    cpu->id_pfr1 = 0x00000200;
1893    cpu->id_dfr0 = 0x00100000;
1894    cpu->id_afr0 = 0x00000000;
1895    cpu->id_mmfr0 = 0x00000030;
1896    cpu->id_mmfr1 = 0x00000000;
1897    cpu->id_mmfr2 = 0x00000000;
1898    cpu->id_mmfr3 = 0x00000000;
1899    cpu->isar.id_isar0 = 0x01141110;
1900    cpu->isar.id_isar1 = 0x02111000;
1901    cpu->isar.id_isar2 = 0x21112231;
1902    cpu->isar.id_isar3 = 0x01111110;
1903    cpu->isar.id_isar4 = 0x01310102;
1904    cpu->isar.id_isar5 = 0x00000000;
1905    cpu->isar.id_isar6 = 0x00000000;
1906}
1907
1908static void cortex_m4_initfn(Object *obj)
1909{
1910    ARMCPU *cpu = ARM_CPU(obj);
1911
1912    set_feature(&cpu->env, ARM_FEATURE_V7);
1913    set_feature(&cpu->env, ARM_FEATURE_M);
1914    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1915    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1916    set_feature(&cpu->env, ARM_FEATURE_VFP4);
1917    cpu->midr = 0x410fc240; /* r0p0 */
1918    cpu->pmsav7_dregion = 8;
1919    cpu->isar.mvfr0 = 0x10110021;
1920    cpu->isar.mvfr1 = 0x11000011;
1921    cpu->isar.mvfr2 = 0x00000000;
1922    cpu->id_pfr0 = 0x00000030;
1923    cpu->id_pfr1 = 0x00000200;
1924    cpu->id_dfr0 = 0x00100000;
1925    cpu->id_afr0 = 0x00000000;
1926    cpu->id_mmfr0 = 0x00000030;
1927    cpu->id_mmfr1 = 0x00000000;
1928    cpu->id_mmfr2 = 0x00000000;
1929    cpu->id_mmfr3 = 0x00000000;
1930    cpu->isar.id_isar0 = 0x01141110;
1931    cpu->isar.id_isar1 = 0x02111000;
1932    cpu->isar.id_isar2 = 0x21112231;
1933    cpu->isar.id_isar3 = 0x01111110;
1934    cpu->isar.id_isar4 = 0x01310102;
1935    cpu->isar.id_isar5 = 0x00000000;
1936    cpu->isar.id_isar6 = 0x00000000;
1937}
1938
1939static void cortex_m33_initfn(Object *obj)
1940{
1941    ARMCPU *cpu = ARM_CPU(obj);
1942
1943    set_feature(&cpu->env, ARM_FEATURE_V8);
1944    set_feature(&cpu->env, ARM_FEATURE_M);
1945    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1946    set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1947    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1948    set_feature(&cpu->env, ARM_FEATURE_VFP4);
1949    cpu->midr = 0x410fd213; /* r0p3 */
1950    cpu->pmsav7_dregion = 16;
1951    cpu->sau_sregion = 8;
1952    cpu->isar.mvfr0 = 0x10110021;
1953    cpu->isar.mvfr1 = 0x11000011;
1954    cpu->isar.mvfr2 = 0x00000040;
1955    cpu->id_pfr0 = 0x00000030;
1956    cpu->id_pfr1 = 0x00000210;
1957    cpu->id_dfr0 = 0x00200000;
1958    cpu->id_afr0 = 0x00000000;
1959    cpu->id_mmfr0 = 0x00101F40;
1960    cpu->id_mmfr1 = 0x00000000;
1961    cpu->id_mmfr2 = 0x01000000;
1962    cpu->id_mmfr3 = 0x00000000;
1963    cpu->isar.id_isar0 = 0x01101110;
1964    cpu->isar.id_isar1 = 0x02212000;
1965    cpu->isar.id_isar2 = 0x20232232;
1966    cpu->isar.id_isar3 = 0x01111131;
1967    cpu->isar.id_isar4 = 0x01310132;
1968    cpu->isar.id_isar5 = 0x00000000;
1969    cpu->isar.id_isar6 = 0x00000000;
1970    cpu->clidr = 0x00000000;
1971    cpu->ctr = 0x8000c000;
1972}
1973
1974static void arm_v7m_class_init(ObjectClass *oc, void *data)
1975{
1976    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1977    CPUClass *cc = CPU_CLASS(oc);
1978
1979    acc->info = data;
1980#ifndef CONFIG_USER_ONLY
1981    cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1982#endif
1983
1984    cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1985}
1986
1987static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1988    /* Dummy the TCM region regs for the moment */
1989    { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1990      .access = PL1_RW, .type = ARM_CP_CONST },
1991    { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1992      .access = PL1_RW, .type = ARM_CP_CONST },
1993    { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1994      .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1995    REGINFO_SENTINEL
1996};
1997
1998static void cortex_r5_initfn(Object *obj)
1999{
2000    ARMCPU *cpu = ARM_CPU(obj);
2001
2002    set_feature(&cpu->env, ARM_FEATURE_V7);
2003    set_feature(&cpu->env, ARM_FEATURE_V7MP);
2004    set_feature(&cpu->env, ARM_FEATURE_PMSA);
2005    cpu->midr = 0x411fc153; /* r1p3 */
2006    cpu->id_pfr0 = 0x0131;
2007    cpu->id_pfr1 = 0x001;
2008    cpu->id_dfr0 = 0x010400;
2009    cpu->id_afr0 = 0x0;
2010    cpu->id_mmfr0 = 0x0210030;
2011    cpu->id_mmfr1 = 0x00000000;
2012    cpu->id_mmfr2 = 0x01200000;
2013    cpu->id_mmfr3 = 0x0211;
2014    cpu->isar.id_isar0 = 0x02101111;
2015    cpu->isar.id_isar1 = 0x13112111;
2016    cpu->isar.id_isar2 = 0x21232141;
2017    cpu->isar.id_isar3 = 0x01112131;
2018    cpu->isar.id_isar4 = 0x0010142;
2019    cpu->isar.id_isar5 = 0x0;
2020    cpu->isar.id_isar6 = 0x0;
2021    cpu->mp_is_up = true;
2022    cpu->pmsav7_dregion = 16;
2023    define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
2024}
2025
2026static void cortex_r5f_initfn(Object *obj)
2027{
2028    ARMCPU *cpu = ARM_CPU(obj);
2029
2030    cortex_r5_initfn(obj);
2031    set_feature(&cpu->env, ARM_FEATURE_VFP3);
2032    cpu->isar.mvfr0 = 0x10110221;
2033    cpu->isar.mvfr1 = 0x00000011;
2034}
2035
2036static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
2037    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
2038      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2039    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2040      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2041    REGINFO_SENTINEL
2042};
2043
2044static void cortex_a8_initfn(Object *obj)
2045{
2046    ARMCPU *cpu = ARM_CPU(obj);
2047
2048    cpu->dtb_compatible = "arm,cortex-a8";
2049    set_feature(&cpu->env, ARM_FEATURE_V7);
2050    set_feature(&cpu->env, ARM_FEATURE_VFP3);
2051    set_feature(&cpu->env, ARM_FEATURE_NEON);
2052    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2053    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2054    set_feature(&cpu->env, ARM_FEATURE_EL3);
2055    cpu->midr = 0x410fc080;
2056    cpu->reset_fpsid = 0x410330c0;
2057    cpu->isar.mvfr0 = 0x11110222;
2058    cpu->isar.mvfr1 = 0x00011111;
2059    cpu->ctr = 0x82048004;
2060    cpu->reset_sctlr = 0x00c50078;
2061    cpu->id_pfr0 = 0x1031;
2062    cpu->id_pfr1 = 0x11;
2063    cpu->id_dfr0 = 0x400;
2064    cpu->id_afr0 = 0;
2065    cpu->id_mmfr0 = 0x31100003;
2066    cpu->id_mmfr1 = 0x20000000;
2067    cpu->id_mmfr2 = 0x01202000;
2068    cpu->id_mmfr3 = 0x11;
2069    cpu->isar.id_isar0 = 0x00101111;
2070    cpu->isar.id_isar1 = 0x12112111;
2071    cpu->isar.id_isar2 = 0x21232031;
2072    cpu->isar.id_isar3 = 0x11112131;
2073    cpu->isar.id_isar4 = 0x00111142;
2074    cpu->dbgdidr = 0x15141000;
2075    cpu->clidr = (1 << 27) | (2 << 24) | 3;
2076    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2077    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2078    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2079    cpu->reset_auxcr = 2;
2080    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
2081}
2082
2083static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
2084    /* power_control should be set to maximum latency. Again,
2085     * default to 0 and set by private hook
2086     */
2087    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2088      .access = PL1_RW, .resetvalue = 0,
2089      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
2090    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
2091      .access = PL1_RW, .resetvalue = 0,
2092      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
2093    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
2094      .access = PL1_RW, .resetvalue = 0,
2095      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
2096    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2097      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2098    /* TLB lockdown control */
2099    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
2100      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2101    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
2102      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2103    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
2104      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2105    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
2106      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2107    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
2108      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2109    REGINFO_SENTINEL
2110};
2111
2112static void cortex_a9_initfn(Object *obj)
2113{
2114    ARMCPU *cpu = ARM_CPU(obj);
2115
2116    cpu->dtb_compatible = "arm,cortex-a9";
2117    set_feature(&cpu->env, ARM_FEATURE_V7);
2118    set_feature(&cpu->env, ARM_FEATURE_VFP3);
2119    set_feature(&cpu->env, ARM_FEATURE_NEON);
2120    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2121    set_feature(&cpu->env, ARM_FEATURE_EL3);
2122    /* Note that A9 supports the MP extensions even for
2123     * A9UP and single-core A9MP (which are both different
2124     * and valid configurations; we don't model A9UP).
2125     */
2126    set_feature(&cpu->env, ARM_FEATURE_V7MP);
2127    set_feature(&cpu->env, ARM_FEATURE_CBAR);
2128    cpu->midr = 0x410fc090;
2129    cpu->reset_fpsid = 0x41033090;
2130    cpu->isar.mvfr0 = 0x11110222;
2131    cpu->isar.mvfr1 = 0x01111111;
2132    cpu->ctr = 0x80038003;
2133    cpu->reset_sctlr = 0x00c50078;
2134    cpu->id_pfr0 = 0x1031;
2135    cpu->id_pfr1 = 0x11;
2136    cpu->id_dfr0 = 0x000;
2137    cpu->id_afr0 = 0;
2138    cpu->id_mmfr0 = 0x00100103;
2139    cpu->id_mmfr1 = 0x20000000;
2140    cpu->id_mmfr2 = 0x01230000;
2141    cpu->id_mmfr3 = 0x00002111;
2142    cpu->isar.id_isar0 = 0x00101111;
2143    cpu->isar.id_isar1 = 0x13112111;
2144    cpu->isar.id_isar2 = 0x21232041;
2145    cpu->isar.id_isar3 = 0x11112131;
2146    cpu->isar.id_isar4 = 0x00111142;
2147    cpu->dbgdidr = 0x35141000;
2148    cpu->clidr = (1 << 27) | (1 << 24) | 3;
2149    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2150    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2151    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2152}
2153
2154#ifndef CONFIG_USER_ONLY
2155static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2156{
2157    MachineState *ms = MACHINE(qdev_get_machine());
2158
2159    /* Linux wants the number of processors from here.
2160     * Might as well set the interrupt-controller bit too.
2161     */
2162    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
2163}
2164#endif
2165
2166static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2167#ifndef CONFIG_USER_ONLY
2168    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2169      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2170      .writefn = arm_cp_write_ignore, },
2171#endif
2172    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2173      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2174    REGINFO_SENTINEL
2175};
2176
2177static void cortex_a7_initfn(Object *obj)
2178{
2179    ARMCPU *cpu = ARM_CPU(obj);
2180
2181    cpu->dtb_compatible = "arm,cortex-a7";
2182    set_feature(&cpu->env, ARM_FEATURE_V7VE);
2183    set_feature(&cpu->env, ARM_FEATURE_VFP4);
2184    set_feature(&cpu->env, ARM_FEATURE_NEON);
2185    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2186    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2187    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2188    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2189    set_feature(&cpu->env, ARM_FEATURE_EL2);
2190    set_feature(&cpu->env, ARM_FEATURE_EL3);
2191    set_feature(&cpu->env, ARM_FEATURE_PMU);
2192    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2193    cpu->midr = 0x410fc075;
2194    cpu->reset_fpsid = 0x41023075;
2195    cpu->isar.mvfr0 = 0x10110222;
2196    cpu->isar.mvfr1 = 0x11111111;
2197    cpu->ctr = 0x84448003;
2198    cpu->reset_sctlr = 0x00c50078;
2199    cpu->id_pfr0 = 0x00001131;
2200    cpu->id_pfr1 = 0x00011011;
2201    cpu->id_dfr0 = 0x02010555;
2202    cpu->id_afr0 = 0x00000000;
2203    cpu->id_mmfr0 = 0x10101105;
2204    cpu->id_mmfr1 = 0x40000000;
2205    cpu->id_mmfr2 = 0x01240000;
2206    cpu->id_mmfr3 = 0x02102211;
2207    /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2208     * table 4-41 gives 0x02101110, which includes the arm div insns.
2209     */
2210    cpu->isar.id_isar0 = 0x02101110;
2211    cpu->isar.id_isar1 = 0x13112111;
2212    cpu->isar.id_isar2 = 0x21232041;
2213    cpu->isar.id_isar3 = 0x11112131;
2214    cpu->isar.id_isar4 = 0x10011142;
2215    cpu->dbgdidr = 0x3515f005;
2216    cpu->clidr = 0x0a200023;
2217    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2218    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2219    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2220    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2221}
2222
2223static void cortex_a15_initfn(Object *obj)
2224{
2225    ARMCPU *cpu = ARM_CPU(obj);
2226
2227    cpu->dtb_compatible = "arm,cortex-a15";
2228    set_feature(&cpu->env, ARM_FEATURE_V7VE);
2229    set_feature(&cpu->env, ARM_FEATURE_VFP4);
2230    set_feature(&cpu->env, ARM_FEATURE_NEON);
2231    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2232    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2233    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2234    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2235    set_feature(&cpu->env, ARM_FEATURE_EL2);
2236    set_feature(&cpu->env, ARM_FEATURE_EL3);
2237    set_feature(&cpu->env, ARM_FEATURE_PMU);
2238    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
2239    cpu->midr = 0x412fc0f1;
2240    cpu->reset_fpsid = 0x410430f0;
2241    cpu->isar.mvfr0 = 0x10110222;
2242    cpu->isar.mvfr1 = 0x11111111;
2243    cpu->ctr = 0x8444c004;
2244    cpu->reset_sctlr = 0x00c50078;
2245    cpu->id_pfr0 = 0x00001131;
2246    cpu->id_pfr1 = 0x00011011;
2247    cpu->id_dfr0 = 0x02010555;
2248    cpu->id_afr0 = 0x00000000;
2249    cpu->id_mmfr0 = 0x10201105;
2250    cpu->id_mmfr1 = 0x20000000;
2251    cpu->id_mmfr2 = 0x01240000;
2252    cpu->id_mmfr3 = 0x02102211;
2253    cpu->isar.id_isar0 = 0x02101110;
2254    cpu->isar.id_isar1 = 0x13112111;
2255    cpu->isar.id_isar2 = 0x21232041;
2256    cpu->isar.id_isar3 = 0x11112131;
2257    cpu->isar.id_isar4 = 0x10011142;
2258    cpu->dbgdidr = 0x3515f021;
2259    cpu->clidr = 0x0a200023;
2260    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2261    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2262    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2263    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2264}
2265
2266static void ti925t_initfn(Object *obj)
2267{
2268    ARMCPU *cpu = ARM_CPU(obj);
2269    set_feature(&cpu->env, ARM_FEATURE_V4T);
2270    set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
2271    cpu->midr = ARM_CPUID_TI925T;
2272    cpu->ctr = 0x5109149;
2273    cpu->reset_sctlr = 0x00000070;
2274}
2275
2276static void sa1100_initfn(Object *obj)
2277{
2278    ARMCPU *cpu = ARM_CPU(obj);
2279
2280    cpu->dtb_compatible = "intel,sa1100";
2281    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2282    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2283    cpu->midr = 0x4401A11B;
2284    cpu->reset_sctlr = 0x00000070;
2285}
2286
2287static void sa1110_initfn(Object *obj)
2288{
2289    ARMCPU *cpu = ARM_CPU(obj);
2290    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2291    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2292    cpu->midr = 0x6901B119;
2293    cpu->reset_sctlr = 0x00000070;
2294}
2295
2296static void pxa250_initfn(Object *obj)
2297{
2298    ARMCPU *cpu = ARM_CPU(obj);
2299
2300    cpu->dtb_compatible = "marvell,xscale";
2301    set_feature(&cpu->env, ARM_FEATURE_V5);
2302    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2303    cpu->midr = 0x69052100;
2304    cpu->ctr = 0xd172172;
2305    cpu->reset_sctlr = 0x00000078;
2306}
2307
2308static void pxa255_initfn(Object *obj)
2309{
2310    ARMCPU *cpu = ARM_CPU(obj);
2311
2312    cpu->dtb_compatible = "marvell,xscale";
2313    set_feature(&cpu->env, ARM_FEATURE_V5);
2314    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2315    cpu->midr = 0x69052d00;
2316    cpu->ctr = 0xd172172;
2317    cpu->reset_sctlr = 0x00000078;
2318}
2319
2320static void pxa260_initfn(Object *obj)
2321{
2322    ARMCPU *cpu = ARM_CPU(obj);
2323
2324    cpu->dtb_compatible = "marvell,xscale";
2325    set_feature(&cpu->env, ARM_FEATURE_V5);
2326    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2327    cpu->midr = 0x69052903;
2328    cpu->ctr = 0xd172172;
2329    cpu->reset_sctlr = 0x00000078;
2330}
2331
2332static void pxa261_initfn(Object *obj)
2333{
2334    ARMCPU *cpu = ARM_CPU(obj);
2335
2336    cpu->dtb_compatible = "marvell,xscale";
2337    set_feature(&cpu->env, ARM_FEATURE_V5);
2338    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2339    cpu->midr = 0x69052d05;
2340    cpu->ctr = 0xd172172;
2341    cpu->reset_sctlr = 0x00000078;
2342}
2343
2344static void pxa262_initfn(Object *obj)
2345{
2346    ARMCPU *cpu = ARM_CPU(obj);
2347
2348    cpu->dtb_compatible = "marvell,xscale";
2349    set_feature(&cpu->env, ARM_FEATURE_V5);
2350    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2351    cpu->midr = 0x69052d06;
2352    cpu->ctr = 0xd172172;
2353    cpu->reset_sctlr = 0x00000078;
2354}
2355
2356static void pxa270a0_initfn(Object *obj)
2357{
2358    ARMCPU *cpu = ARM_CPU(obj);
2359
2360    cpu->dtb_compatible = "marvell,xscale";
2361    set_feature(&cpu->env, ARM_FEATURE_V5);
2362    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2363    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2364    cpu->midr = 0x69054110;
2365    cpu->ctr = 0xd172172;
2366    cpu->reset_sctlr = 0x00000078;
2367}
2368
2369static void pxa270a1_initfn(Object *obj)
2370{
2371    ARMCPU *cpu = ARM_CPU(obj);
2372
2373    cpu->dtb_compatible = "marvell,xscale";
2374    set_feature(&cpu->env, ARM_FEATURE_V5);
2375    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2376    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2377    cpu->midr = 0x69054111;
2378    cpu->ctr = 0xd172172;
2379    cpu->reset_sctlr = 0x00000078;
2380}
2381
2382static void pxa270b0_initfn(Object *obj)
2383{
2384    ARMCPU *cpu = ARM_CPU(obj);
2385
2386    cpu->dtb_compatible = "marvell,xscale";
2387    set_feature(&cpu->env, ARM_FEATURE_V5);
2388    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2389    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2390    cpu->midr = 0x69054112;
2391    cpu->ctr = 0xd172172;
2392    cpu->reset_sctlr = 0x00000078;
2393}
2394
2395static void pxa270b1_initfn(Object *obj)
2396{
2397    ARMCPU *cpu = ARM_CPU(obj);
2398
2399    cpu->dtb_compatible = "marvell,xscale";
2400    set_feature(&cpu->env, ARM_FEATURE_V5);
2401    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2402    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2403    cpu->midr = 0x69054113;
2404    cpu->ctr = 0xd172172;
2405    cpu->reset_sctlr = 0x00000078;
2406}
2407
2408static void pxa270c0_initfn(Object *obj)
2409{
2410    ARMCPU *cpu = ARM_CPU(obj);
2411
2412    cpu->dtb_compatible = "marvell,xscale";
2413    set_feature(&cpu->env, ARM_FEATURE_V5);
2414    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2415    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2416    cpu->midr = 0x69054114;
2417    cpu->ctr = 0xd172172;
2418    cpu->reset_sctlr = 0x00000078;
2419}
2420
2421static void pxa270c5_initfn(Object *obj)
2422{
2423    ARMCPU *cpu = ARM_CPU(obj);
2424
2425    cpu->dtb_compatible = "marvell,xscale";
2426    set_feature(&cpu->env, ARM_FEATURE_V5);
2427    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2428    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2429    cpu->midr = 0x69054117;
2430    cpu->ctr = 0xd172172;
2431    cpu->reset_sctlr = 0x00000078;
2432}
2433
2434#ifndef TARGET_AARCH64
2435/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2436 * otherwise, a CPU with as many features enabled as our emulation supports.
2437 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2438 * this only needs to handle 32 bits.
2439 */
2440static void arm_max_initfn(Object *obj)
2441{
2442    ARMCPU *cpu = ARM_CPU(obj);
2443
2444    if (kvm_enabled()) {
2445        kvm_arm_set_cpu_features_from_host(cpu);
2446    } else {
2447        cortex_a15_initfn(obj);
2448
2449        /* old-style VFP short-vector support */
2450        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2451
2452#ifdef CONFIG_USER_ONLY
2453        /* We don't set these in system emulation mode for the moment,
2454         * since we don't correctly set (all of) the ID registers to
2455         * advertise them.
2456         */
2457        set_feature(&cpu->env, ARM_FEATURE_V8);
2458        {
2459            uint32_t t;
2460
2461            t = cpu->isar.id_isar5;
2462            t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2463            t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2464            t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2465            t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2466            t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2467            t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2468            cpu->isar.id_isar5 = t;
2469
2470            t = cpu->isar.id_isar6;
2471            t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2472            t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2473            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2474            t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2475            t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2476            cpu->isar.id_isar6 = t;
2477
2478            t = cpu->isar.mvfr1;
2479            t = FIELD_DP32(t, MVFR1, FPHP, 2);     /* v8.0 FP support */
2480            cpu->isar.mvfr1 = t;
2481
2482            t = cpu->isar.mvfr2;
2483            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2484            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
2485            cpu->isar.mvfr2 = t;
2486
2487            t = cpu->id_mmfr4;
2488            t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2489            cpu->id_mmfr4 = t;
2490        }
2491#endif
2492    }
2493}
2494#endif
2495
2496#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2497
2498struct ARMCPUInfo {
2499    const char *name;
2500    void (*initfn)(Object *obj);
2501    void (*class_init)(ObjectClass *oc, void *data);
2502};
2503
2504static const ARMCPUInfo arm_cpus[] = {
2505#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2506    { .name = "arm926",      .initfn = arm926_initfn },
2507    { .name = "arm946",      .initfn = arm946_initfn },
2508    { .name = "arm1026",     .initfn = arm1026_initfn },
2509    /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2510     * older core than plain "arm1136". In particular this does not
2511     * have the v6K features.
2512     */
2513    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
2514    { .name = "arm1136",     .initfn = arm1136_initfn },
2515    { .name = "arm1176",     .initfn = arm1176_initfn },
2516    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
2517    { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
2518                             .class_init = arm_v7m_class_init },
2519    { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
2520                             .class_init = arm_v7m_class_init },
2521    { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
2522                             .class_init = arm_v7m_class_init },
2523    { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
2524                             .class_init = arm_v7m_class_init },
2525    { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
2526    { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
2527    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
2528    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
2529    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
2530    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
2531    { .name = "ti925t",      .initfn = ti925t_initfn },
2532    { .name = "sa1100",      .initfn = sa1100_initfn },
2533    { .name = "sa1110",      .initfn = sa1110_initfn },
2534    { .name = "pxa250",      .initfn = pxa250_initfn },
2535    { .name = "pxa255",      .initfn = pxa255_initfn },
2536    { .name = "pxa260",      .initfn = pxa260_initfn },
2537    { .name = "pxa261",      .initfn = pxa261_initfn },
2538    { .name = "pxa262",      .initfn = pxa262_initfn },
2539    /* "pxa270" is an alias for "pxa270-a0" */
2540    { .name = "pxa270",      .initfn = pxa270a0_initfn },
2541    { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
2542    { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
2543    { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
2544    { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
2545    { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
2546    { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
2547#ifndef TARGET_AARCH64
2548    { .name = "max",         .initfn = arm_max_initfn },
2549#endif
2550#ifdef CONFIG_USER_ONLY
2551    { .name = "any",         .initfn = arm_max_initfn },
2552#endif
2553#endif
2554    { .name = NULL }
2555};
2556
2557static Property arm_cpu_properties[] = {
2558    DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2559    DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2560    DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2561    DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2562                        mp_affinity, ARM64_AFFINITY_INVALID),
2563    DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2564    DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2565    DEFINE_PROP_END_OF_LIST()
2566};
2567
2568static gchar *arm_gdb_arch_name(CPUState *cs)
2569{
2570    ARMCPU *cpu = ARM_CPU(cs);
2571    CPUARMState *env = &cpu->env;
2572
2573    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2574        return g_strdup("iwmmxt");
2575    }
2576    return g_strdup("arm");
2577}
2578
2579static void arm_cpu_class_init(ObjectClass *oc, void *data)
2580{
2581    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2582    CPUClass *cc = CPU_CLASS(acc);
2583    DeviceClass *dc = DEVICE_CLASS(oc);
2584
2585    device_class_set_parent_realize(dc, arm_cpu_realizefn,
2586                                    &acc->parent_realize);
2587    dc->props = arm_cpu_properties;
2588
2589    acc->parent_reset = cc->reset;
2590    cc->reset = arm_cpu_reset;
2591
2592    cc->class_by_name = arm_cpu_class_by_name;
2593    cc->has_work = arm_cpu_has_work;
2594    cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2595    cc->dump_state = arm_cpu_dump_state;
2596    cc->set_pc = arm_cpu_set_pc;
2597    cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
2598    cc->gdb_read_register = arm_cpu_gdb_read_register;
2599    cc->gdb_write_register = arm_cpu_gdb_write_register;
2600#ifndef CONFIG_USER_ONLY
2601    cc->do_interrupt = arm_cpu_do_interrupt;
2602    cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2603    cc->asidx_from_attrs = arm_asidx_from_attrs;
2604    cc->vmsd = &vmstate_arm_cpu;
2605    cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2606    cc->write_elf64_note = arm_cpu_write_elf64_note;
2607    cc->write_elf32_note = arm_cpu_write_elf32_note;
2608#endif
2609    cc->gdb_num_core_regs = 26;
2610    cc->gdb_core_xml_file = "arm-core.xml";
2611    cc->gdb_arch_name = arm_gdb_arch_name;
2612    cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2613    cc->gdb_stop_before_watchpoint = true;
2614    cc->disas_set_info = arm_disas_set_info;
2615#ifdef CONFIG_TCG
2616    cc->tcg_initialize = arm_translate_init;
2617    cc->tlb_fill = arm_cpu_tlb_fill;
2618    cc->debug_excp_handler = arm_debug_excp_handler;
2619    cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2620#if !defined(CONFIG_USER_ONLY)
2621    cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2622    cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2623    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2624#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2625#endif
2626}
2627
2628#ifdef CONFIG_KVM
2629static void arm_host_initfn(Object *obj)
2630{
2631    ARMCPU *cpu = ARM_CPU(obj);
2632
2633    kvm_arm_set_cpu_features_from_host(cpu);
2634    arm_cpu_post_init(obj);
2635}
2636
2637static const TypeInfo host_arm_cpu_type_info = {
2638    .name = TYPE_ARM_HOST_CPU,
2639#ifdef TARGET_AARCH64
2640    .parent = TYPE_AARCH64_CPU,
2641#else
2642    .parent = TYPE_ARM_CPU,
2643#endif
2644    .instance_init = arm_host_initfn,
2645};
2646
2647#endif
2648
2649static void arm_cpu_instance_init(Object *obj)
2650{
2651    ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2652
2653    acc->info->initfn(obj);
2654    arm_cpu_post_init(obj);
2655}
2656
2657static void cpu_register_class_init(ObjectClass *oc, void *data)
2658{
2659    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2660
2661    acc->info = data;
2662}
2663
2664static void cpu_register(const ARMCPUInfo *info)
2665{
2666    TypeInfo type_info = {
2667        .parent = TYPE_ARM_CPU,
2668        .instance_size = sizeof(ARMCPU),
2669        .instance_init = arm_cpu_instance_init,
2670        .class_size = sizeof(ARMCPUClass),
2671        .class_init = info->class_init ?: cpu_register_class_init,
2672        .class_data = (void *)info,
2673    };
2674
2675    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2676    type_register(&type_info);
2677    g_free((void *)type_info.name);
2678}
2679
2680static const TypeInfo arm_cpu_type_info = {
2681    .name = TYPE_ARM_CPU,
2682    .parent = TYPE_CPU,
2683    .instance_size = sizeof(ARMCPU),
2684    .instance_init = arm_cpu_initfn,
2685    .instance_finalize = arm_cpu_finalizefn,
2686    .abstract = true,
2687    .class_size = sizeof(ARMCPUClass),
2688    .class_init = arm_cpu_class_init,
2689};
2690
2691static const TypeInfo idau_interface_type_info = {
2692    .name = TYPE_IDAU_INTERFACE,
2693    .parent = TYPE_INTERFACE,
2694    .class_size = sizeof(IDAUInterfaceClass),
2695};
2696
2697static void arm_cpu_register_types(void)
2698{
2699    const ARMCPUInfo *info = arm_cpus;
2700
2701    type_register_static(&arm_cpu_type_info);
2702    type_register_static(&idau_interface_type_info);
2703
2704    while (info->name) {
2705        cpu_register(info);
2706        info++;
2707    }
2708
2709#ifdef CONFIG_KVM
2710    type_register_static(&host_arm_cpu_type_info);
2711#endif
2712}
2713
2714type_init(arm_cpu_register_types)
2715