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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28
29
30#define TCG_GUEST_DEFAULT_MO (0)
31
32#ifdef TARGET_AARCH64
33#define KVM_HAVE_MCE_INJECTION 1
34#endif
35
36#define EXCP_UDEF 1
37#define EXCP_SWI 2
38#define EXCP_PREFETCH_ABORT 3
39#define EXCP_DATA_ABORT 4
40#define EXCP_IRQ 5
41#define EXCP_FIQ 6
42#define EXCP_BKPT 7
43#define EXCP_EXCEPTION_EXIT 8
44#define EXCP_KERNEL_TRAP 9
45#define EXCP_HVC 11
46#define EXCP_HYP_TRAP 12
47#define EXCP_SMC 13
48#define EXCP_VIRQ 14
49#define EXCP_VFIQ 15
50#define EXCP_SEMIHOST 16
51#define EXCP_NOCP 17
52#define EXCP_INVSTATE 18
53#define EXCP_STKOF 19
54#define EXCP_LAZYFP 20
55#define EXCP_LSERR 21
56#define EXCP_UNALIGNED 22
57#define EXCP_DIVBYZERO 23
58
59
60#define ARMV7M_EXCP_RESET 1
61#define ARMV7M_EXCP_NMI 2
62#define ARMV7M_EXCP_HARD 3
63#define ARMV7M_EXCP_MEM 4
64#define ARMV7M_EXCP_BUS 5
65#define ARMV7M_EXCP_USAGE 6
66#define ARMV7M_EXCP_SECURE 7
67#define ARMV7M_EXCP_SVC 11
68#define ARMV7M_EXCP_DEBUG 12
69#define ARMV7M_EXCP_PENDSV 14
70#define ARMV7M_EXCP_SYSTICK 15
71
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80
81enum {
82 M_REG_NS = 0,
83 M_REG_S = 1,
84 M_REG_NUM_BANKS = 2,
85};
86
87
88#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
89#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
90#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
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97
98#ifdef HOST_WORDS_BIGENDIAN
99#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
100#define offsetofhigh32(S, M) offsetof(S, M)
101#else
102#define offsetoflow32(S, M) offsetof(S, M)
103#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
104#endif
105
106
107#define ARM_CPU_IRQ 0
108#define ARM_CPU_FIQ 1
109#define ARM_CPU_VIRQ 2
110#define ARM_CPU_VFIQ 3
111
112
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114
115
116#define TARGET_INSN_START_EXTRA_WORDS 2
117
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122
123#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
124#define ARM_INSN_START_WORD2_SHIFT 14
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142
143typedef struct DynamicGDBXMLInfo {
144 char *desc;
145 int num;
146 union {
147 struct {
148 uint32_t *keys;
149 } cpregs;
150 } data;
151} DynamicGDBXMLInfo;
152
153
154typedef struct ARMGenericTimer {
155 uint64_t cval;
156 uint64_t ctl;
157} ARMGenericTimer;
158
159#define GTIMER_PHYS 0
160#define GTIMER_VIRT 1
161#define GTIMER_HYP 2
162#define GTIMER_SEC 3
163#define GTIMER_HYPVIRT 4
164#define NUM_GTIMERS 5
165
166typedef struct {
167 uint64_t raw_tcr;
168 uint32_t mask;
169 uint32_t base_mask;
170} TCR;
171
172#define VTCR_NSW (1u << 29)
173#define VTCR_NSA (1u << 30)
174#define VSTCR_SW VTCR_NSW
175#define VSTCR_SA VTCR_NSA
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203#ifdef TARGET_AARCH64
204# define ARM_MAX_VQ 16
205void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
206void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
207#else
208# define ARM_MAX_VQ 1
209static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
210static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
211#endif
212
213typedef struct ARMVectorReg {
214 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
215} ARMVectorReg;
216
217#ifdef TARGET_AARCH64
218
219typedef struct ARMPredicateReg {
220 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
221} ARMPredicateReg;
222
223
224typedef struct ARMPACKey {
225 uint64_t lo, hi;
226} ARMPACKey;
227#endif
228
229
230typedef struct CPUARMTBFlags {
231 uint32_t flags;
232 target_ulong flags2;
233} CPUARMTBFlags;
234
235typedef struct CPUARMState {
236
237 uint32_t regs[16];
238
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243
244 uint64_t xregs[32];
245 uint64_t pc;
246
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257
258 uint32_t pstate;
259 uint32_t aarch64;
260
261
262 CPUARMTBFlags hflags;
263
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266
267 uint32_t uncached_cpsr;
268 uint32_t spsr;
269
270
271 uint64_t banked_spsr[8];
272 uint32_t banked_r13[8];
273 uint32_t banked_r14[8];
274
275
276 uint32_t usr_regs[5];
277 uint32_t fiq_regs[5];
278
279
280 uint32_t CF;
281 uint32_t VF;
282 uint32_t NF;
283 uint32_t ZF;
284 uint32_t QF;
285 uint32_t GE;
286 uint32_t thumb;
287 uint32_t condexec_bits;
288 uint32_t btype;
289 uint64_t daif;
290
291 uint64_t elr_el[4];
292 uint64_t sp_el[4];
293
294
295 struct {
296 uint32_t c0_cpuid;
297 union {
298 struct {
299 uint64_t _unused_csselr0;
300 uint64_t csselr_ns;
301 uint64_t _unused_csselr1;
302 uint64_t csselr_s;
303 };
304 uint64_t csselr_el[4];
305 };
306 union {
307 struct {
308 uint64_t _unused_sctlr;
309 uint64_t sctlr_ns;
310 uint64_t hsctlr;
311 uint64_t sctlr_s;
312 };
313 uint64_t sctlr_el[4];
314 };
315 uint64_t cpacr_el1;
316 uint64_t cptr_el[4];
317 uint32_t c1_xscaleauxcr;
318 uint64_t sder;
319 uint32_t nsacr;
320 union {
321 struct {
322 uint64_t _unused_ttbr0_0;
323 uint64_t ttbr0_ns;
324 uint64_t _unused_ttbr0_1;
325 uint64_t ttbr0_s;
326 };
327 uint64_t ttbr0_el[4];
328 };
329 union {
330 struct {
331 uint64_t _unused_ttbr1_0;
332 uint64_t ttbr1_ns;
333 uint64_t _unused_ttbr1_1;
334 uint64_t ttbr1_s;
335 };
336 uint64_t ttbr1_el[4];
337 };
338 uint64_t vttbr_el2;
339 uint64_t vsttbr_el2;
340
341 TCR tcr_el[4];
342 TCR vtcr_el2;
343 TCR vstcr_el2;
344 uint32_t c2_data;
345 uint32_t c2_insn;
346 union {
347
348
349 struct {
350 uint64_t dacr_ns;
351 uint64_t dacr_s;
352 };
353 struct {
354 uint64_t dacr32_el2;
355 };
356 };
357 uint32_t pmsav5_data_ap;
358 uint32_t pmsav5_insn_ap;
359 uint64_t hcr_el2;
360 uint64_t scr_el3;
361 union {
362 struct {
363 uint64_t ifsr_ns;
364 uint64_t ifsr_s;
365 };
366 struct {
367 uint64_t ifsr32_el2;
368 };
369 };
370 union {
371 struct {
372 uint64_t _unused_dfsr;
373 uint64_t dfsr_ns;
374 uint64_t hsr;
375 uint64_t dfsr_s;
376 };
377 uint64_t esr_el[4];
378 };
379 uint32_t c6_region[8];
380 union {
381 struct {
382 uint64_t _unused_far0;
383#ifdef HOST_WORDS_BIGENDIAN
384 uint32_t ifar_ns;
385 uint32_t dfar_ns;
386 uint32_t ifar_s;
387 uint32_t dfar_s;
388#else
389 uint32_t dfar_ns;
390 uint32_t ifar_ns;
391 uint32_t dfar_s;
392 uint32_t ifar_s;
393#endif
394 uint64_t _unused_far3;
395 };
396 uint64_t far_el[4];
397 };
398 uint64_t hpfar_el2;
399 uint64_t hstr_el2;
400 union {
401 struct {
402 uint64_t _unused_par_0;
403 uint64_t par_ns;
404 uint64_t _unused_par_1;
405 uint64_t par_s;
406 };
407 uint64_t par_el[4];
408 };
409
410 uint32_t c9_insn;
411 uint32_t c9_data;
412 uint64_t c9_pmcr;
413 uint64_t c9_pmcnten;
414 uint64_t c9_pmovsr;
415 uint64_t c9_pmuserenr;
416 uint64_t c9_pmselr;
417 uint64_t c9_pminten;
418 union {
419 struct {
420#ifdef HOST_WORDS_BIGENDIAN
421 uint64_t _unused_mair_0;
422 uint32_t mair1_ns;
423 uint32_t mair0_ns;
424 uint64_t _unused_mair_1;
425 uint32_t mair1_s;
426 uint32_t mair0_s;
427#else
428 uint64_t _unused_mair_0;
429 uint32_t mair0_ns;
430 uint32_t mair1_ns;
431 uint64_t _unused_mair_1;
432 uint32_t mair0_s;
433 uint32_t mair1_s;
434#endif
435 };
436 uint64_t mair_el[4];
437 };
438 union {
439 struct {
440 uint64_t _unused_vbar;
441 uint64_t vbar_ns;
442 uint64_t hvbar;
443 uint64_t vbar_s;
444 };
445 uint64_t vbar_el[4];
446 };
447 uint32_t mvbar;
448 struct {
449 uint32_t fcseidr_ns;
450 uint32_t fcseidr_s;
451 };
452 union {
453 struct {
454 uint64_t _unused_contextidr_0;
455 uint64_t contextidr_ns;
456 uint64_t _unused_contextidr_1;
457 uint64_t contextidr_s;
458 };
459 uint64_t contextidr_el[4];
460 };
461 union {
462 struct {
463 uint64_t tpidrurw_ns;
464 uint64_t tpidrprw_ns;
465 uint64_t htpidr;
466 uint64_t _tpidr_el3;
467 };
468 uint64_t tpidr_el[4];
469 };
470
471 uint64_t tpidrurw_s;
472 uint64_t tpidrprw_s;
473 uint64_t tpidruro_s;
474
475 union {
476 uint64_t tpidruro_ns;
477 uint64_t tpidrro_el[1];
478 };
479 uint64_t c14_cntfrq;
480 uint64_t c14_cntkctl;
481 uint32_t cnthctl_el2;
482 uint64_t cntvoff_el2;
483 ARMGenericTimer c14_timer[NUM_GTIMERS];
484 uint32_t c15_cpar;
485 uint32_t c15_ticonfig;
486 uint32_t c15_i_max;
487 uint32_t c15_i_min;
488 uint32_t c15_threadid;
489 uint32_t c15_config_base_address;
490 uint32_t c15_diagnostic;
491 uint32_t c15_power_diagnostic;
492 uint32_t c15_power_control;
493 uint64_t dbgbvr[16];
494 uint64_t dbgbcr[16];
495 uint64_t dbgwvr[16];
496 uint64_t dbgwcr[16];
497 uint64_t mdscr_el1;
498 uint64_t oslsr_el1;
499 uint64_t mdcr_el2;
500 uint64_t mdcr_el3;
501
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505
506 uint64_t c15_ccnt;
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514 uint64_t c15_ccnt_delta;
515 uint64_t c14_pmevcntr[31];
516 uint64_t c14_pmevcntr_delta[31];
517 uint64_t c14_pmevtyper[31];
518 uint64_t pmccfiltr_el0;
519 uint64_t vpidr_el2;
520 uint64_t vmpidr_el2;
521 uint64_t tfsr_el[4];
522 uint64_t gcr_el1;
523 uint64_t rgsr_el1;
524 } cp15;
525
526 struct {
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537
538 uint32_t other_sp;
539 uint32_t other_ss_msp;
540 uint32_t other_ss_psp;
541 uint32_t vecbase[M_REG_NUM_BANKS];
542 uint32_t basepri[M_REG_NUM_BANKS];
543 uint32_t control[M_REG_NUM_BANKS];
544 uint32_t ccr[M_REG_NUM_BANKS];
545 uint32_t cfsr[M_REG_NUM_BANKS];
546 uint32_t hfsr;
547 uint32_t dfsr;
548 uint32_t sfsr;
549 uint32_t mmfar[M_REG_NUM_BANKS];
550 uint32_t bfar;
551 uint32_t sfar;
552 unsigned mpu_ctrl[M_REG_NUM_BANKS];
553 int exception;
554 uint32_t primask[M_REG_NUM_BANKS];
555 uint32_t faultmask[M_REG_NUM_BANKS];
556 uint32_t aircr;
557 uint32_t secure;
558 uint32_t csselr[M_REG_NUM_BANKS];
559 uint32_t scr[M_REG_NUM_BANKS];
560 uint32_t msplim[M_REG_NUM_BANKS];
561 uint32_t psplim[M_REG_NUM_BANKS];
562 uint32_t fpcar[M_REG_NUM_BANKS];
563 uint32_t fpccr[M_REG_NUM_BANKS];
564 uint32_t fpdscr[M_REG_NUM_BANKS];
565 uint32_t cpacr[M_REG_NUM_BANKS];
566 uint32_t nsacr;
567 uint32_t ltpsize;
568 uint32_t vpr;
569 } v7m;
570
571
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576
577 struct {
578 uint32_t syndrome;
579 uint32_t fsr;
580 uint64_t vaddress;
581 uint32_t target_el;
582
583
584
585 } exception;
586
587
588 struct {
589 uint8_t pending;
590 uint8_t has_esr;
591 uint64_t esr;
592 } serror;
593
594 uint8_t ext_dabt_raised;
595
596
597 uint32_t irq_line_state;
598
599
600 uint32_t teecr;
601 uint32_t teehbr;
602
603
604 struct {
605 ARMVectorReg zregs[32];
606
607#ifdef TARGET_AARCH64
608
609#define FFR_PRED_NUM 16
610 ARMPredicateReg pregs[17];
611
612 ARMPredicateReg preg_tmp;
613#endif
614
615
616 uint32_t qc[4] QEMU_ALIGNED(16);
617 int vec_len;
618 int vec_stride;
619
620 uint32_t xregs[16];
621
622
623 uint32_t scratch[8];
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652 float_status fp_status;
653 float_status fp_status_f16;
654 float_status standard_fp_status;
655 float_status standard_fp_status_f16;
656
657
658 uint64_t zcr_el[4];
659 } vfp;
660 uint64_t exclusive_addr;
661 uint64_t exclusive_val;
662 uint64_t exclusive_high;
663
664
665 struct {
666 uint64_t regs[16];
667 uint64_t val;
668
669 uint32_t cregs[16];
670 } iwmmxt;
671
672#ifdef TARGET_AARCH64
673 struct {
674 ARMPACKey apia;
675 ARMPACKey apib;
676 ARMPACKey apda;
677 ARMPACKey apdb;
678 ARMPACKey apga;
679 } keys;
680#endif
681
682#if defined(CONFIG_USER_ONLY)
683
684 int eabi;
685#endif
686
687 struct CPUBreakpoint *cpu_breakpoint[16];
688 struct CPUWatchpoint *cpu_watchpoint[16];
689
690
691 struct {} end_reset_fields;
692
693
694
695
696 uint64_t features;
697
698
699 struct {
700 uint32_t *drbar;
701 uint32_t *drsr;
702 uint32_t *dracr;
703 uint32_t rnr[M_REG_NUM_BANKS];
704 } pmsav7;
705
706
707 struct {
708
709
710
711
712
713 uint32_t *rbar[M_REG_NUM_BANKS];
714 uint32_t *rlar[M_REG_NUM_BANKS];
715 uint32_t mair0[M_REG_NUM_BANKS];
716 uint32_t mair1[M_REG_NUM_BANKS];
717 } pmsav8;
718
719
720 struct {
721 uint32_t *rbar;
722 uint32_t *rlar;
723 uint32_t rnr;
724 uint32_t ctrl;
725 } sau;
726
727 void *nvic;
728 const struct arm_boot_info *boot_info;
729
730 void *gicv3state;
731
732#ifdef TARGET_TAGGED_ADDRESSES
733
734 bool tagged_addr_enable;
735#endif
736} CPUARMState;
737
738static inline void set_feature(CPUARMState *env, int feature)
739{
740 env->features |= 1ULL << feature;
741}
742
743static inline void unset_feature(CPUARMState *env, int feature)
744{
745 env->features &= ~(1ULL << feature);
746}
747
748
749
750
751
752
753typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
754typedef struct ARMELChangeHook ARMELChangeHook;
755struct ARMELChangeHook {
756 ARMELChangeHookFn *hook;
757 void *opaque;
758 QLIST_ENTRY(ARMELChangeHook) node;
759};
760
761
762
763typedef enum ARMPSCIState {
764 PSCI_ON = 0,
765 PSCI_OFF = 1,
766 PSCI_ON_PENDING = 2
767} ARMPSCIState;
768
769typedef struct ARMISARegisters ARMISARegisters;
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776
777struct ARMCPU {
778
779 CPUState parent_obj;
780
781
782 CPUNegativeOffsetState neg;
783 CPUARMState env;
784
785
786 GHashTable *cp_regs;
787
788
789
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793
794 uint64_t *cpreg_indexes;
795
796 uint64_t *cpreg_values;
797
798 int32_t cpreg_array_len;
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802
803 uint64_t *cpreg_vmstate_indexes;
804 uint64_t *cpreg_vmstate_values;
805 int32_t cpreg_vmstate_array_len;
806
807 DynamicGDBXMLInfo dyn_sysreg_xml;
808 DynamicGDBXMLInfo dyn_svereg_xml;
809
810
811 QEMUTimer *gt_timer[NUM_GTIMERS];
812
813
814
815
816 QEMUTimer *pmu_timer;
817
818 qemu_irq gt_timer_outputs[NUM_GTIMERS];
819
820 qemu_irq gicv3_maintenance_interrupt;
821
822 qemu_irq pmu_interrupt;
823
824
825 MemoryRegion *secure_memory;
826
827
828 MemoryRegion *tag_memory;
829 MemoryRegion *secure_tag_memory;
830
831
832 Object *idau;
833
834
835 const char *dtb_compatible;
836
837
838
839
840
841 uint32_t psci_version;
842
843
844 ARMPSCIState power_state;
845
846
847 bool has_el2;
848
849 bool has_el3;
850
851 bool has_pmu;
852
853 bool has_vfp;
854
855 bool has_neon;
856
857 bool has_dsp;
858
859
860 bool has_mpu;
861
862 uint32_t pmsav7_dregion;
863
864 uint32_t sau_sregion;
865
866
867
868
869 uint32_t psci_conduit;
870
871
872 uint32_t init_svtor;
873
874 uint32_t init_nsvtor;
875
876
877
878
879 uint32_t kvm_target;
880
881
882 uint32_t kvm_init_features[7];
883
884
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886
887 bool kvm_adjvtime;
888 bool kvm_vtime_dirty;
889 uint64_t kvm_vtime;
890
891
892 OnOffAuto kvm_steal_time;
893
894
895 bool mp_is_up;
896
897
898
899
900 bool host_cpu_probe_failed;
901
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904
905 int32_t core_count;
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923
924 struct ARMISARegisters {
925 uint32_t id_isar0;
926 uint32_t id_isar1;
927 uint32_t id_isar2;
928 uint32_t id_isar3;
929 uint32_t id_isar4;
930 uint32_t id_isar5;
931 uint32_t id_isar6;
932 uint32_t id_mmfr0;
933 uint32_t id_mmfr1;
934 uint32_t id_mmfr2;
935 uint32_t id_mmfr3;
936 uint32_t id_mmfr4;
937 uint32_t id_pfr0;
938 uint32_t id_pfr1;
939 uint32_t id_pfr2;
940 uint32_t mvfr0;
941 uint32_t mvfr1;
942 uint32_t mvfr2;
943 uint32_t id_dfr0;
944 uint32_t dbgdidr;
945 uint64_t id_aa64isar0;
946 uint64_t id_aa64isar1;
947 uint64_t id_aa64pfr0;
948 uint64_t id_aa64pfr1;
949 uint64_t id_aa64mmfr0;
950 uint64_t id_aa64mmfr1;
951 uint64_t id_aa64mmfr2;
952 uint64_t id_aa64dfr0;
953 uint64_t id_aa64dfr1;
954 uint64_t id_aa64zfr0;
955 } isar;
956 uint64_t midr;
957 uint32_t revidr;
958 uint32_t reset_fpsid;
959 uint64_t ctr;
960 uint32_t reset_sctlr;
961 uint64_t pmceid0;
962 uint64_t pmceid1;
963 uint32_t id_afr0;
964 uint64_t id_aa64afr0;
965 uint64_t id_aa64afr1;
966 uint64_t clidr;
967 uint64_t mp_affinity;
968
969
970
971 uint64_t ccsidr[16];
972 uint64_t reset_cbar;
973 uint32_t reset_auxcr;
974 bool reset_hivecs;
975
976
977
978
979
980 bool prop_pauth;
981 bool prop_pauth_impdef;
982
983
984 uint32_t dcz_blocksize;
985 uint64_t rvbar;
986
987
988 int gic_num_lrs;
989 int gic_vpribits;
990 int gic_vprebits;
991
992
993
994
995
996
997 bool cfgend;
998
999 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1000 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1001
1002 int32_t node_id;
1003
1004
1005 uint8_t device_irq_level;
1006
1007
1008 uint32_t sve_max_vq;
1009
1010#ifdef CONFIG_USER_ONLY
1011
1012 uint32_t sve_default_vq;
1013#endif
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
1028 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
1029 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ);
1030
1031
1032 uint64_t gt_cntfrq_hz;
1033};
1034
1035unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1036
1037void arm_cpu_post_init(Object *obj);
1038
1039uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1040
1041#ifndef CONFIG_USER_ONLY
1042extern const VMStateDescription vmstate_arm_cpu;
1043
1044void arm_cpu_do_interrupt(CPUState *cpu);
1045void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1046#endif
1047
1048hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1049 MemTxAttrs *attrs);
1050
1051int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1052int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1053
1054
1055
1056
1057
1058int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1059int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1060
1061
1062
1063
1064
1065const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1066
1067int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1068 int cpuid, void *opaque);
1069int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1070 int cpuid, void *opaque);
1071
1072#ifdef TARGET_AARCH64
1073int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1074int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1075void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1076void aarch64_sve_change_el(CPUARMState *env, int old_el,
1077 int new_el, bool el0_a64);
1078void aarch64_add_sve_properties(Object *obj);
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1090{
1091#ifdef HOST_WORDS_BIGENDIAN
1092 int i;
1093
1094 for (i = 0; i < nr; ++i) {
1095 dst[i] = bswap64(src[i]);
1096 }
1097
1098 return dst;
1099#else
1100 return src;
1101#endif
1102}
1103
1104#else
1105static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1106static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1107 int n, bool a)
1108{ }
1109static inline void aarch64_add_sve_properties(Object *obj) { }
1110#endif
1111
1112void aarch64_sync_32_to_64(CPUARMState *env);
1113void aarch64_sync_64_to_32(CPUARMState *env);
1114
1115int fp_exception_el(CPUARMState *env, int cur_el);
1116int sve_exception_el(CPUARMState *env, int cur_el);
1117uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1118
1119static inline bool is_a64(CPUARMState *env)
1120{
1121 return env->aarch64;
1122}
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132void pmu_op_start(CPUARMState *env);
1133void pmu_op_finish(CPUARMState *env);
1134
1135
1136
1137
1138void arm_pmu_timer_cb(void *opaque);
1139
1140
1141
1142
1143void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1144void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1145
1146
1147
1148
1149
1150
1151
1152
1153void pmu_init(ARMCPU *cpu);
1154
1155
1156
1157
1158
1159
1160
1161#define SCTLR_M (1U << 0)
1162#define SCTLR_A (1U << 1)
1163#define SCTLR_C (1U << 2)
1164#define SCTLR_W (1U << 3)
1165#define SCTLR_nTLSMD_32 (1U << 3)
1166#define SCTLR_SA (1U << 3)
1167#define SCTLR_P (1U << 4)
1168#define SCTLR_LSMAOE_32 (1U << 4)
1169#define SCTLR_SA0 (1U << 4)
1170#define SCTLR_D (1U << 5)
1171#define SCTLR_CP15BEN (1U << 5)
1172#define SCTLR_L (1U << 6)
1173#define SCTLR_nAA (1U << 6)
1174#define SCTLR_B (1U << 7)
1175#define SCTLR_ITD (1U << 7)
1176#define SCTLR_S (1U << 8)
1177#define SCTLR_SED (1U << 8)
1178#define SCTLR_R (1U << 9)
1179#define SCTLR_UMA (1U << 9)
1180#define SCTLR_F (1U << 10)
1181#define SCTLR_SW (1U << 10)
1182#define SCTLR_EnRCTX (1U << 10)
1183#define SCTLR_Z (1U << 11)
1184#define SCTLR_EOS (1U << 11)
1185#define SCTLR_I (1U << 12)
1186#define SCTLR_V (1U << 13)
1187#define SCTLR_EnDB (1U << 13)
1188#define SCTLR_RR (1U << 14)
1189#define SCTLR_DZE (1U << 14)
1190#define SCTLR_L4 (1U << 15)
1191#define SCTLR_UCT (1U << 15)
1192#define SCTLR_DT (1U << 16)
1193#define SCTLR_nTWI (1U << 16)
1194#define SCTLR_HA (1U << 17)
1195#define SCTLR_BR (1U << 17)
1196#define SCTLR_IT (1U << 18)
1197#define SCTLR_nTWE (1U << 18)
1198#define SCTLR_WXN (1U << 19)
1199#define SCTLR_ST (1U << 20)
1200#define SCTLR_UWXN (1U << 20)
1201#define SCTLR_FI (1U << 21)
1202#define SCTLR_IESB (1U << 21)
1203#define SCTLR_U (1U << 22)
1204#define SCTLR_EIS (1U << 22)
1205#define SCTLR_XP (1U << 23)
1206#define SCTLR_SPAN (1U << 23)
1207#define SCTLR_VE (1U << 24)
1208#define SCTLR_E0E (1U << 24)
1209#define SCTLR_EE (1U << 25)
1210#define SCTLR_L2 (1U << 26)
1211#define SCTLR_UCI (1U << 26)
1212#define SCTLR_NMFI (1U << 27)
1213#define SCTLR_EnDA (1U << 27)
1214#define SCTLR_TRE (1U << 28)
1215#define SCTLR_nTLSMD_64 (1U << 28)
1216#define SCTLR_AFE (1U << 29)
1217#define SCTLR_LSMAOE_64 (1U << 29)
1218#define SCTLR_TE (1U << 30)
1219#define SCTLR_EnIB (1U << 30)
1220#define SCTLR_EnIA (1U << 31)
1221#define SCTLR_DSSBS_32 (1U << 31)
1222#define SCTLR_BT0 (1ULL << 35)
1223#define SCTLR_BT1 (1ULL << 36)
1224#define SCTLR_ITFSB (1ULL << 37)
1225#define SCTLR_TCF0 (3ULL << 38)
1226#define SCTLR_TCF (3ULL << 40)
1227#define SCTLR_ATA0 (1ULL << 42)
1228#define SCTLR_ATA (1ULL << 43)
1229#define SCTLR_DSSBS_64 (1ULL << 44)
1230
1231#define CPTR_TCPAC (1U << 31)
1232#define CPTR_TTA (1U << 20)
1233#define CPTR_TFP (1U << 10)
1234#define CPTR_TZ (1U << 8)
1235#define CPTR_EZ (1U << 8)
1236
1237#define MDCR_EPMAD (1U << 21)
1238#define MDCR_EDAD (1U << 20)
1239#define MDCR_SPME (1U << 17)
1240#define MDCR_HPMD (1U << 17)
1241#define MDCR_SDD (1U << 16)
1242#define MDCR_SPD (3U << 14)
1243#define MDCR_TDRA (1U << 11)
1244#define MDCR_TDOSA (1U << 10)
1245#define MDCR_TDA (1U << 9)
1246#define MDCR_TDE (1U << 8)
1247#define MDCR_HPME (1U << 7)
1248#define MDCR_TPM (1U << 6)
1249#define MDCR_TPMCR (1U << 5)
1250#define MDCR_HPMN (0x1fU)
1251
1252
1253#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1254
1255#define CPSR_M (0x1fU)
1256#define CPSR_T (1U << 5)
1257#define CPSR_F (1U << 6)
1258#define CPSR_I (1U << 7)
1259#define CPSR_A (1U << 8)
1260#define CPSR_E (1U << 9)
1261#define CPSR_IT_2_7 (0xfc00U)
1262#define CPSR_GE (0xfU << 16)
1263#define CPSR_IL (1U << 20)
1264#define CPSR_DIT (1U << 21)
1265#define CPSR_PAN (1U << 22)
1266#define CPSR_SSBS (1U << 23)
1267#define CPSR_J (1U << 24)
1268#define CPSR_IT_0_1 (3U << 25)
1269#define CPSR_Q (1U << 27)
1270#define CPSR_V (1U << 28)
1271#define CPSR_C (1U << 29)
1272#define CPSR_Z (1U << 30)
1273#define CPSR_N (1U << 31)
1274#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1275#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1276
1277#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1278#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1279 | CPSR_NZCV)
1280
1281#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1282
1283#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1284
1285
1286#define XPSR_EXCP 0x1ffU
1287#define XPSR_SPREALIGN (1U << 9)
1288#define XPSR_IT_2_7 CPSR_IT_2_7
1289#define XPSR_GE CPSR_GE
1290#define XPSR_SFPA (1U << 20)
1291#define XPSR_T (1U << 24)
1292#define XPSR_IT_0_1 CPSR_IT_0_1
1293#define XPSR_Q CPSR_Q
1294#define XPSR_V CPSR_V
1295#define XPSR_C CPSR_C
1296#define XPSR_Z CPSR_Z
1297#define XPSR_N CPSR_N
1298#define XPSR_NZCV CPSR_NZCV
1299#define XPSR_IT CPSR_IT
1300
1301#define TTBCR_N (7U << 0)
1302#define TTBCR_T0SZ (7U << 0)
1303#define TTBCR_PD0 (1U << 4)
1304#define TTBCR_PD1 (1U << 5)
1305#define TTBCR_EPD0 (1U << 7)
1306#define TTBCR_IRGN0 (3U << 8)
1307#define TTBCR_ORGN0 (3U << 10)
1308#define TTBCR_SH0 (3U << 12)
1309#define TTBCR_T1SZ (3U << 16)
1310#define TTBCR_A1 (1U << 22)
1311#define TTBCR_EPD1 (1U << 23)
1312#define TTBCR_IRGN1 (3U << 24)
1313#define TTBCR_ORGN1 (3U << 26)
1314#define TTBCR_SH1 (1U << 28)
1315#define TTBCR_EAE (1U << 31)
1316
1317
1318
1319
1320
1321#define PSTATE_SP (1U)
1322#define PSTATE_M (0xFU)
1323#define PSTATE_nRW (1U << 4)
1324#define PSTATE_F (1U << 6)
1325#define PSTATE_I (1U << 7)
1326#define PSTATE_A (1U << 8)
1327#define PSTATE_D (1U << 9)
1328#define PSTATE_BTYPE (3U << 10)
1329#define PSTATE_SSBS (1U << 12)
1330#define PSTATE_IL (1U << 20)
1331#define PSTATE_SS (1U << 21)
1332#define PSTATE_PAN (1U << 22)
1333#define PSTATE_UAO (1U << 23)
1334#define PSTATE_DIT (1U << 24)
1335#define PSTATE_TCO (1U << 25)
1336#define PSTATE_V (1U << 28)
1337#define PSTATE_C (1U << 29)
1338#define PSTATE_Z (1U << 30)
1339#define PSTATE_N (1U << 31)
1340#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1341#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1342#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1343
1344#define PSTATE_MODE_EL3h 13
1345#define PSTATE_MODE_EL3t 12
1346#define PSTATE_MODE_EL2h 9
1347#define PSTATE_MODE_EL2t 8
1348#define PSTATE_MODE_EL1h 5
1349#define PSTATE_MODE_EL1t 4
1350#define PSTATE_MODE_EL0t 0
1351
1352
1353
1354
1355void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1356
1357
1358static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1359{
1360 return (el << 2) | handler;
1361}
1362
1363
1364
1365
1366
1367static inline uint32_t pstate_read(CPUARMState *env)
1368{
1369 int ZF;
1370
1371 ZF = (env->ZF == 0);
1372 return (env->NF & 0x80000000) | (ZF << 30)
1373 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1374 | env->pstate | env->daif | (env->btype << 10);
1375}
1376
1377static inline void pstate_write(CPUARMState *env, uint32_t val)
1378{
1379 env->ZF = (~val) & PSTATE_Z;
1380 env->NF = val;
1381 env->CF = (val >> 29) & 1;
1382 env->VF = (val << 3) & 0x80000000;
1383 env->daif = val & PSTATE_DAIF;
1384 env->btype = (val >> 10) & 3;
1385 env->pstate = val & ~CACHED_PSTATE_BITS;
1386}
1387
1388
1389uint32_t cpsr_read(CPUARMState *env);
1390
1391typedef enum CPSRWriteType {
1392 CPSRWriteByInstr = 0,
1393 CPSRWriteExceptionReturn = 1,
1394 CPSRWriteRaw = 2,
1395
1396 CPSRWriteByGDBStub = 3,
1397} CPSRWriteType;
1398
1399
1400
1401
1402
1403
1404
1405void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1406 CPSRWriteType write_type);
1407
1408
1409static inline uint32_t xpsr_read(CPUARMState *env)
1410{
1411 int ZF;
1412 ZF = (env->ZF == 0);
1413 return (env->NF & 0x80000000) | (ZF << 30)
1414 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1415 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1416 | ((env->condexec_bits & 0xfc) << 8)
1417 | (env->GE << 16)
1418 | env->v7m.exception;
1419}
1420
1421
1422static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1423{
1424 if (mask & XPSR_NZCV) {
1425 env->ZF = (~val) & XPSR_Z;
1426 env->NF = val;
1427 env->CF = (val >> 29) & 1;
1428 env->VF = (val << 3) & 0x80000000;
1429 }
1430 if (mask & XPSR_Q) {
1431 env->QF = ((val & XPSR_Q) != 0);
1432 }
1433 if (mask & XPSR_GE) {
1434 env->GE = (val & XPSR_GE) >> 16;
1435 }
1436#ifndef CONFIG_USER_ONLY
1437 if (mask & XPSR_T) {
1438 env->thumb = ((val & XPSR_T) != 0);
1439 }
1440 if (mask & XPSR_IT_0_1) {
1441 env->condexec_bits &= ~3;
1442 env->condexec_bits |= (val >> 25) & 3;
1443 }
1444 if (mask & XPSR_IT_2_7) {
1445 env->condexec_bits &= 3;
1446 env->condexec_bits |= (val >> 8) & 0xfc;
1447 }
1448 if (mask & XPSR_EXCP) {
1449
1450 write_v7m_exception(env, val & XPSR_EXCP);
1451 }
1452#endif
1453}
1454
1455#define HCR_VM (1ULL << 0)
1456#define HCR_SWIO (1ULL << 1)
1457#define HCR_PTW (1ULL << 2)
1458#define HCR_FMO (1ULL << 3)
1459#define HCR_IMO (1ULL << 4)
1460#define HCR_AMO (1ULL << 5)
1461#define HCR_VF (1ULL << 6)
1462#define HCR_VI (1ULL << 7)
1463#define HCR_VSE (1ULL << 8)
1464#define HCR_FB (1ULL << 9)
1465#define HCR_BSU_MASK (3ULL << 10)
1466#define HCR_DC (1ULL << 12)
1467#define HCR_TWI (1ULL << 13)
1468#define HCR_TWE (1ULL << 14)
1469#define HCR_TID0 (1ULL << 15)
1470#define HCR_TID1 (1ULL << 16)
1471#define HCR_TID2 (1ULL << 17)
1472#define HCR_TID3 (1ULL << 18)
1473#define HCR_TSC (1ULL << 19)
1474#define HCR_TIDCP (1ULL << 20)
1475#define HCR_TACR (1ULL << 21)
1476#define HCR_TSW (1ULL << 22)
1477#define HCR_TPCP (1ULL << 23)
1478#define HCR_TPU (1ULL << 24)
1479#define HCR_TTLB (1ULL << 25)
1480#define HCR_TVM (1ULL << 26)
1481#define HCR_TGE (1ULL << 27)
1482#define HCR_TDZ (1ULL << 28)
1483#define HCR_HCD (1ULL << 29)
1484#define HCR_TRVM (1ULL << 30)
1485#define HCR_RW (1ULL << 31)
1486#define HCR_CD (1ULL << 32)
1487#define HCR_ID (1ULL << 33)
1488#define HCR_E2H (1ULL << 34)
1489#define HCR_TLOR (1ULL << 35)
1490#define HCR_TERR (1ULL << 36)
1491#define HCR_TEA (1ULL << 37)
1492#define HCR_MIOCNCE (1ULL << 38)
1493
1494#define HCR_APK (1ULL << 40)
1495#define HCR_API (1ULL << 41)
1496#define HCR_NV (1ULL << 42)
1497#define HCR_NV1 (1ULL << 43)
1498#define HCR_AT (1ULL << 44)
1499#define HCR_NV2 (1ULL << 45)
1500#define HCR_FWB (1ULL << 46)
1501#define HCR_FIEN (1ULL << 47)
1502
1503#define HCR_TID4 (1ULL << 49)
1504#define HCR_TICAB (1ULL << 50)
1505#define HCR_AMVOFFEN (1ULL << 51)
1506#define HCR_TOCU (1ULL << 52)
1507#define HCR_ENSCXT (1ULL << 53)
1508#define HCR_TTLBIS (1ULL << 54)
1509#define HCR_TTLBOS (1ULL << 55)
1510#define HCR_ATA (1ULL << 56)
1511#define HCR_DCT (1ULL << 57)
1512#define HCR_TID5 (1ULL << 58)
1513#define HCR_TWEDEN (1ULL << 59)
1514#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1515
1516#define HPFAR_NS (1ULL << 63)
1517
1518#define SCR_NS (1U << 0)
1519#define SCR_IRQ (1U << 1)
1520#define SCR_FIQ (1U << 2)
1521#define SCR_EA (1U << 3)
1522#define SCR_FW (1U << 4)
1523#define SCR_AW (1U << 5)
1524#define SCR_NET (1U << 6)
1525#define SCR_SMD (1U << 7)
1526#define SCR_HCE (1U << 8)
1527#define SCR_SIF (1U << 9)
1528#define SCR_RW (1U << 10)
1529#define SCR_ST (1U << 11)
1530#define SCR_TWI (1U << 12)
1531#define SCR_TWE (1U << 13)
1532#define SCR_TLOR (1U << 14)
1533#define SCR_TERR (1U << 15)
1534#define SCR_APK (1U << 16)
1535#define SCR_API (1U << 17)
1536#define SCR_EEL2 (1U << 18)
1537#define SCR_EASE (1U << 19)
1538#define SCR_NMEA (1U << 20)
1539#define SCR_FIEN (1U << 21)
1540#define SCR_ENSCXT (1U << 25)
1541#define SCR_ATA (1U << 26)
1542
1543#define HSTR_TTEE (1 << 16)
1544#define HSTR_TJDBX (1 << 17)
1545
1546
1547uint32_t vfp_get_fpscr(CPUARMState *env);
1548void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1549
1550
1551
1552
1553
1554
1555
1556
1557#define FPSR_MASK 0xf800009f
1558#define FPCR_MASK 0x07ff9f00
1559
1560#define FPCR_IOE (1 << 8)
1561#define FPCR_DZE (1 << 9)
1562#define FPCR_OFE (1 << 10)
1563#define FPCR_UFE (1 << 11)
1564#define FPCR_IXE (1 << 12)
1565#define FPCR_IDE (1 << 15)
1566#define FPCR_FZ16 (1 << 19)
1567#define FPCR_RMODE_MASK (3 << 22)
1568#define FPCR_FZ (1 << 24)
1569#define FPCR_DN (1 << 25)
1570#define FPCR_AHP (1 << 26)
1571#define FPCR_QC (1 << 27)
1572#define FPCR_V (1 << 28)
1573#define FPCR_C (1 << 29)
1574#define FPCR_Z (1 << 30)
1575#define FPCR_N (1 << 31)
1576
1577#define FPCR_LTPSIZE_SHIFT 16
1578#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1579#define FPCR_LTPSIZE_LENGTH 3
1580
1581#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1582#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1583
1584static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1585{
1586 return vfp_get_fpscr(env) & FPSR_MASK;
1587}
1588
1589static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1590{
1591 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1592 vfp_set_fpscr(env, new_fpscr);
1593}
1594
1595static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1596{
1597 return vfp_get_fpscr(env) & FPCR_MASK;
1598}
1599
1600static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1601{
1602 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1603 vfp_set_fpscr(env, new_fpscr);
1604}
1605
1606enum arm_cpu_mode {
1607 ARM_CPU_MODE_USR = 0x10,
1608 ARM_CPU_MODE_FIQ = 0x11,
1609 ARM_CPU_MODE_IRQ = 0x12,
1610 ARM_CPU_MODE_SVC = 0x13,
1611 ARM_CPU_MODE_MON = 0x16,
1612 ARM_CPU_MODE_ABT = 0x17,
1613 ARM_CPU_MODE_HYP = 0x1a,
1614 ARM_CPU_MODE_UND = 0x1b,
1615 ARM_CPU_MODE_SYS = 0x1f
1616};
1617
1618
1619#define ARM_VFP_FPSID 0
1620#define ARM_VFP_FPSCR 1
1621#define ARM_VFP_MVFR2 5
1622#define ARM_VFP_MVFR1 6
1623#define ARM_VFP_MVFR0 7
1624#define ARM_VFP_FPEXC 8
1625#define ARM_VFP_FPINST 9
1626#define ARM_VFP_FPINST2 10
1627
1628#define ARM_VFP_FPSCR_NZCVQC 2
1629#define ARM_VFP_VPR 12
1630#define ARM_VFP_P0 13
1631#define ARM_VFP_FPCXT_NS 14
1632#define ARM_VFP_FPCXT_S 15
1633
1634
1635#define QEMU_VFP_FPSCR_NZCV 0xffff
1636
1637
1638#define ARM_IWMMXT_wCID 0
1639#define ARM_IWMMXT_wCon 1
1640#define ARM_IWMMXT_wCSSF 2
1641#define ARM_IWMMXT_wCASF 3
1642#define ARM_IWMMXT_wCGR0 8
1643#define ARM_IWMMXT_wCGR1 9
1644#define ARM_IWMMXT_wCGR2 10
1645#define ARM_IWMMXT_wCGR3 11
1646
1647
1648FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1649FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1650FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1651FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1652FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1653FIELD(V7M_CCR, STKALIGN, 9, 1)
1654FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1655FIELD(V7M_CCR, DC, 16, 1)
1656FIELD(V7M_CCR, IC, 17, 1)
1657FIELD(V7M_CCR, BP, 18, 1)
1658FIELD(V7M_CCR, LOB, 19, 1)
1659FIELD(V7M_CCR, TRD, 20, 1)
1660
1661
1662FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1663FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1664FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1665FIELD(V7M_SCR, SEVONPEND, 4, 1)
1666
1667
1668FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1669FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1670FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1671FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1672FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1673FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1674FIELD(V7M_AIRCR, PRIS, 14, 1)
1675FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1676FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1677
1678
1679FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1680FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1681FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1682FIELD(V7M_CFSR, MSTKERR, 4, 1)
1683FIELD(V7M_CFSR, MLSPERR, 5, 1)
1684FIELD(V7M_CFSR, MMARVALID, 7, 1)
1685
1686
1687FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1688FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1689FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1690FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1691FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1692FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1693FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1694
1695
1696FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1697FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1698FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1699FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1700FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1701FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1702FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1703
1704
1705FIELD(V7M_CFSR, MMFSR, 0, 8)
1706FIELD(V7M_CFSR, BFSR, 8, 8)
1707FIELD(V7M_CFSR, UFSR, 16, 16)
1708
1709
1710FIELD(V7M_HFSR, VECTTBL, 1, 1)
1711FIELD(V7M_HFSR, FORCED, 30, 1)
1712FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1713
1714
1715FIELD(V7M_DFSR, HALTED, 0, 1)
1716FIELD(V7M_DFSR, BKPT, 1, 1)
1717FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1718FIELD(V7M_DFSR, VCATCH, 3, 1)
1719FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1720
1721
1722FIELD(V7M_SFSR, INVEP, 0, 1)
1723FIELD(V7M_SFSR, INVIS, 1, 1)
1724FIELD(V7M_SFSR, INVER, 2, 1)
1725FIELD(V7M_SFSR, AUVIOL, 3, 1)
1726FIELD(V7M_SFSR, INVTRAN, 4, 1)
1727FIELD(V7M_SFSR, LSPERR, 5, 1)
1728FIELD(V7M_SFSR, SFARVALID, 6, 1)
1729FIELD(V7M_SFSR, LSERR, 7, 1)
1730
1731
1732FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1733FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1734FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1735
1736
1737FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1738FIELD(V7M_CLIDR, LOUIS, 21, 3)
1739FIELD(V7M_CLIDR, LOC, 24, 3)
1740FIELD(V7M_CLIDR, LOUU, 27, 3)
1741FIELD(V7M_CLIDR, ICB, 30, 2)
1742
1743FIELD(V7M_CSSELR, IND, 0, 1)
1744FIELD(V7M_CSSELR, LEVEL, 1, 3)
1745
1746
1747
1748
1749FIELD(V7M_CSSELR, INDEX, 0, 4)
1750
1751
1752FIELD(V7M_FPCCR, LSPACT, 0, 1)
1753FIELD(V7M_FPCCR, USER, 1, 1)
1754FIELD(V7M_FPCCR, S, 2, 1)
1755FIELD(V7M_FPCCR, THREAD, 3, 1)
1756FIELD(V7M_FPCCR, HFRDY, 4, 1)
1757FIELD(V7M_FPCCR, MMRDY, 5, 1)
1758FIELD(V7M_FPCCR, BFRDY, 6, 1)
1759FIELD(V7M_FPCCR, SFRDY, 7, 1)
1760FIELD(V7M_FPCCR, MONRDY, 8, 1)
1761FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1762FIELD(V7M_FPCCR, UFRDY, 10, 1)
1763FIELD(V7M_FPCCR, RES0, 11, 15)
1764FIELD(V7M_FPCCR, TS, 26, 1)
1765FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1766FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1767FIELD(V7M_FPCCR, LSPENS, 29, 1)
1768FIELD(V7M_FPCCR, LSPEN, 30, 1)
1769FIELD(V7M_FPCCR, ASPEN, 31, 1)
1770
1771#define R_V7M_FPCCR_BANKED_MASK \
1772 (R_V7M_FPCCR_LSPACT_MASK | \
1773 R_V7M_FPCCR_USER_MASK | \
1774 R_V7M_FPCCR_THREAD_MASK | \
1775 R_V7M_FPCCR_MMRDY_MASK | \
1776 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1777 R_V7M_FPCCR_UFRDY_MASK | \
1778 R_V7M_FPCCR_ASPEN_MASK)
1779
1780
1781FIELD(V7M_VPR, P0, 0, 16)
1782FIELD(V7M_VPR, MASK01, 16, 4)
1783FIELD(V7M_VPR, MASK23, 20, 4)
1784
1785
1786
1787
1788FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1789FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1790FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1791FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1792FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1793FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1794FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1795FIELD(CLIDR_EL1, LOUIS, 21, 3)
1796FIELD(CLIDR_EL1, LOC, 24, 3)
1797FIELD(CLIDR_EL1, LOUU, 27, 3)
1798FIELD(CLIDR_EL1, ICB, 30, 3)
1799
1800
1801FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1802FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1803FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1804
1805
1806FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1807FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1808FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1809
1810FIELD(CTR_EL0, IMINLINE, 0, 4)
1811FIELD(CTR_EL0, L1IP, 14, 2)
1812FIELD(CTR_EL0, DMINLINE, 16, 4)
1813FIELD(CTR_EL0, ERG, 20, 4)
1814FIELD(CTR_EL0, CWG, 24, 4)
1815FIELD(CTR_EL0, IDC, 28, 1)
1816FIELD(CTR_EL0, DIC, 29, 1)
1817FIELD(CTR_EL0, TMINLINE, 32, 6)
1818
1819FIELD(MIDR_EL1, REVISION, 0, 4)
1820FIELD(MIDR_EL1, PARTNUM, 4, 12)
1821FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1822FIELD(MIDR_EL1, VARIANT, 20, 4)
1823FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1824
1825FIELD(ID_ISAR0, SWAP, 0, 4)
1826FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1827FIELD(ID_ISAR0, BITFIELD, 8, 4)
1828FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1829FIELD(ID_ISAR0, COPROC, 16, 4)
1830FIELD(ID_ISAR0, DEBUG, 20, 4)
1831FIELD(ID_ISAR0, DIVIDE, 24, 4)
1832
1833FIELD(ID_ISAR1, ENDIAN, 0, 4)
1834FIELD(ID_ISAR1, EXCEPT, 4, 4)
1835FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1836FIELD(ID_ISAR1, EXTEND, 12, 4)
1837FIELD(ID_ISAR1, IFTHEN, 16, 4)
1838FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1839FIELD(ID_ISAR1, INTERWORK, 24, 4)
1840FIELD(ID_ISAR1, JAZELLE, 28, 4)
1841
1842FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1843FIELD(ID_ISAR2, MEMHINT, 4, 4)
1844FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1845FIELD(ID_ISAR2, MULT, 12, 4)
1846FIELD(ID_ISAR2, MULTS, 16, 4)
1847FIELD(ID_ISAR2, MULTU, 20, 4)
1848FIELD(ID_ISAR2, PSR_AR, 24, 4)
1849FIELD(ID_ISAR2, REVERSAL, 28, 4)
1850
1851FIELD(ID_ISAR3, SATURATE, 0, 4)
1852FIELD(ID_ISAR3, SIMD, 4, 4)
1853FIELD(ID_ISAR3, SVC, 8, 4)
1854FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1855FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1856FIELD(ID_ISAR3, T32COPY, 20, 4)
1857FIELD(ID_ISAR3, TRUENOP, 24, 4)
1858FIELD(ID_ISAR3, T32EE, 28, 4)
1859
1860FIELD(ID_ISAR4, UNPRIV, 0, 4)
1861FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1862FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1863FIELD(ID_ISAR4, SMC, 12, 4)
1864FIELD(ID_ISAR4, BARRIER, 16, 4)
1865FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1866FIELD(ID_ISAR4, PSR_M, 24, 4)
1867FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1868
1869FIELD(ID_ISAR5, SEVL, 0, 4)
1870FIELD(ID_ISAR5, AES, 4, 4)
1871FIELD(ID_ISAR5, SHA1, 8, 4)
1872FIELD(ID_ISAR5, SHA2, 12, 4)
1873FIELD(ID_ISAR5, CRC32, 16, 4)
1874FIELD(ID_ISAR5, RDM, 24, 4)
1875FIELD(ID_ISAR5, VCMA, 28, 4)
1876
1877FIELD(ID_ISAR6, JSCVT, 0, 4)
1878FIELD(ID_ISAR6, DP, 4, 4)
1879FIELD(ID_ISAR6, FHM, 8, 4)
1880FIELD(ID_ISAR6, SB, 12, 4)
1881FIELD(ID_ISAR6, SPECRES, 16, 4)
1882FIELD(ID_ISAR6, BF16, 20, 4)
1883FIELD(ID_ISAR6, I8MM, 24, 4)
1884
1885FIELD(ID_MMFR0, VMSA, 0, 4)
1886FIELD(ID_MMFR0, PMSA, 4, 4)
1887FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1888FIELD(ID_MMFR0, SHARELVL, 12, 4)
1889FIELD(ID_MMFR0, TCM, 16, 4)
1890FIELD(ID_MMFR0, AUXREG, 20, 4)
1891FIELD(ID_MMFR0, FCSE, 24, 4)
1892FIELD(ID_MMFR0, INNERSHR, 28, 4)
1893
1894FIELD(ID_MMFR1, L1HVDVA, 0, 4)
1895FIELD(ID_MMFR1, L1UNIVA, 4, 4)
1896FIELD(ID_MMFR1, L1HVDSW, 8, 4)
1897FIELD(ID_MMFR1, L1UNISW, 12, 4)
1898FIELD(ID_MMFR1, L1HVD, 16, 4)
1899FIELD(ID_MMFR1, L1UNI, 20, 4)
1900FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
1901FIELD(ID_MMFR1, BPRED, 28, 4)
1902
1903FIELD(ID_MMFR2, L1HVDFG, 0, 4)
1904FIELD(ID_MMFR2, L1HVDBG, 4, 4)
1905FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
1906FIELD(ID_MMFR2, HVDTLB, 12, 4)
1907FIELD(ID_MMFR2, UNITLB, 16, 4)
1908FIELD(ID_MMFR2, MEMBARR, 20, 4)
1909FIELD(ID_MMFR2, WFISTALL, 24, 4)
1910FIELD(ID_MMFR2, HWACCFLG, 28, 4)
1911
1912FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1913FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1914FIELD(ID_MMFR3, BPMAINT, 8, 4)
1915FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1916FIELD(ID_MMFR3, PAN, 16, 4)
1917FIELD(ID_MMFR3, COHWALK, 20, 4)
1918FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1919FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1920
1921FIELD(ID_MMFR4, SPECSEI, 0, 4)
1922FIELD(ID_MMFR4, AC2, 4, 4)
1923FIELD(ID_MMFR4, XNX, 8, 4)
1924FIELD(ID_MMFR4, CNP, 12, 4)
1925FIELD(ID_MMFR4, HPDS, 16, 4)
1926FIELD(ID_MMFR4, LSM, 20, 4)
1927FIELD(ID_MMFR4, CCIDX, 24, 4)
1928FIELD(ID_MMFR4, EVT, 28, 4)
1929
1930FIELD(ID_MMFR5, ETS, 0, 4)
1931
1932FIELD(ID_PFR0, STATE0, 0, 4)
1933FIELD(ID_PFR0, STATE1, 4, 4)
1934FIELD(ID_PFR0, STATE2, 8, 4)
1935FIELD(ID_PFR0, STATE3, 12, 4)
1936FIELD(ID_PFR0, CSV2, 16, 4)
1937FIELD(ID_PFR0, AMU, 20, 4)
1938FIELD(ID_PFR0, DIT, 24, 4)
1939FIELD(ID_PFR0, RAS, 28, 4)
1940
1941FIELD(ID_PFR1, PROGMOD, 0, 4)
1942FIELD(ID_PFR1, SECURITY, 4, 4)
1943FIELD(ID_PFR1, MPROGMOD, 8, 4)
1944FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1945FIELD(ID_PFR1, GENTIMER, 16, 4)
1946FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1947FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1948FIELD(ID_PFR1, GIC, 28, 4)
1949
1950FIELD(ID_PFR2, CSV3, 0, 4)
1951FIELD(ID_PFR2, SSBS, 4, 4)
1952FIELD(ID_PFR2, RAS_FRAC, 8, 4)
1953
1954FIELD(ID_AA64ISAR0, AES, 4, 4)
1955FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1956FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1957FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1958FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1959FIELD(ID_AA64ISAR0, RDM, 28, 4)
1960FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1961FIELD(ID_AA64ISAR0, SM3, 36, 4)
1962FIELD(ID_AA64ISAR0, SM4, 40, 4)
1963FIELD(ID_AA64ISAR0, DP, 44, 4)
1964FIELD(ID_AA64ISAR0, FHM, 48, 4)
1965FIELD(ID_AA64ISAR0, TS, 52, 4)
1966FIELD(ID_AA64ISAR0, TLB, 56, 4)
1967FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1968
1969FIELD(ID_AA64ISAR1, DPB, 0, 4)
1970FIELD(ID_AA64ISAR1, APA, 4, 4)
1971FIELD(ID_AA64ISAR1, API, 8, 4)
1972FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1973FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1974FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1975FIELD(ID_AA64ISAR1, GPA, 24, 4)
1976FIELD(ID_AA64ISAR1, GPI, 28, 4)
1977FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1978FIELD(ID_AA64ISAR1, SB, 36, 4)
1979FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1980FIELD(ID_AA64ISAR1, BF16, 44, 4)
1981FIELD(ID_AA64ISAR1, DGH, 48, 4)
1982FIELD(ID_AA64ISAR1, I8MM, 52, 4)
1983
1984FIELD(ID_AA64PFR0, EL0, 0, 4)
1985FIELD(ID_AA64PFR0, EL1, 4, 4)
1986FIELD(ID_AA64PFR0, EL2, 8, 4)
1987FIELD(ID_AA64PFR0, EL3, 12, 4)
1988FIELD(ID_AA64PFR0, FP, 16, 4)
1989FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1990FIELD(ID_AA64PFR0, GIC, 24, 4)
1991FIELD(ID_AA64PFR0, RAS, 28, 4)
1992FIELD(ID_AA64PFR0, SVE, 32, 4)
1993FIELD(ID_AA64PFR0, SEL2, 36, 4)
1994FIELD(ID_AA64PFR0, MPAM, 40, 4)
1995FIELD(ID_AA64PFR0, AMU, 44, 4)
1996FIELD(ID_AA64PFR0, DIT, 48, 4)
1997FIELD(ID_AA64PFR0, CSV2, 56, 4)
1998FIELD(ID_AA64PFR0, CSV3, 60, 4)
1999
2000FIELD(ID_AA64PFR1, BT, 0, 4)
2001FIELD(ID_AA64PFR1, SSBS, 4, 4)
2002FIELD(ID_AA64PFR1, MTE, 8, 4)
2003FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2004FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2005
2006FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2007FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2008FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2009FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2010FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2011FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2012FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2013FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2014FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2015FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2016FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2017FIELD(ID_AA64MMFR0, EXS, 44, 4)
2018FIELD(ID_AA64MMFR0, FGT, 56, 4)
2019FIELD(ID_AA64MMFR0, ECV, 60, 4)
2020
2021FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2022FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2023FIELD(ID_AA64MMFR1, VH, 8, 4)
2024FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2025FIELD(ID_AA64MMFR1, LO, 16, 4)
2026FIELD(ID_AA64MMFR1, PAN, 20, 4)
2027FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2028FIELD(ID_AA64MMFR1, XNX, 28, 4)
2029FIELD(ID_AA64MMFR1, TWED, 32, 4)
2030FIELD(ID_AA64MMFR1, ETS, 36, 4)
2031
2032FIELD(ID_AA64MMFR2, CNP, 0, 4)
2033FIELD(ID_AA64MMFR2, UAO, 4, 4)
2034FIELD(ID_AA64MMFR2, LSM, 8, 4)
2035FIELD(ID_AA64MMFR2, IESB, 12, 4)
2036FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2037FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2038FIELD(ID_AA64MMFR2, NV, 24, 4)
2039FIELD(ID_AA64MMFR2, ST, 28, 4)
2040FIELD(ID_AA64MMFR2, AT, 32, 4)
2041FIELD(ID_AA64MMFR2, IDS, 36, 4)
2042FIELD(ID_AA64MMFR2, FWB, 40, 4)
2043FIELD(ID_AA64MMFR2, TTL, 48, 4)
2044FIELD(ID_AA64MMFR2, BBM, 52, 4)
2045FIELD(ID_AA64MMFR2, EVT, 56, 4)
2046FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2047
2048FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2049FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2050FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2051FIELD(ID_AA64DFR0, BRPS, 12, 4)
2052FIELD(ID_AA64DFR0, WRPS, 20, 4)
2053FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2054FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2055FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2056FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2057FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2058
2059FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2060FIELD(ID_AA64ZFR0, AES, 4, 4)
2061FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2062FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2063FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2064FIELD(ID_AA64ZFR0, SM4, 40, 4)
2065FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2066FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2067FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2068
2069FIELD(ID_DFR0, COPDBG, 0, 4)
2070FIELD(ID_DFR0, COPSDBG, 4, 4)
2071FIELD(ID_DFR0, MMAPDBG, 8, 4)
2072FIELD(ID_DFR0, COPTRC, 12, 4)
2073FIELD(ID_DFR0, MMAPTRC, 16, 4)
2074FIELD(ID_DFR0, MPROFDBG, 20, 4)
2075FIELD(ID_DFR0, PERFMON, 24, 4)
2076FIELD(ID_DFR0, TRACEFILT, 28, 4)
2077
2078FIELD(ID_DFR1, MTPMU, 0, 4)
2079
2080FIELD(DBGDIDR, SE_IMP, 12, 1)
2081FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2082FIELD(DBGDIDR, VERSION, 16, 4)
2083FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2084FIELD(DBGDIDR, BRPS, 24, 4)
2085FIELD(DBGDIDR, WRPS, 28, 4)
2086
2087FIELD(MVFR0, SIMDREG, 0, 4)
2088FIELD(MVFR0, FPSP, 4, 4)
2089FIELD(MVFR0, FPDP, 8, 4)
2090FIELD(MVFR0, FPTRAP, 12, 4)
2091FIELD(MVFR0, FPDIVIDE, 16, 4)
2092FIELD(MVFR0, FPSQRT, 20, 4)
2093FIELD(MVFR0, FPSHVEC, 24, 4)
2094FIELD(MVFR0, FPROUND, 28, 4)
2095
2096FIELD(MVFR1, FPFTZ, 0, 4)
2097FIELD(MVFR1, FPDNAN, 4, 4)
2098FIELD(MVFR1, SIMDLS, 8, 4)
2099FIELD(MVFR1, SIMDINT, 12, 4)
2100FIELD(MVFR1, SIMDSP, 16, 4)
2101FIELD(MVFR1, SIMDHP, 20, 4)
2102FIELD(MVFR1, MVE, 8, 4)
2103FIELD(MVFR1, FP16, 20, 4)
2104FIELD(MVFR1, FPHP, 24, 4)
2105FIELD(MVFR1, SIMDFMAC, 28, 4)
2106
2107FIELD(MVFR2, SIMDMISC, 0, 4)
2108FIELD(MVFR2, FPMISC, 4, 4)
2109
2110QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2111
2112
2113
2114
2115
2116enum arm_features {
2117 ARM_FEATURE_AUXCR,
2118 ARM_FEATURE_XSCALE,
2119 ARM_FEATURE_IWMMXT,
2120 ARM_FEATURE_V6,
2121 ARM_FEATURE_V6K,
2122 ARM_FEATURE_V7,
2123 ARM_FEATURE_THUMB2,
2124 ARM_FEATURE_PMSA,
2125 ARM_FEATURE_NEON,
2126 ARM_FEATURE_M,
2127 ARM_FEATURE_OMAPCP,
2128 ARM_FEATURE_THUMB2EE,
2129 ARM_FEATURE_V7MP,
2130 ARM_FEATURE_V7VE,
2131 ARM_FEATURE_V4T,
2132 ARM_FEATURE_V5,
2133 ARM_FEATURE_STRONGARM,
2134 ARM_FEATURE_VAPA,
2135 ARM_FEATURE_GENERIC_TIMER,
2136 ARM_FEATURE_MVFR,
2137 ARM_FEATURE_DUMMY_C15_REGS,
2138 ARM_FEATURE_CACHE_TEST_CLEAN,
2139 ARM_FEATURE_CACHE_DIRTY_REG,
2140 ARM_FEATURE_CACHE_BLOCK_OPS,
2141 ARM_FEATURE_MPIDR,
2142 ARM_FEATURE_LPAE,
2143 ARM_FEATURE_V8,
2144 ARM_FEATURE_AARCH64,
2145 ARM_FEATURE_CBAR,
2146 ARM_FEATURE_CBAR_RO,
2147 ARM_FEATURE_EL2,
2148 ARM_FEATURE_EL3,
2149 ARM_FEATURE_THUMB_DSP,
2150 ARM_FEATURE_PMU,
2151 ARM_FEATURE_VBAR,
2152 ARM_FEATURE_M_SECURITY,
2153 ARM_FEATURE_M_MAIN,
2154 ARM_FEATURE_V8_1M,
2155};
2156
2157static inline int arm_feature(CPUARMState *env, int feature)
2158{
2159 return (env->features & (1ULL << feature)) != 0;
2160}
2161
2162void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2163
2164#if !defined(CONFIG_USER_ONLY)
2165
2166
2167
2168
2169
2170
2171static inline bool arm_is_secure_below_el3(CPUARMState *env)
2172{
2173 if (arm_feature(env, ARM_FEATURE_EL3)) {
2174 return !(env->cp15.scr_el3 & SCR_NS);
2175 } else {
2176
2177
2178
2179 return false;
2180 }
2181}
2182
2183
2184static inline bool arm_is_el3_or_mon(CPUARMState *env)
2185{
2186 if (arm_feature(env, ARM_FEATURE_EL3)) {
2187 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2188
2189 return true;
2190 } else if (!is_a64(env) &&
2191 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2192
2193 return true;
2194 }
2195 }
2196 return false;
2197}
2198
2199
2200static inline bool arm_is_secure(CPUARMState *env)
2201{
2202 if (arm_is_el3_or_mon(env)) {
2203 return true;
2204 }
2205 return arm_is_secure_below_el3(env);
2206}
2207
2208
2209
2210
2211
2212static inline bool arm_is_el2_enabled(CPUARMState *env)
2213{
2214 if (arm_feature(env, ARM_FEATURE_EL2)) {
2215 if (arm_is_secure_below_el3(env)) {
2216 return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2217 }
2218 return true;
2219 }
2220 return false;
2221}
2222
2223#else
2224static inline bool arm_is_secure_below_el3(CPUARMState *env)
2225{
2226 return false;
2227}
2228
2229static inline bool arm_is_secure(CPUARMState *env)
2230{
2231 return false;
2232}
2233
2234static inline bool arm_is_el2_enabled(CPUARMState *env)
2235{
2236 return false;
2237}
2238#endif
2239
2240
2241
2242
2243
2244
2245
2246uint64_t arm_hcr_el2_eff(CPUARMState *env);
2247
2248
2249static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2250{
2251
2252
2253
2254 assert(el >= 1 && el <= 3);
2255 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2256
2257
2258
2259
2260
2261 if (el == 3) {
2262 return aa64;
2263 }
2264
2265 if (arm_feature(env, ARM_FEATURE_EL3) &&
2266 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2267 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2268 }
2269
2270 if (el == 2) {
2271 return aa64;
2272 }
2273
2274 if (arm_is_el2_enabled(env)) {
2275 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2276 }
2277
2278 return aa64;
2279}
2280
2281
2282
2283
2284
2285
2286
2287
2288static inline bool access_secure_reg(CPUARMState *env)
2289{
2290 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2291 !arm_el_is_aa64(env, 3) &&
2292 !(env->cp15.scr_el3 & SCR_NS));
2293
2294 return ret;
2295}
2296
2297
2298#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2299 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2300
2301#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2302 do { \
2303 if (_secure) { \
2304 (_env)->cp15._regname##_s = (_val); \
2305 } else { \
2306 (_env)->cp15._regname##_ns = (_val); \
2307 } \
2308 } while (0)
2309
2310
2311
2312
2313
2314
2315#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2316 A32_BANKED_REG_GET((_env), _regname, \
2317 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2318
2319#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2320 A32_BANKED_REG_SET((_env), _regname, \
2321 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2322 (_val))
2323
2324void arm_cpu_list(void);
2325uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2326 uint32_t cur_el, bool secure);
2327
2328
2329#ifndef CONFIG_USER_ONLY
2330bool armv7m_nvic_can_take_pending_exception(void *opaque);
2331#else
2332static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2333{
2334 return true;
2335}
2336#endif
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2389 bool *ptargets_secure);
2390
2391
2392
2393
2394
2395
2396
2397
2398void armv7m_nvic_acknowledge_irq(void *opaque);
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434int armv7m_nvic_raw_execution_priority(void *opaque);
2435
2436
2437
2438
2439
2440
2441
2442#ifndef CONFIG_USER_ONLY
2443bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2444#else
2445static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2446{
2447 return false;
2448}
2449#endif
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477#define CP_REG_AA64_SHIFT 28
2478#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2479
2480
2481
2482
2483
2484#define CP_REG_NS_SHIFT 29
2485#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2486
2487#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2488 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2489 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2490
2491#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2492 (CP_REG_AA64_MASK | \
2493 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2494 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2495 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2496 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2497 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2498 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2499
2500
2501
2502
2503static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2504{
2505 uint32_t cpregid = kvmid;
2506 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2507 cpregid |= CP_REG_AA64_MASK;
2508 } else {
2509 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2510 cpregid |= (1 << 15);
2511 }
2512
2513
2514
2515
2516 cpregid |= 1 << CP_REG_NS_SHIFT;
2517 }
2518 return cpregid;
2519}
2520
2521
2522
2523
2524static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2525{
2526 uint64_t kvmid;
2527
2528 if (cpregid & CP_REG_AA64_MASK) {
2529 kvmid = cpregid & ~CP_REG_AA64_MASK;
2530 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2531 } else {
2532 kvmid = cpregid & ~(1 << 15);
2533 if (cpregid & (1 << 15)) {
2534 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2535 } else {
2536 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2537 }
2538 }
2539 return kvmid;
2540}
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570#define ARM_CP_SPECIAL 0x0001
2571#define ARM_CP_CONST 0x0002
2572#define ARM_CP_64BIT 0x0004
2573#define ARM_CP_SUPPRESS_TB_END 0x0008
2574#define ARM_CP_OVERRIDE 0x0010
2575#define ARM_CP_ALIAS 0x0020
2576#define ARM_CP_IO 0x0040
2577#define ARM_CP_NO_RAW 0x0080
2578#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2579#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2580#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2581#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2582#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2583#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2584#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2585#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2586#define ARM_CP_FPU 0x1000
2587#define ARM_CP_SVE 0x2000
2588#define ARM_CP_NO_GDB 0x4000
2589#define ARM_CP_RAISES_EXC 0x8000
2590#define ARM_CP_NEWEL 0x10000
2591
2592#define ARM_CP_SENTINEL 0xfffff
2593
2594#define ARM_CP_FLAG_MASK 0x1f0ff
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605enum {
2606 ARM_CP_STATE_AA32 = 0,
2607 ARM_CP_STATE_AA64 = 1,
2608 ARM_CP_STATE_BOTH = 2,
2609};
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621enum {
2622 ARM_CP_SECSTATE_S = (1 << 0),
2623 ARM_CP_SECSTATE_NS = (1 << 1),
2624};
2625
2626
2627
2628
2629
2630static inline bool cptype_valid(int cptype)
2631{
2632 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2633 || ((cptype & ARM_CP_SPECIAL) &&
2634 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2635}
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654#define PL3_R 0x80
2655#define PL3_W 0x40
2656#define PL2_R (0x20 | PL3_R)
2657#define PL2_W (0x10 | PL3_W)
2658#define PL1_R (0x08 | PL2_R)
2659#define PL1_W (0x04 | PL2_W)
2660#define PL0_R (0x02 | PL1_R)
2661#define PL0_W (0x01 | PL1_W)
2662
2663
2664
2665
2666
2667
2668
2669#ifdef CONFIG_USER_ONLY
2670#define PL0U_R PL0_R
2671#else
2672#define PL0U_R PL1_R
2673#endif
2674
2675#define PL3_RW (PL3_R | PL3_W)
2676#define PL2_RW (PL2_R | PL2_W)
2677#define PL1_RW (PL1_R | PL1_W)
2678#define PL0_RW (PL0_R | PL0_W)
2679
2680
2681static inline int arm_highest_el(CPUARMState *env)
2682{
2683 if (arm_feature(env, ARM_FEATURE_EL3)) {
2684 return 3;
2685 }
2686 if (arm_feature(env, ARM_FEATURE_EL2)) {
2687 return 2;
2688 }
2689 return 1;
2690}
2691
2692
2693static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2694{
2695 return env->v7m.exception != 0;
2696}
2697
2698
2699
2700
2701static inline int arm_current_el(CPUARMState *env)
2702{
2703 if (arm_feature(env, ARM_FEATURE_M)) {
2704 return arm_v7m_is_handler_mode(env) ||
2705 !(env->v7m.control[env->v7m.secure] & 1);
2706 }
2707
2708 if (is_a64(env)) {
2709 return extract32(env->pstate, 2, 2);
2710 }
2711
2712 switch (env->uncached_cpsr & 0x1f) {
2713 case ARM_CPU_MODE_USR:
2714 return 0;
2715 case ARM_CPU_MODE_HYP:
2716 return 2;
2717 case ARM_CPU_MODE_MON:
2718 return 3;
2719 default:
2720 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2721
2722
2723
2724 return 3;
2725 }
2726
2727 return 1;
2728 }
2729}
2730
2731typedef struct ARMCPRegInfo ARMCPRegInfo;
2732
2733typedef enum CPAccessResult {
2734
2735 CP_ACCESS_OK = 0,
2736
2737
2738
2739
2740
2741
2742 CP_ACCESS_TRAP = 1,
2743
2744
2745
2746
2747 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2748
2749 CP_ACCESS_TRAP_EL2 = 3,
2750 CP_ACCESS_TRAP_EL3 = 4,
2751
2752 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2753 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2754
2755
2756
2757 CP_ACCESS_TRAP_FP_EL2 = 7,
2758 CP_ACCESS_TRAP_FP_EL3 = 8,
2759} CPAccessResult;
2760
2761
2762
2763
2764typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2765typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2766 uint64_t value);
2767
2768typedef CPAccessResult CPAccessFn(CPUARMState *env,
2769 const ARMCPRegInfo *opaque,
2770 bool isread);
2771
2772typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2773
2774#define CP_ANY 0xff
2775
2776
2777struct ARMCPRegInfo {
2778
2779 const char *name;
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797 uint8_t cp;
2798 uint8_t crn;
2799 uint8_t crm;
2800 uint8_t opc0;
2801 uint8_t opc1;
2802 uint8_t opc2;
2803
2804 int state;
2805
2806 int type;
2807
2808 int access;
2809
2810 int secure;
2811
2812
2813
2814
2815 void *opaque;
2816
2817
2818
2819 uint64_t resetvalue;
2820
2821
2822
2823
2824
2825
2826 ptrdiff_t fieldoffset;
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839 ptrdiff_t bank_fieldoffsets[2];
2840
2841
2842
2843
2844
2845
2846 CPAccessFn *accessfn;
2847
2848
2849
2850
2851 CPReadFn *readfn;
2852
2853
2854
2855
2856 CPWriteFn *writefn;
2857
2858
2859
2860
2861
2862 CPReadFn *raw_readfn;
2863
2864
2865
2866
2867
2868
2869 CPWriteFn *raw_writefn;
2870
2871
2872
2873
2874 CPResetFn *resetfn;
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886 CPReadFn *orig_readfn;
2887 CPWriteFn *orig_writefn;
2888};
2889
2890
2891
2892
2893#define CPREG_FIELD32(env, ri) \
2894 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2895#define CPREG_FIELD64(env, ri) \
2896 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2897
2898#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2899
2900void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2901 const ARMCPRegInfo *regs, void *opaque);
2902void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2903 const ARMCPRegInfo *regs, void *opaque);
2904static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2905{
2906 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2907}
2908static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2909{
2910 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2911}
2912const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2913
2914
2915
2916
2917
2918
2919
2920typedef struct ARMCPRegUserSpaceInfo {
2921
2922 const char *name;
2923
2924
2925 bool is_glob;
2926
2927
2928 uint64_t exported_bits;
2929
2930
2931 uint64_t fixed_bits;
2932} ARMCPRegUserSpaceInfo;
2933
2934#define REGUSERINFO_SENTINEL { .name = NULL }
2935
2936void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2937
2938
2939void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2940 uint64_t value);
2941
2942uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2943
2944
2945
2946
2947void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2948
2949
2950
2951
2952static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2953{
2954 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2955}
2956
2957static inline bool cp_access_ok(int current_el,
2958 const ARMCPRegInfo *ri, int isread)
2959{
2960 return (ri->access >> ((current_el * 2) + isread)) & 1;
2961}
2962
2963
2964uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980bool write_list_to_cpustate(ARMCPU *cpu);
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
3004
3005#define ARM_CPUID_TI915T 0x54029152
3006#define ARM_CPUID_TI925T 0x54029252
3007
3008#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
3009#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
3010#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
3011
3012#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
3013
3014#define cpu_list arm_cpu_list
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110#define ARM_MMU_IDX_A 0x10
3111#define ARM_MMU_IDX_NOTLB 0x20
3112#define ARM_MMU_IDX_M 0x40
3113
3114
3115#define ARM_MMU_IDX_A_NS 0x8
3116
3117
3118#define ARM_MMU_IDX_M_PRIV 0x1
3119#define ARM_MMU_IDX_M_NEGPRI 0x2
3120#define ARM_MMU_IDX_M_S 0x4
3121
3122#define ARM_MMU_IDX_TYPE_MASK \
3123 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
3124#define ARM_MMU_IDX_COREIDX_MASK 0xf
3125
3126typedef enum ARMMMUIdx {
3127
3128
3129
3130 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A,
3131 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A,
3132 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A,
3133 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A,
3134 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A,
3135 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A,
3136 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A,
3137 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A,
3138
3139 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
3140 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
3141 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
3142 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
3143 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
3144 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
3145 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
3146
3147
3148
3149
3150
3151 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
3152 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
3153 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
3154 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
3155 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
3156 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
3157
3158
3159
3160
3161
3162
3163
3164 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB,
3165 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB,
3166
3167
3168
3169
3170 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3171 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3172 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3173 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3174 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3175 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3176 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3177 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3178} ARMMMUIdx;
3179
3180
3181
3182
3183
3184#define TO_CORE_BIT(NAME) \
3185 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3186
3187typedef enum ARMMMUIdxBit {
3188 TO_CORE_BIT(E10_0),
3189 TO_CORE_BIT(E20_0),
3190 TO_CORE_BIT(E10_1),
3191 TO_CORE_BIT(E10_1_PAN),
3192 TO_CORE_BIT(E2),
3193 TO_CORE_BIT(E20_2),
3194 TO_CORE_BIT(E20_2_PAN),
3195 TO_CORE_BIT(SE10_0),
3196 TO_CORE_BIT(SE20_0),
3197 TO_CORE_BIT(SE10_1),
3198 TO_CORE_BIT(SE20_2),
3199 TO_CORE_BIT(SE10_1_PAN),
3200 TO_CORE_BIT(SE20_2_PAN),
3201 TO_CORE_BIT(SE2),
3202 TO_CORE_BIT(SE3),
3203
3204 TO_CORE_BIT(MUser),
3205 TO_CORE_BIT(MPriv),
3206 TO_CORE_BIT(MUserNegPri),
3207 TO_CORE_BIT(MPrivNegPri),
3208 TO_CORE_BIT(MSUser),
3209 TO_CORE_BIT(MSPriv),
3210 TO_CORE_BIT(MSUserNegPri),
3211 TO_CORE_BIT(MSPrivNegPri),
3212} ARMMMUIdxBit;
3213
3214#undef TO_CORE_BIT
3215
3216#define MMU_USER_IDX 0
3217
3218
3219typedef enum ARMASIdx {
3220 ARMASIdx_NS = 0,
3221 ARMASIdx_S = 1,
3222 ARMASIdx_TagNS = 2,
3223 ARMASIdx_TagS = 3,
3224} ARMASIdx;
3225
3226
3227static inline int arm_debug_target_el(CPUARMState *env)
3228{
3229 bool secure = arm_is_secure(env);
3230 bool route_to_el2 = false;
3231
3232 if (arm_is_el2_enabled(env)) {
3233 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3234 env->cp15.mdcr_el2 & MDCR_TDE;
3235 }
3236
3237 if (route_to_el2) {
3238 return 2;
3239 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3240 !arm_el_is_aa64(env, 3) && secure) {
3241 return 3;
3242 } else {
3243 return 1;
3244 }
3245}
3246
3247static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3248{
3249
3250
3251
3252 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3253}
3254
3255
3256static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3257{
3258 int cur_el = arm_current_el(env);
3259 int debug_el;
3260
3261 if (cur_el == 3) {
3262 return false;
3263 }
3264
3265
3266 if (arm_is_secure_below_el3(env)
3267 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3268 return false;
3269 }
3270
3271
3272
3273
3274
3275 debug_el = arm_debug_target_el(env);
3276
3277 if (cur_el == debug_el) {
3278 return extract32(env->cp15.mdscr_el1, 13, 1)
3279 && !(env->daif & PSTATE_D);
3280 }
3281
3282
3283 return debug_el > cur_el;
3284}
3285
3286static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3287{
3288 int el = arm_current_el(env);
3289
3290 if (el == 0 && arm_el_is_aa64(env, 1)) {
3291 return aa64_generate_debug_exceptions(env);
3292 }
3293
3294 if (arm_is_secure(env)) {
3295 int spd;
3296
3297 if (el == 0 && (env->cp15.sder & 1)) {
3298
3299
3300
3301
3302 return true;
3303 }
3304
3305 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3306 switch (spd) {
3307 case 1:
3308
3309 case 0:
3310
3311
3312
3313
3314
3315 return true;
3316 case 2:
3317 return false;
3318 case 3:
3319 return true;
3320 }
3321 }
3322
3323 return el != 2;
3324}
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3338{
3339 if (env->aarch64) {
3340 return aa64_generate_debug_exceptions(env);
3341 } else {
3342 return aa32_generate_debug_exceptions(env);
3343 }
3344}
3345
3346
3347
3348
3349static inline bool arm_singlestep_active(CPUARMState *env)
3350{
3351 return extract32(env->cp15.mdscr_el1, 0, 1)
3352 && arm_el_is_aa64(env, arm_debug_target_el(env))
3353 && arm_generate_debug_exceptions(env);
3354}
3355
3356static inline bool arm_sctlr_b(CPUARMState *env)
3357{
3358 return
3359
3360
3361
3362
3363#ifndef CONFIG_USER_ONLY
3364 !arm_feature(env, ARM_FEATURE_V7) &&
3365#endif
3366 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3367}
3368
3369uint64_t arm_sctlr(CPUARMState *env, int el);
3370
3371static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3372 bool sctlr_b)
3373{
3374#ifdef CONFIG_USER_ONLY
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387 if (sctlr_b) {
3388 return true;
3389 }
3390#endif
3391
3392 return env->uncached_cpsr & CPSR_E;
3393}
3394
3395static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3396{
3397 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3398}
3399
3400
3401static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3402{
3403 if (!is_a64(env)) {
3404 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3405 } else {
3406 int cur_el = arm_current_el(env);
3407 uint64_t sctlr = arm_sctlr(env, cur_el);
3408 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3409 }
3410}
3411
3412typedef CPUARMState CPUArchState;
3413typedef ARMCPU ArchCPU;
3414
3415#include "exec/cpu-all.h"
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3442FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3443FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)
3444FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3445FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3446
3447FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3448
3449FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
3450
3451FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
3452FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1)
3453
3454
3455
3456
3457FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)
3458FIELD(TBFLAG_AM32, THUMB, 23, 1)
3459
3460
3461
3462
3463FIELD(TBFLAG_A32, VECLEN, 0, 3)
3464FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)
3465
3466
3467
3468
3469
3470
3471FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3472FIELD(TBFLAG_A32, VFPEN, 7, 1)
3473FIELD(TBFLAG_A32, SCTLR__B, 8, 1)
3474FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3475
3476
3477
3478
3479
3480FIELD(TBFLAG_A32, NS, 10, 1)
3481
3482
3483
3484
3485
3486FIELD(TBFLAG_M32, HANDLER, 0, 1)
3487
3488FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3489
3490FIELD(TBFLAG_M32, LSPACT, 2, 1)
3491
3492FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)
3493
3494FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)
3495
3496FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)
3497
3498
3499
3500
3501FIELD(TBFLAG_A64, TBII, 0, 2)
3502FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3503FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3504FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3505FIELD(TBFLAG_A64, BT, 9, 1)
3506FIELD(TBFLAG_A64, BTYPE, 10, 2)
3507FIELD(TBFLAG_A64, TBID, 12, 2)
3508FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3509FIELD(TBFLAG_A64, ATA, 15, 1)
3510FIELD(TBFLAG_A64, TCMA, 16, 2)
3511FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3512FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3513
3514
3515
3516
3517#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3518 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3519#define DP_TBFLAG_A64(DST, WHICH, VAL) \
3520 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3521#define DP_TBFLAG_A32(DST, WHICH, VAL) \
3522 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3523#define DP_TBFLAG_M32(DST, WHICH, VAL) \
3524 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3525#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3526 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3527
3528#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3529#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3530#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3531#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3532#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3543{
3544 return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3545}
3546
3547static inline bool bswap_code(bool sctlr_b)
3548{
3549#ifdef CONFIG_USER_ONLY
3550
3551
3552
3553
3554 return
3555#ifdef TARGET_WORDS_BIGENDIAN
3556 1 ^
3557#endif
3558 sctlr_b;
3559#else
3560
3561
3562
3563 return 0;
3564#endif
3565}
3566
3567#ifdef CONFIG_USER_ONLY
3568static inline bool arm_cpu_bswap_data(CPUARMState *env)
3569{
3570 return
3571#ifdef TARGET_WORDS_BIGENDIAN
3572 1 ^
3573#endif
3574 arm_cpu_data_is_big_endian(env);
3575}
3576#endif
3577
3578void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3579 target_ulong *cs_base, uint32_t *flags);
3580
3581enum {
3582 QEMU_PSCI_CONDUIT_DISABLED = 0,
3583 QEMU_PSCI_CONDUIT_SMC = 1,
3584 QEMU_PSCI_CONDUIT_HVC = 2,
3585};
3586
3587#ifndef CONFIG_USER_ONLY
3588
3589static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3590{
3591 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3592}
3593
3594
3595
3596
3597
3598static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3599{
3600 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3601}
3602#endif
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3615 void *opaque);
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3627 *opaque);
3628
3629
3630
3631
3632
3633void arm_rebuild_hflags(CPUARMState *env);
3634
3635
3636
3637
3638
3639static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3640{
3641 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3642}
3643
3644
3645
3646
3647
3648static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3649{
3650 return &env->vfp.zregs[regno].d[0];
3651}
3652
3653
3654
3655
3656
3657static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3658{
3659 return &env->vfp.zregs[regno].d[0];
3660}
3661
3662
3663extern const uint64_t pred_esz_masks[4];
3664
3665
3666static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3667{
3668 return x;
3669}
3670
3671
3672
3673
3674
3675
3676#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3677#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3678
3679
3680
3681
3682#define PAGE_BTI PAGE_TARGET_1
3683#define PAGE_MTE PAGE_TARGET_2
3684
3685#ifdef TARGET_TAGGED_ADDRESSES
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3698{
3699 ARMCPU *cpu = ARM_CPU(cs);
3700 if (cpu->env.tagged_addr_enable) {
3701
3702
3703
3704
3705 x &= sextract64(x, 0, 56);
3706 }
3707 return x;
3708}
3709#endif
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3731{
3732 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3733}
3734
3735static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3736{
3737 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3738}
3739
3740static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3741{
3742
3743 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3744}
3745
3746static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3747{
3748 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3749}
3750
3751static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3752{
3753 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3754}
3755
3756static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3757{
3758 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3759}
3760
3761static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3762{
3763 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3764}
3765
3766static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3767{
3768 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3769}
3770
3771static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3772{
3773 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3774}
3775
3776static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3777{
3778 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3779}
3780
3781static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3782{
3783 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3784}
3785
3786static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3787{
3788 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3789}
3790
3791static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3792{
3793 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3794}
3795
3796static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3797{
3798 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3799}
3800
3801static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3802{
3803 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3804}
3805
3806static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3807{
3808 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3809}
3810
3811static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3812{
3813 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3814}
3815
3816static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3817{
3818 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3819}
3820
3821static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3822{
3823 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3824}
3825
3826static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3827{
3828 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3829}
3830
3831static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3832{
3833
3834
3835
3836
3837 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3838}
3839
3840static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3841{
3842
3843 if (isar_feature_aa32_mprofile(id)) {
3844 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3845 } else {
3846 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3847 }
3848}
3849
3850static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3851{
3852
3853
3854
3855
3856
3857 return isar_feature_aa32_mprofile(id) &&
3858 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3859}
3860
3861static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3862{
3863
3864
3865
3866
3867
3868 return isar_feature_aa32_mprofile(id) &&
3869 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3870}
3871
3872static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3873{
3874
3875
3876
3877
3878 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3879}
3880
3881static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3882{
3883
3884 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3885}
3886
3887static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3888{
3889 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3890}
3891
3892static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3893{
3894
3895 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3896}
3897
3898static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3899{
3900
3901 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3902}
3903
3904static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3905{
3906
3907 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3908}
3909
3910static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3911{
3912
3913 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3914}
3915
3916static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3917{
3918 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3919}
3920
3921
3922
3923
3924
3925
3926static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3927{
3928 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3929}
3930
3931static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3932{
3933 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3934}
3935
3936
3937
3938
3939
3940
3941
3942
3943static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3944{
3945 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3946}
3947
3948static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3949{
3950 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3951}
3952
3953static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3954{
3955 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3956}
3957
3958static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3959{
3960 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3961}
3962
3963static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3964{
3965 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3966}
3967
3968static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3969{
3970 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3971}
3972
3973static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3974{
3975 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3976}
3977
3978static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3979{
3980 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3981}
3982
3983static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3984{
3985
3986 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3987 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3988}
3989
3990static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3991{
3992
3993 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3994 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3995}
3996
3997static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3998{
3999 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
4000}
4001
4002static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
4003{
4004 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
4005}
4006
4007static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
4008{
4009 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
4010}
4011
4012static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
4013{
4014 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
4015}
4016
4017static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
4018{
4019 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
4020}
4021
4022static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
4023{
4024 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
4025}
4026
4027
4028
4029
4030static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
4031{
4032 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
4033}
4034
4035static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
4036{
4037 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
4038}
4039
4040static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
4041{
4042 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
4043}
4044
4045static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
4046{
4047 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
4048}
4049
4050static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
4051{
4052 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
4053}
4054
4055static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
4056{
4057 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
4058}
4059
4060static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
4061{
4062 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
4063}
4064
4065static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
4066{
4067 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
4068}
4069
4070static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
4071{
4072 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
4073}
4074
4075static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
4076{
4077 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
4078}
4079
4080static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
4081{
4082 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
4083}
4084
4085static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
4086{
4087 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
4088}
4089
4090static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
4091{
4092 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
4093}
4094
4095static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
4096{
4097 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
4098}
4099
4100static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
4101{
4102 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
4103}
4104
4105static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
4106{
4107 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
4108}
4109
4110static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
4111{
4112 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
4113}
4114
4115static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
4116{
4117 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
4118}
4119
4120static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
4121{
4122
4123
4124
4125
4126 return (id->id_aa64isar1 &
4127 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
4128 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
4129 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
4130 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
4131}
4132
4133static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
4134{
4135
4136
4137
4138
4139 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
4140}
4141
4142static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
4143{
4144 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
4145}
4146
4147static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
4148{
4149 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
4150}
4151
4152static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
4153{
4154 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
4155}
4156
4157static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
4158{
4159 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
4160}
4161
4162static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
4163{
4164 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
4165}
4166
4167static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
4168{
4169 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
4170}
4171
4172static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
4173{
4174 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
4175}
4176
4177static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
4178{
4179 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
4180}
4181
4182static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
4183{
4184
4185 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
4186}
4187
4188static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
4189{
4190
4191 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
4192}
4193
4194static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
4195{
4196 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
4197}
4198
4199static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
4200{
4201 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
4202}
4203
4204static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
4205{
4206 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
4207}
4208
4209static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
4210{
4211 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
4212}
4213
4214static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
4215{
4216 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
4217}
4218
4219static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
4220{
4221 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
4222}
4223
4224static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
4225{
4226 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
4227}
4228
4229static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
4230{
4231 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
4232}
4233
4234static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4235{
4236 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4237}
4238
4239static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4240{
4241 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4242}
4243
4244static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4245{
4246 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4247}
4248
4249static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4250{
4251 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4252}
4253
4254static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4255{
4256 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4257}
4258
4259static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
4260{
4261 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4262 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4263}
4264
4265static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
4266{
4267 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4268 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4269}
4270
4271static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4272{
4273 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4274}
4275
4276static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4277{
4278 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4279}
4280
4281static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4282{
4283 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4284}
4285
4286static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4287{
4288 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4289}
4290
4291static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4292{
4293 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4294}
4295
4296static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4297{
4298 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4299}
4300
4301static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4302{
4303 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4304}
4305
4306static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4307{
4308 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4309}
4310
4311static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4312{
4313 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4314}
4315
4316static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4317{
4318 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4319}
4320
4321static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4322{
4323 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4324}
4325
4326static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4327{
4328 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4329}
4330
4331static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4332{
4333 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4334}
4335
4336static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4337{
4338 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4339}
4340
4341static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4342{
4343 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4344}
4345
4346static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4347{
4348 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4349}
4350
4351static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4352{
4353 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4354}
4355
4356
4357
4358
4359static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4360{
4361 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4362}
4363
4364static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4365{
4366 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4367}
4368
4369static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4370{
4371 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4372}
4373
4374static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4375{
4376 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4377}
4378
4379static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4380{
4381 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4382}
4383
4384static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4385{
4386 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4387}
4388
4389
4390
4391
4392#define cpu_isar_feature(name, cpu) \
4393 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4394
4395#endif
4396