1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#ifndef TARGET_ARM_INTERNALS_H
26#define TARGET_ARM_INTERNALS_H
27
28#include "hw/registerfields.h"
29#include "tcg/tcg-gvec-desc.h"
30#include "syndrome.h"
31
32
33#define BANK_USRSYS 0
34#define BANK_SVC 1
35#define BANK_ABT 2
36#define BANK_UND 3
37#define BANK_IRQ 4
38#define BANK_FIQ 5
39#define BANK_HYP 6
40#define BANK_MON 7
41
42static inline bool excp_is_internal(int excp)
43{
44
45
46
47 return excp == EXCP_INTERRUPT
48 || excp == EXCP_HLT
49 || excp == EXCP_DEBUG
50 || excp == EXCP_HALTED
51 || excp == EXCP_EXCEPTION_EXIT
52 || excp == EXCP_KERNEL_TRAP
53 || excp == EXCP_SEMIHOST;
54}
55
56
57
58
59#define GTIMER_SCALE 16
60
61
62FIELD(V7M_CONTROL, NPRIV, 0, 1)
63FIELD(V7M_CONTROL, SPSEL, 1, 1)
64FIELD(V7M_CONTROL, FPCA, 2, 1)
65FIELD(V7M_CONTROL, SFPA, 3, 1)
66
67
68FIELD(V7M_EXCRET, ES, 0, 1)
69FIELD(V7M_EXCRET, RES0, 1, 1)
70FIELD(V7M_EXCRET, SPSEL, 2, 1)
71FIELD(V7M_EXCRET, MODE, 3, 1)
72FIELD(V7M_EXCRET, FTYPE, 4, 1)
73FIELD(V7M_EXCRET, DCRS, 5, 1)
74FIELD(V7M_EXCRET, S, 6, 1)
75FIELD(V7M_EXCRET, RES1, 7, 25)
76
77
78#define EXC_RETURN_MIN_MAGIC 0xff000000
79
80
81
82#define FNC_RETURN_MIN_MAGIC 0xfefffffe
83
84
85
86
87
88
89
90
91
92
93
94
95
96#define M_FAKE_FSR_NSC_EXEC 0xf
97#define M_FAKE_FSR_SFAULT 0xe
98
99
100
101
102
103
104
105void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
106 uint32_t syndrome, uint32_t target_el);
107
108
109
110
111void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp,
112 uint32_t syndrome, uint32_t target_el,
113 uintptr_t ra);
114
115
116
117
118
119
120
121static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
122{
123 static const unsigned int map[4] = {
124 [1] = BANK_SVC,
125 [2] = BANK_HYP,
126 [3] = BANK_MON,
127 };
128 assert(el >= 1 && el <= 3);
129 return map[el];
130}
131
132
133static inline int bank_number(int mode)
134{
135 switch (mode) {
136 case ARM_CPU_MODE_USR:
137 case ARM_CPU_MODE_SYS:
138 return BANK_USRSYS;
139 case ARM_CPU_MODE_SVC:
140 return BANK_SVC;
141 case ARM_CPU_MODE_ABT:
142 return BANK_ABT;
143 case ARM_CPU_MODE_UND:
144 return BANK_UND;
145 case ARM_CPU_MODE_IRQ:
146 return BANK_IRQ;
147 case ARM_CPU_MODE_FIQ:
148 return BANK_FIQ;
149 case ARM_CPU_MODE_HYP:
150 return BANK_HYP;
151 case ARM_CPU_MODE_MON:
152 return BANK_MON;
153 }
154 g_assert_not_reached();
155}
156
157
158
159
160
161
162
163
164
165
166
167
168static inline int r14_bank_number(int mode)
169{
170 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
171}
172
173void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
174void arm_translate_init(void);
175
176#ifdef CONFIG_TCG
177void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
178#endif
179
180
181
182
183
184
185
186
187
188
189uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
190
191enum arm_fprounding {
192 FPROUNDING_TIEEVEN,
193 FPROUNDING_POSINF,
194 FPROUNDING_NEGINF,
195 FPROUNDING_ZERO,
196 FPROUNDING_TIEAWAY,
197 FPROUNDING_ODD
198};
199
200int arm_rmode_to_sf(int rmode);
201
202static inline void aarch64_save_sp(CPUARMState *env, int el)
203{
204 if (env->pstate & PSTATE_SP) {
205 env->sp_el[el] = env->xregs[31];
206 } else {
207 env->sp_el[0] = env->xregs[31];
208 }
209}
210
211static inline void aarch64_restore_sp(CPUARMState *env, int el)
212{
213 if (env->pstate & PSTATE_SP) {
214 env->xregs[31] = env->sp_el[el];
215 } else {
216 env->xregs[31] = env->sp_el[0];
217 }
218}
219
220static inline void update_spsel(CPUARMState *env, uint32_t imm)
221{
222 unsigned int cur_el = arm_current_el(env);
223
224
225
226 if (!((imm ^ env->pstate) & PSTATE_SP)) {
227 return;
228 }
229 aarch64_save_sp(env, cur_el);
230 env->pstate = deposit32(env->pstate, 0, 1, imm);
231
232
233
234
235 assert(cur_el >= 1 && cur_el <= 3);
236 aarch64_restore_sp(env, cur_el);
237}
238
239
240
241
242
243
244
245
246static inline unsigned int arm_pamax(ARMCPU *cpu)
247{
248 static const unsigned int pamax_map[] = {
249 [0] = 32,
250 [1] = 36,
251 [2] = 40,
252 [3] = 42,
253 [4] = 44,
254 [5] = 48,
255 };
256 unsigned int parange =
257 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
258
259
260
261 assert(parange < ARRAY_SIZE(pamax_map));
262 return pamax_map[parange];
263}
264
265
266
267
268
269static inline bool extended_addresses_enabled(CPUARMState *env)
270{
271 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
272 return arm_el_is_aa64(env, 1) ||
273 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
274}
275
276
277
278
279void hw_watchpoint_update(ARMCPU *cpu, int n);
280
281
282
283
284void hw_watchpoint_update_all(ARMCPU *cpu);
285
286
287
288void hw_breakpoint_update(ARMCPU *cpu, int n);
289
290
291
292
293void hw_breakpoint_update_all(ARMCPU *cpu);
294
295
296bool arm_debug_check_breakpoint(CPUState *cs);
297
298
299bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
300
301
302
303
304vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
305
306
307void arm_debug_excp_handler(CPUState *cs);
308
309#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
310static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
311{
312 return false;
313}
314static inline void arm_handle_psci_call(ARMCPU *cpu)
315{
316 g_assert_not_reached();
317}
318#else
319
320bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
321
322void arm_handle_psci_call(ARMCPU *cpu);
323#endif
324
325
326
327
328
329
330static inline void arm_clear_exclusive(CPUARMState *env)
331{
332 env->exclusive_addr = -1;
333}
334
335
336
337
338
339
340typedef enum ARMFaultType {
341 ARMFault_None,
342 ARMFault_AccessFlag,
343 ARMFault_Alignment,
344 ARMFault_Background,
345 ARMFault_Domain,
346 ARMFault_Permission,
347 ARMFault_Translation,
348 ARMFault_AddressSize,
349 ARMFault_SyncExternal,
350 ARMFault_SyncExternalOnWalk,
351 ARMFault_SyncParity,
352 ARMFault_SyncParityOnWalk,
353 ARMFault_AsyncParity,
354 ARMFault_AsyncExternal,
355 ARMFault_Debug,
356 ARMFault_TLBConflict,
357 ARMFault_Lockdown,
358 ARMFault_Exclusive,
359 ARMFault_ICacheMaint,
360 ARMFault_QEMU_NSCExec,
361 ARMFault_QEMU_SFault,
362} ARMFaultType;
363
364
365
366
367
368
369
370
371
372
373
374
375typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
376struct ARMMMUFaultInfo {
377 ARMFaultType type;
378 target_ulong s2addr;
379 int level;
380 int domain;
381 bool stage2;
382 bool s1ptw;
383 bool s1ns;
384 bool ea;
385};
386
387
388
389
390
391
392
393static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi)
394{
395 uint32_t fsc;
396
397 switch (fi->type) {
398 case ARMFault_None:
399 return 0;
400 case ARMFault_AccessFlag:
401 fsc = fi->level == 1 ? 0x3 : 0x6;
402 break;
403 case ARMFault_Alignment:
404 fsc = 0x1;
405 break;
406 case ARMFault_Permission:
407 fsc = fi->level == 1 ? 0xd : 0xf;
408 break;
409 case ARMFault_Domain:
410 fsc = fi->level == 1 ? 0x9 : 0xb;
411 break;
412 case ARMFault_Translation:
413 fsc = fi->level == 1 ? 0x5 : 0x7;
414 break;
415 case ARMFault_SyncExternal:
416 fsc = 0x8 | (fi->ea << 12);
417 break;
418 case ARMFault_SyncExternalOnWalk:
419 fsc = fi->level == 1 ? 0xc : 0xe;
420 fsc |= (fi->ea << 12);
421 break;
422 case ARMFault_SyncParity:
423 fsc = 0x409;
424 break;
425 case ARMFault_SyncParityOnWalk:
426 fsc = fi->level == 1 ? 0x40c : 0x40e;
427 break;
428 case ARMFault_AsyncParity:
429 fsc = 0x408;
430 break;
431 case ARMFault_AsyncExternal:
432 fsc = 0x406 | (fi->ea << 12);
433 break;
434 case ARMFault_Debug:
435 fsc = 0x2;
436 break;
437 case ARMFault_TLBConflict:
438 fsc = 0x400;
439 break;
440 case ARMFault_Lockdown:
441 fsc = 0x404;
442 break;
443 case ARMFault_Exclusive:
444 fsc = 0x405;
445 break;
446 case ARMFault_ICacheMaint:
447 fsc = 0x4;
448 break;
449 case ARMFault_Background:
450 fsc = 0x0;
451 break;
452 case ARMFault_QEMU_NSCExec:
453 fsc = M_FAKE_FSR_NSC_EXEC;
454 break;
455 case ARMFault_QEMU_SFault:
456 fsc = M_FAKE_FSR_SFAULT;
457 break;
458 default:
459
460
461
462 g_assert_not_reached();
463 }
464
465 fsc |= (fi->domain << 4);
466 return fsc;
467}
468
469
470
471
472
473
474static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
475{
476 uint32_t fsc;
477
478 switch (fi->type) {
479 case ARMFault_None:
480 return 0;
481 case ARMFault_AddressSize:
482 fsc = fi->level & 3;
483 break;
484 case ARMFault_AccessFlag:
485 fsc = (fi->level & 3) | (0x2 << 2);
486 break;
487 case ARMFault_Permission:
488 fsc = (fi->level & 3) | (0x3 << 2);
489 break;
490 case ARMFault_Translation:
491 fsc = (fi->level & 3) | (0x1 << 2);
492 break;
493 case ARMFault_SyncExternal:
494 fsc = 0x10 | (fi->ea << 12);
495 break;
496 case ARMFault_SyncExternalOnWalk:
497 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
498 break;
499 case ARMFault_SyncParity:
500 fsc = 0x18;
501 break;
502 case ARMFault_SyncParityOnWalk:
503 fsc = (fi->level & 3) | (0x7 << 2);
504 break;
505 case ARMFault_AsyncParity:
506 fsc = 0x19;
507 break;
508 case ARMFault_AsyncExternal:
509 fsc = 0x11 | (fi->ea << 12);
510 break;
511 case ARMFault_Alignment:
512 fsc = 0x21;
513 break;
514 case ARMFault_Debug:
515 fsc = 0x22;
516 break;
517 case ARMFault_TLBConflict:
518 fsc = 0x30;
519 break;
520 case ARMFault_Lockdown:
521 fsc = 0x34;
522 break;
523 case ARMFault_Exclusive:
524 fsc = 0x35;
525 break;
526 default:
527
528
529
530 g_assert_not_reached();
531 }
532
533 fsc |= 1 << 9;
534 return fsc;
535}
536
537static inline bool arm_extabort_type(MemTxResult result)
538{
539
540
541
542
543
544 return result != MEMTX_DECODE_ERROR;
545}
546
547#ifdef CONFIG_USER_ONLY
548void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
549 MMUAccessType access_type,
550 bool maperr, uintptr_t ra);
551void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
552 MMUAccessType access_type, uintptr_t ra);
553#else
554bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
555 MMUAccessType access_type, int mmu_idx,
556 bool probe, uintptr_t retaddr);
557#endif
558
559static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
560{
561 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
562}
563
564static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
565{
566 if (arm_feature(env, ARM_FEATURE_M)) {
567 return mmu_idx | ARM_MMU_IDX_M;
568 } else {
569 return mmu_idx | ARM_MMU_IDX_A;
570 }
571}
572
573static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
574{
575
576 return mmu_idx | ARM_MMU_IDX_A;
577}
578
579int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
580
581
582
583
584
585ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
586 bool secstate, bool priv, bool negpri);
587
588
589
590
591
592ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
593 bool secstate, bool priv);
594
595
596ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
597
598
599
600bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
601
602
603void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
604 MMUAccessType access_type,
605 int mmu_idx, uintptr_t retaddr) QEMU_NORETURN;
606
607
608
609
610
611void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
612 vaddr addr, unsigned size,
613 MMUAccessType access_type,
614 int mmu_idx, MemTxAttrs attrs,
615 MemTxResult response, uintptr_t retaddr);
616
617
618static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
619{
620 ARMELChangeHook *hook, *next;
621 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
622 hook->hook(cpu, hook->opaque);
623 }
624}
625static inline void arm_call_el_change_hook(ARMCPU *cpu)
626{
627 ARMELChangeHook *hook, *next;
628 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
629 hook->hook(cpu, hook->opaque);
630 }
631}
632
633
634static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
635{
636 switch (mmu_idx) {
637 case ARMMMUIdx_Stage1_E0:
638 case ARMMMUIdx_Stage1_E1:
639 case ARMMMUIdx_Stage1_E1_PAN:
640 case ARMMMUIdx_Stage1_SE0:
641 case ARMMMUIdx_Stage1_SE1:
642 case ARMMMUIdx_Stage1_SE1_PAN:
643 case ARMMMUIdx_E10_0:
644 case ARMMMUIdx_E10_1:
645 case ARMMMUIdx_E10_1_PAN:
646 case ARMMMUIdx_E20_0:
647 case ARMMMUIdx_E20_2:
648 case ARMMMUIdx_E20_2_PAN:
649 case ARMMMUIdx_SE10_0:
650 case ARMMMUIdx_SE10_1:
651 case ARMMMUIdx_SE10_1_PAN:
652 case ARMMMUIdx_SE20_0:
653 case ARMMMUIdx_SE20_2:
654 case ARMMMUIdx_SE20_2_PAN:
655 return true;
656 default:
657 return false;
658 }
659}
660
661
662static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
663{
664 switch (mmu_idx) {
665 case ARMMMUIdx_E10_0:
666 case ARMMMUIdx_E10_1:
667 case ARMMMUIdx_E10_1_PAN:
668 case ARMMMUIdx_E20_0:
669 case ARMMMUIdx_E20_2:
670 case ARMMMUIdx_E20_2_PAN:
671 case ARMMMUIdx_Stage1_E0:
672 case ARMMMUIdx_Stage1_E1:
673 case ARMMMUIdx_Stage1_E1_PAN:
674 case ARMMMUIdx_E2:
675 case ARMMMUIdx_Stage2:
676 case ARMMMUIdx_MPrivNegPri:
677 case ARMMMUIdx_MUserNegPri:
678 case ARMMMUIdx_MPriv:
679 case ARMMMUIdx_MUser:
680 return false;
681 case ARMMMUIdx_SE3:
682 case ARMMMUIdx_SE10_0:
683 case ARMMMUIdx_SE10_1:
684 case ARMMMUIdx_SE10_1_PAN:
685 case ARMMMUIdx_SE20_0:
686 case ARMMMUIdx_SE20_2:
687 case ARMMMUIdx_SE20_2_PAN:
688 case ARMMMUIdx_Stage1_SE0:
689 case ARMMMUIdx_Stage1_SE1:
690 case ARMMMUIdx_Stage1_SE1_PAN:
691 case ARMMMUIdx_SE2:
692 case ARMMMUIdx_Stage2_S:
693 case ARMMMUIdx_MSPrivNegPri:
694 case ARMMMUIdx_MSUserNegPri:
695 case ARMMMUIdx_MSPriv:
696 case ARMMMUIdx_MSUser:
697 return true;
698 default:
699 g_assert_not_reached();
700 }
701}
702
703static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
704{
705 switch (mmu_idx) {
706 case ARMMMUIdx_Stage1_E1_PAN:
707 case ARMMMUIdx_Stage1_SE1_PAN:
708 case ARMMMUIdx_E10_1_PAN:
709 case ARMMMUIdx_E20_2_PAN:
710 case ARMMMUIdx_SE10_1_PAN:
711 case ARMMMUIdx_SE20_2_PAN:
712 return true;
713 default:
714 return false;
715 }
716}
717
718
719static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
720{
721 switch (mmu_idx) {
722 case ARMMMUIdx_SE20_0:
723 case ARMMMUIdx_SE20_2:
724 case ARMMMUIdx_SE20_2_PAN:
725 case ARMMMUIdx_E20_0:
726 case ARMMMUIdx_E20_2:
727 case ARMMMUIdx_E20_2_PAN:
728 case ARMMMUIdx_Stage2:
729 case ARMMMUIdx_Stage2_S:
730 case ARMMMUIdx_SE2:
731 case ARMMMUIdx_E2:
732 return 2;
733 case ARMMMUIdx_SE3:
734 return 3;
735 case ARMMMUIdx_SE10_0:
736 case ARMMMUIdx_Stage1_SE0:
737 return arm_el_is_aa64(env, 3) ? 1 : 3;
738 case ARMMMUIdx_SE10_1:
739 case ARMMMUIdx_SE10_1_PAN:
740 case ARMMMUIdx_Stage1_E0:
741 case ARMMMUIdx_Stage1_E1:
742 case ARMMMUIdx_Stage1_E1_PAN:
743 case ARMMMUIdx_Stage1_SE1:
744 case ARMMMUIdx_Stage1_SE1_PAN:
745 case ARMMMUIdx_E10_0:
746 case ARMMMUIdx_E10_1:
747 case ARMMMUIdx_E10_1_PAN:
748 case ARMMMUIdx_MPrivNegPri:
749 case ARMMMUIdx_MUserNegPri:
750 case ARMMMUIdx_MPriv:
751 case ARMMMUIdx_MUser:
752 case ARMMMUIdx_MSPrivNegPri:
753 case ARMMMUIdx_MSUserNegPri:
754 case ARMMMUIdx_MSPriv:
755 case ARMMMUIdx_MSUser:
756 return 1;
757 default:
758 g_assert_not_reached();
759 }
760}
761
762
763static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
764{
765 if (mmu_idx == ARMMMUIdx_Stage2) {
766 return &env->cp15.vtcr_el2;
767 }
768 if (mmu_idx == ARMMMUIdx_Stage2_S) {
769
770
771
772
773 return &env->cp15.vstcr_el2;
774 }
775 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
776}
777
778
779
780
781static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
782{
783 ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
784 int target_el = arm_debug_target_el(env);
785 bool using_lpae = false;
786
787 if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
788 using_lpae = true;
789 } else {
790 if (arm_feature(env, ARM_FEATURE_LPAE) &&
791 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
792 using_lpae = true;
793 }
794 }
795
796 if (using_lpae) {
797 return arm_fi_to_lfsc(&fi);
798 } else {
799 return arm_fi_to_sfsc(&fi);
800 }
801}
802
803
804
805
806
807
808static inline int arm_num_brps(ARMCPU *cpu)
809{
810 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
811 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
812 } else {
813 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
814 }
815}
816
817
818
819
820
821
822static inline int arm_num_wrps(ARMCPU *cpu)
823{
824 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
825 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
826 } else {
827 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
828 }
829}
830
831
832
833
834
835
836static inline int arm_num_ctx_cmps(ARMCPU *cpu)
837{
838 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
839 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
840 } else {
841 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
842 }
843}
844
845
846
847
848
849
850static inline bool v7m_using_psp(CPUARMState *env)
851{
852
853
854
855
856
857 return !arm_v7m_is_handler_mode(env) &&
858 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
859}
860
861
862
863
864
865
866static inline uint32_t v7m_sp_limit(CPUARMState *env)
867{
868 if (v7m_using_psp(env)) {
869 return env->v7m.psplim[env->v7m.secure];
870 } else {
871 return env->v7m.msplim[env->v7m.secure];
872 }
873}
874
875
876
877
878
879
880static inline bool v7m_cpacr_pass(CPUARMState *env,
881 bool is_secure, bool is_priv)
882{
883 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
884 case 0:
885 case 2:
886 return false;
887 case 1:
888 return is_priv;
889 case 3:
890 return true;
891 default:
892 g_assert_not_reached();
893 }
894}
895
896
897
898
899
900
901
902
903
904static inline const char *aarch32_mode_name(uint32_t psr)
905{
906 static const char cpu_mode_names[16][4] = {
907 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
908 "???", "???", "hyp", "und", "???", "???", "???", "sys"
909 };
910
911 return cpu_mode_names[psr & 0xf];
912}
913
914
915
916
917
918
919
920
921void arm_cpu_update_virq(ARMCPU *cpu);
922
923
924
925
926
927
928
929
930void arm_cpu_update_vfiq(ARMCPU *cpu);
931
932
933
934
935
936
937
938
939ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
940
941
942
943
944
945
946
947ARMMMUIdx arm_mmu_idx(CPUARMState *env);
948
949
950
951
952
953
954
955#ifdef CONFIG_USER_ONLY
956static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
957{
958 return ARMMMUIdx_Stage1_E0;
959}
960#else
961ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
962#endif
963
964
965
966
967
968
969
970
971static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
972{
973 switch (mmu_idx) {
974 case ARMMMUIdx_Stage1_E0:
975 case ARMMMUIdx_Stage1_E1:
976 case ARMMMUIdx_Stage1_E1_PAN:
977 case ARMMMUIdx_Stage1_SE0:
978 case ARMMMUIdx_Stage1_SE1:
979 case ARMMMUIdx_Stage1_SE1_PAN:
980 return true;
981 default:
982 return false;
983 }
984}
985
986static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
987 const ARMISARegisters *id)
988{
989 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
990
991 if ((features >> ARM_FEATURE_V4T) & 1) {
992 valid |= CPSR_T;
993 }
994 if ((features >> ARM_FEATURE_V5) & 1) {
995 valid |= CPSR_Q;
996 }
997 if ((features >> ARM_FEATURE_V6) & 1) {
998 valid |= CPSR_E | CPSR_GE;
999 }
1000 if ((features >> ARM_FEATURE_THUMB2) & 1) {
1001 valid |= CPSR_IT;
1002 }
1003 if (isar_feature_aa32_jazelle(id)) {
1004 valid |= CPSR_J;
1005 }
1006 if (isar_feature_aa32_pan(id)) {
1007 valid |= CPSR_PAN;
1008 }
1009 if (isar_feature_aa32_dit(id)) {
1010 valid |= CPSR_DIT;
1011 }
1012 if (isar_feature_aa32_ssbs(id)) {
1013 valid |= CPSR_SSBS;
1014 }
1015
1016 return valid;
1017}
1018
1019static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
1020{
1021 uint32_t valid;
1022
1023 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
1024 if (isar_feature_aa64_bti(id)) {
1025 valid |= PSTATE_BTYPE;
1026 }
1027 if (isar_feature_aa64_pan(id)) {
1028 valid |= PSTATE_PAN;
1029 }
1030 if (isar_feature_aa64_uao(id)) {
1031 valid |= PSTATE_UAO;
1032 }
1033 if (isar_feature_aa64_dit(id)) {
1034 valid |= PSTATE_DIT;
1035 }
1036 if (isar_feature_aa64_ssbs(id)) {
1037 valid |= PSTATE_SSBS;
1038 }
1039 if (isar_feature_aa64_mte(id)) {
1040 valid |= PSTATE_TCO;
1041 }
1042
1043 return valid;
1044}
1045
1046
1047
1048
1049
1050typedef struct ARMVAParameters {
1051 unsigned tsz : 8;
1052 unsigned select : 1;
1053 bool tbi : 1;
1054 bool epd : 1;
1055 bool hpd : 1;
1056 bool using16k : 1;
1057 bool using64k : 1;
1058} ARMVAParameters;
1059
1060ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1061 ARMMMUIdx mmu_idx, bool data);
1062
1063static inline int exception_target_el(CPUARMState *env)
1064{
1065 int target_el = MAX(1, arm_current_el(env));
1066
1067
1068
1069
1070
1071 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
1072 target_el = 3;
1073 }
1074
1075 return target_el;
1076}
1077
1078
1079static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
1080 uint64_t sctlr)
1081{
1082 if (el < 3
1083 && arm_feature(env, ARM_FEATURE_EL3)
1084 && !(env->cp15.scr_el3 & SCR_ATA)) {
1085 return false;
1086 }
1087 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
1088 uint64_t hcr = arm_hcr_el2_eff(env);
1089 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
1090 return false;
1091 }
1092 }
1093 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
1094 return sctlr != 0;
1095}
1096
1097#ifndef CONFIG_USER_ONLY
1098
1099
1100typedef struct V8M_SAttributes {
1101 bool subpage;
1102 bool ns;
1103 bool nsc;
1104 uint8_t sregion;
1105 bool srvalid;
1106 uint8_t iregion;
1107 bool irvalid;
1108} V8M_SAttributes;
1109
1110void v8m_security_lookup(CPUARMState *env, uint32_t address,
1111 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1112 V8M_SAttributes *sattrs);
1113
1114bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
1115 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1116 hwaddr *phys_ptr, MemTxAttrs *txattrs,
1117 int *prot, bool *is_subpage,
1118 ARMMMUFaultInfo *fi, uint32_t *mregion);
1119
1120
1121typedef struct ARMCacheAttrs {
1122 unsigned int attrs:8;
1123 unsigned int shareability:2;
1124} ARMCacheAttrs;
1125
1126bool get_phys_addr(CPUARMState *env, target_ulong address,
1127 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1128 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
1129 target_ulong *page_size,
1130 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
1131 __attribute__((nonnull));
1132
1133void arm_log_exception(int idx);
1134
1135#endif
1136
1137
1138
1139
1140
1141#define GMID_EL1_BS 6
1142
1143
1144#define LOG2_TAG_GRANULE 4
1145#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
1146
1147
1148
1149
1150
1151
1152FIELD(PREDDESC, OPRSZ, 0, 6)
1153FIELD(PREDDESC, ESZ, 6, 2)
1154FIELD(PREDDESC, DATA, 8, 24)
1155
1156
1157
1158
1159
1160#define SVE_MTEDESC_SHIFT 5
1161
1162
1163FIELD(MTEDESC, MIDX, 0, 4)
1164FIELD(MTEDESC, TBI, 4, 2)
1165FIELD(MTEDESC, TCMA, 6, 2)
1166FIELD(MTEDESC, WRITE, 8, 1)
1167FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9)
1168
1169bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
1170uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
1171
1172static inline int allocation_tag_from_addr(uint64_t ptr)
1173{
1174 return extract64(ptr, 56, 4);
1175}
1176
1177static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
1178{
1179 return deposit64(ptr, 56, 4, rtag);
1180}
1181
1182
1183static inline bool tbi_check(uint32_t desc, int bit55)
1184{
1185 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
1186}
1187
1188
1189static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag)
1190{
1191
1192
1193
1194
1195 bool match = ((ptr_tag + bit55) & 0xf) == 0;
1196 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1;
1197 return tcma && match;
1198}
1199
1200
1201
1202
1203
1204
1205
1206static inline uint64_t useronly_clean_ptr(uint64_t ptr)
1207{
1208#ifdef CONFIG_USER_ONLY
1209
1210 ptr &= sextract64(ptr, 0, 56);
1211#endif
1212 return ptr;
1213}
1214
1215static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
1216{
1217#ifdef CONFIG_USER_ONLY
1218 int64_t clean_ptr = sextract64(ptr, 0, 56);
1219 if (tbi_check(desc, clean_ptr < 0)) {
1220 ptr = clean_ptr;
1221 }
1222#endif
1223 return ptr;
1224}
1225
1226
1227enum MVEECIState {
1228 ECI_NONE = 0,
1229 ECI_A0 = 1,
1230 ECI_A0A1 = 2,
1231
1232 ECI_A0A1A2 = 4,
1233 ECI_A0A1A2B0 = 5,
1234
1235};
1236
1237
1238#define PMCRN_MASK 0xf800
1239#define PMCRN_SHIFT 11
1240#define PMCRLC 0x40
1241#define PMCRDP 0x20
1242#define PMCRX 0x10
1243#define PMCRD 0x8
1244#define PMCRC 0x4
1245#define PMCRP 0x2
1246#define PMCRE 0x1
1247
1248
1249
1250
1251#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1252
1253#define PMXEVTYPER_P 0x80000000
1254#define PMXEVTYPER_U 0x40000000
1255#define PMXEVTYPER_NSK 0x20000000
1256#define PMXEVTYPER_NSU 0x10000000
1257#define PMXEVTYPER_NSH 0x08000000
1258#define PMXEVTYPER_M 0x04000000
1259#define PMXEVTYPER_MT 0x02000000
1260#define PMXEVTYPER_EVTCOUNT 0x0000ffff
1261#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1262 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1263 PMXEVTYPER_M | PMXEVTYPER_MT | \
1264 PMXEVTYPER_EVTCOUNT)
1265
1266#define PMCCFILTR 0xf8000000
1267#define PMCCFILTR_M PMXEVTYPER_M
1268#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1269
1270static inline uint32_t pmu_num_counters(CPUARMState *env)
1271{
1272 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
1273}
1274
1275
1276static inline uint64_t pmu_counter_mask(CPUARMState *env)
1277{
1278 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
1279}
1280
1281#ifdef TARGET_AARCH64
1282int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
1283int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
1284int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
1285int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
1286#endif
1287
1288#endif
1289