1#ifndef TARGET_ARM_TRANSLATE_H
2#define TARGET_ARM_TRANSLATE_H
3
4#include "exec/translator.h"
5#include "internals.h"
6
7
8
9typedef struct DisasContext {
10 DisasContextBase base;
11 const ARMISARegisters *isar;
12
13
14 target_ulong pc_curr;
15 target_ulong page_start;
16 uint32_t insn;
17
18 int condjmp;
19
20 TCGLabel *condlabel;
21
22 int condexec_mask;
23 int condexec_cond;
24
25 int eci;
26
27
28
29
30 bool eci_handled;
31
32 TCGOp *insn_eci_rewind;
33 int thumb;
34 int sctlr_b;
35 MemOp be_data;
36#if !defined(CONFIG_USER_ONLY)
37 int user;
38#endif
39 ARMMMUIdx mmu_idx;
40 uint8_t tbii;
41 uint8_t tbid;
42 uint8_t tcma;
43 bool ns;
44 int fp_excp_el;
45 int sve_excp_el;
46 int sve_len;
47
48 bool secure_routed_to_el3;
49 bool vfp_enabled;
50 int vec_len;
51 int vec_stride;
52 bool v7m_handler_mode;
53 bool v8m_secure;
54 bool v8m_stackcheck;
55 bool v8m_fpccr_s_wrong;
56 bool v7m_new_fp_ctxt_needed;
57 bool v7m_lspact;
58
59
60
61 uint32_t svc_imm;
62 int aarch64;
63 int current_el;
64
65 int debug_target_el;
66 GHashTable *cp_regs;
67 uint64_t features;
68
69
70
71
72
73
74
75 bool fp_access_checked;
76 bool sve_access_checked;
77
78
79
80 bool ss_active;
81 bool pstate_ss;
82
83
84
85
86 bool is_ldex;
87
88 bool unpriv;
89
90 bool pauth_active;
91
92 bool ata;
93
94 bool mte_active[2];
95
96 bool bt;
97
98 bool hstr_active;
99
100 bool align_mem;
101
102 bool pstate_il;
103
104 bool mve_no_pred;
105
106
107
108
109 int8_t btype;
110
111 uint8_t dcz_blocksize;
112
113 bool guarded_page;
114
115 int c15_cpar;
116
117 TCGOp *insn_start;
118#define TMP_A64_MAX 16
119 int tmp_a64_count;
120 TCGv_i64 tmp_a64[TMP_A64_MAX];
121} DisasContext;
122
123typedef struct DisasCompare {
124 TCGCond cond;
125 TCGv_i32 value;
126 bool value_global;
127} DisasCompare;
128
129
130extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
131extern TCGv_i64 cpu_exclusive_addr;
132extern TCGv_i64 cpu_exclusive_val;
133
134
135
136
137
138static inline int negate(DisasContext *s, int x)
139{
140 return -x;
141}
142
143static inline int plus_1(DisasContext *s, int x)
144{
145 return x + 1;
146}
147
148static inline int plus_2(DisasContext *s, int x)
149{
150 return x + 2;
151}
152
153static inline int times_2(DisasContext *s, int x)
154{
155 return x * 2;
156}
157
158static inline int times_4(DisasContext *s, int x)
159{
160 return x * 4;
161}
162
163static inline int times_2_plus_1(DisasContext *s, int x)
164{
165 return x * 2 + 1;
166}
167
168static inline int rsub_64(DisasContext *s, int x)
169{
170 return 64 - x;
171}
172
173static inline int rsub_32(DisasContext *s, int x)
174{
175 return 32 - x;
176}
177
178static inline int rsub_16(DisasContext *s, int x)
179{
180 return 16 - x;
181}
182
183static inline int rsub_8(DisasContext *s, int x)
184{
185 return 8 - x;
186}
187
188static inline int neon_3same_fp_size(DisasContext *s, int x)
189{
190
191 return MO_32 - x;
192}
193
194static inline int arm_dc_feature(DisasContext *dc, int feature)
195{
196 return (dc->features & (1ULL << feature)) != 0;
197}
198
199static inline int get_mem_index(DisasContext *s)
200{
201 return arm_to_core_mmu_idx(s->mmu_idx);
202}
203
204
205
206
207static inline int default_exception_el(DisasContext *s)
208{
209
210
211
212
213
214 return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
215 ? 3 : MAX(1, s->current_el);
216}
217
218static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
219{
220
221
222
223 syn &= ARM_INSN_START_WORD2_MASK;
224 syn >>= ARM_INSN_START_WORD2_SHIFT;
225
226
227 assert(s->insn_start != NULL);
228 tcg_set_insn_start_param(s->insn_start, 2, syn);
229 s->insn_start = NULL;
230}
231
232
233#define DISAS_JUMP DISAS_TARGET_0
234
235#define DISAS_UPDATE_EXIT DISAS_TARGET_1
236
237
238
239
240#define DISAS_WFI DISAS_TARGET_2
241#define DISAS_SWI DISAS_TARGET_3
242
243#define DISAS_WFE DISAS_TARGET_4
244#define DISAS_HVC DISAS_TARGET_5
245#define DISAS_SMC DISAS_TARGET_6
246#define DISAS_YIELD DISAS_TARGET_7
247
248
249
250#define DISAS_BX_EXCRET DISAS_TARGET_8
251
252
253
254
255
256
257
258#define DISAS_EXIT DISAS_TARGET_9
259
260#define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
261
262#ifdef TARGET_AARCH64
263void a64_translate_init(void);
264void gen_a64_set_pc_im(uint64_t val);
265extern const TranslatorOps aarch64_translator_ops;
266#else
267static inline void a64_translate_init(void)
268{
269}
270
271static inline void gen_a64_set_pc_im(uint64_t val)
272{
273}
274#endif
275
276void arm_test_cc(DisasCompare *cmp, int cc);
277void arm_free_cc(DisasCompare *cmp);
278void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
279void arm_gen_test_cc(int cc, TCGLabel *label);
280MemOp pow2_align(unsigned i);
281void unallocated_encoding(DisasContext *s);
282void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
283 uint32_t syn, uint32_t target_el);
284
285
286static inline TCGv_i32 get_ahp_flag(void)
287{
288 TCGv_i32 ret = tcg_temp_new_i32();
289
290 tcg_gen_ld_i32(ret, cpu_env,
291 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
292 tcg_gen_extract_i32(ret, ret, 26, 1);
293
294 return ret;
295}
296
297
298static inline void set_pstate_bits(uint32_t bits)
299{
300 TCGv_i32 p = tcg_temp_new_i32();
301
302 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
303
304 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
305 tcg_gen_ori_i32(p, p, bits);
306 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
307 tcg_temp_free_i32(p);
308}
309
310
311static inline void clear_pstate_bits(uint32_t bits)
312{
313 TCGv_i32 p = tcg_temp_new_i32();
314
315 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
316
317 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
318 tcg_gen_andi_i32(p, p, ~bits);
319 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
320 tcg_temp_free_i32(p);
321}
322
323
324static inline void gen_ss_advance(DisasContext *s)
325{
326 if (s->ss_active) {
327 s->pstate_ss = 0;
328 clear_pstate_bits(PSTATE_SS);
329 }
330}
331
332static inline void gen_exception(int excp, uint32_t syndrome,
333 uint32_t target_el)
334{
335 TCGv_i32 tcg_excp = tcg_const_i32(excp);
336 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
337 TCGv_i32 tcg_el = tcg_const_i32(target_el);
338
339 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
340 tcg_syn, tcg_el);
341
342 tcg_temp_free_i32(tcg_el);
343 tcg_temp_free_i32(tcg_syn);
344 tcg_temp_free_i32(tcg_excp);
345}
346
347
348static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
349{
350 bool same_el = (s->debug_target_el == s->current_el);
351
352
353
354
355
356 assert(s->debug_target_el >= s->current_el);
357
358 gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
359}
360
361
362
363
364
365
366uint64_t vfp_expand_imm(int size, uint8_t imm8);
367
368
369void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
370 uint32_t opr_sz, uint32_t max_sz);
371void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
372 uint32_t opr_sz, uint32_t max_sz);
373void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
374 uint32_t opr_sz, uint32_t max_sz);
375void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
376 uint32_t opr_sz, uint32_t max_sz);
377void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
378 uint32_t opr_sz, uint32_t max_sz);
379
380void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
381 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
382void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
383 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
384
385void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
386 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
387void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
388 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
389void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
390 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
391
392void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
393void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
394void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
395void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
396void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
397
398void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
399 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
400void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
401 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
402void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
403 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
404void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
405 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
406
407void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
408 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
409void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
410 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
411
412void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
413 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
414void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
415 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
416void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
417 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
418void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
419 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
420
421void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
422 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
423void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
424 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
425
426void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
427 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
428void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
429 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
430
431void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
432 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
433void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
434 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
435
436void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
437 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
438void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
439 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
440
441
442
443
444#define dc_isar_feature(name, ctx) \
445 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
446
447
448typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
449typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
450 uint32_t, uint32_t);
451typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
452 uint32_t, uint32_t, uint32_t);
453typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
454 uint32_t, uint32_t, uint32_t);
455
456
457typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
458typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
459typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
460typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
461typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
462 TCGv_i32, TCGv_i32);
463typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
464typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
465typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
466typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
467typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
468typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
469typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
470typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
471typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
472typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
473typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
474typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
475typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
476typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
477typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
478typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
479typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
480typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
481
482
483
484
485
486
487
488static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
489{
490 return (CPUARMTBFlags){ tb->flags, tb->cs_base };
491}
492
493
494
495
496typedef enum ARMFPStatusFlavour {
497 FPST_FPCR,
498 FPST_FPCR_F16,
499 FPST_STD,
500 FPST_STD_F16,
501} ARMFPStatusFlavour;
502
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519
520static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
521{
522 TCGv_ptr statusptr = tcg_temp_new_ptr();
523 int offset;
524
525 switch (flavour) {
526 case FPST_FPCR:
527 offset = offsetof(CPUARMState, vfp.fp_status);
528 break;
529 case FPST_FPCR_F16:
530 offset = offsetof(CPUARMState, vfp.fp_status_f16);
531 break;
532 case FPST_STD:
533 offset = offsetof(CPUARMState, vfp.standard_fp_status);
534 break;
535 case FPST_STD_F16:
536 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
537 break;
538 default:
539 g_assert_not_reached();
540 }
541 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
542 return statusptr;
543}
544
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560
561static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
562{
563 if (s->align_mem && !(opc & MO_AMASK)) {
564 opc |= MO_ALIGN;
565 }
566 return opc | s->be_data;
567}
568
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583
584uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
585
586#endif
587