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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "hw/core/tcg-cpu-ops.h"
24#include "exec/exec-all.h"
25#include "exec/address-spaces.h"
26#include "exec/helper-proto.h"
27
28bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
29{
30 bool ret = false;
31 CPUClass *cc = CPU_GET_CLASS(cs);
32 AVRCPU *cpu = AVR_CPU(cs);
33 CPUAVRState *env = &cpu->env;
34
35 if (interrupt_request & CPU_INTERRUPT_RESET) {
36 if (cpu_interrupts_enabled(env)) {
37 cs->exception_index = EXCP_RESET;
38 cc->tcg_ops->do_interrupt(cs);
39
40 cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
41
42 ret = true;
43 }
44 }
45 if (interrupt_request & CPU_INTERRUPT_HARD) {
46 if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
47 int index = ctz32(env->intsrc);
48 cs->exception_index = EXCP_INT(index);
49 cc->tcg_ops->do_interrupt(cs);
50
51 env->intsrc &= env->intsrc - 1;
52 if (!env->intsrc) {
53 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
54 }
55
56 ret = true;
57 }
58 }
59 return ret;
60}
61
62void avr_cpu_do_interrupt(CPUState *cs)
63{
64 AVRCPU *cpu = AVR_CPU(cs);
65 CPUAVRState *env = &cpu->env;
66
67 uint32_t ret = env->pc_w;
68 int vector = 0;
69 int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
70 int base = 0;
71
72 if (cs->exception_index == EXCP_RESET) {
73 vector = 0;
74 } else if (env->intsrc != 0) {
75 vector = ctz32(env->intsrc) + 1;
76 }
77
78 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
79 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
80 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
81 cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
82 } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
83 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
84 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
85 } else {
86 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
87 }
88
89 env->pc_w = base + vector * size;
90 env->sregI = 0;
91
92 cs->exception_index = -1;
93}
94
95int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
96 int len, bool is_write)
97{
98 return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
99}
100
101hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
102{
103 return addr;
104}
105
106bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
107 MMUAccessType access_type, int mmu_idx,
108 bool probe, uintptr_t retaddr)
109{
110 int prot = 0;
111 MemTxAttrs attrs = {};
112 uint32_t paddr;
113
114 address &= TARGET_PAGE_MASK;
115
116 if (mmu_idx == MMU_CODE_IDX) {
117
118 paddr = OFFSET_CODE + address;
119 prot = PAGE_READ | PAGE_EXEC;
120 if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
121 error_report("execution left flash memory");
122 abort();
123 }
124 } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
125
126
127
128
129 AVRCPU *cpu = AVR_CPU(cs);
130 CPUAVRState *env = &cpu->env;
131 env->fullacc = 1;
132 cpu_loop_exit_restore(cs, retaddr);
133 } else {
134
135 paddr = OFFSET_DATA + address;
136 prot = PAGE_READ | PAGE_WRITE;
137 }
138
139 tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
140 mmu_idx, TARGET_PAGE_SIZE);
141
142 return true;
143}
144
145
146
147
148
149void helper_sleep(CPUAVRState *env)
150{
151 CPUState *cs = env_cpu(env);
152
153 cs->exception_index = EXCP_HLT;
154 cpu_loop_exit(cs);
155}
156
157void helper_unsupported(CPUAVRState *env)
158{
159 CPUState *cs = env_cpu(env);
160
161
162
163
164
165 cs->exception_index = EXCP_DEBUG;
166 if (qemu_loglevel_mask(LOG_UNIMP)) {
167 qemu_log("UNSUPPORTED\n");
168 cpu_dump_state(cs, stderr, 0);
169 }
170 cpu_loop_exit(cs);
171}
172
173void helper_debug(CPUAVRState *env)
174{
175 CPUState *cs = env_cpu(env);
176
177 cs->exception_index = EXCP_DEBUG;
178 cpu_loop_exit(cs);
179}
180
181void helper_break(CPUAVRState *env)
182{
183 CPUState *cs = env_cpu(env);
184
185 cs->exception_index = EXCP_DEBUG;
186 cpu_loop_exit(cs);
187}
188
189void helper_wdr(CPUAVRState *env)
190{
191 qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
192}
193
194
195
196
197
198
199
200
201
202
203
204target_ulong helper_inb(CPUAVRState *env, uint32_t port)
205{
206 target_ulong data = 0;
207
208 switch (port) {
209 case 0x38:
210 data = 0xff & (env->rampD >> 16);
211 break;
212 case 0x39:
213 data = 0xff & (env->rampX >> 16);
214 break;
215 case 0x3a:
216 data = 0xff & (env->rampY >> 16);
217 break;
218 case 0x3b:
219 data = 0xff & (env->rampZ >> 16);
220 break;
221 case 0x3c:
222 data = 0xff & (env->eind >> 16);
223 break;
224 case 0x3d:
225 data = env->sp & 0x00ff;
226 break;
227 case 0x3e:
228 data = env->sp >> 8;
229 break;
230 case 0x3f:
231 data = cpu_get_sreg(env);
232 break;
233 default:
234
235 data = address_space_ldub(&address_space_memory,
236 OFFSET_IO_REGISTERS + port,
237 MEMTXATTRS_UNSPECIFIED, NULL);
238 }
239
240 return data;
241}
242
243
244
245
246
247
248
249
250
251
252
253void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
254{
255 data &= 0x000000ff;
256
257 switch (port) {
258 case 0x38:
259 if (avr_feature(env, AVR_FEATURE_RAMPD)) {
260 env->rampD = (data & 0xff) << 16;
261 }
262 break;
263 case 0x39:
264 if (avr_feature(env, AVR_FEATURE_RAMPX)) {
265 env->rampX = (data & 0xff) << 16;
266 }
267 break;
268 case 0x3a:
269 if (avr_feature(env, AVR_FEATURE_RAMPY)) {
270 env->rampY = (data & 0xff) << 16;
271 }
272 break;
273 case 0x3b:
274 if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
275 env->rampZ = (data & 0xff) << 16;
276 }
277 break;
278 case 0x3c:
279 env->eind = (data & 0xff) << 16;
280 break;
281 case 0x3d:
282 env->sp = (env->sp & 0xff00) | (data);
283 break;
284 case 0x3e:
285 if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
286 env->sp = (env->sp & 0x00ff) | (data << 8);
287 }
288 break;
289 case 0x3f:
290 cpu_set_sreg(env, data);
291 break;
292 default:
293
294 address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
295 data, MEMTXATTRS_UNSPECIFIED, NULL);
296 }
297}
298
299
300
301
302
303target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
304{
305 uint8_t data;
306
307 env->fullacc = false;
308
309 if (addr < NUMBER_OF_CPU_REGISTERS) {
310
311 data = env->r[addr];
312 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
313
314 data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
315 } else {
316
317 data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
318 MEMTXATTRS_UNSPECIFIED, NULL);
319 }
320 return data;
321}
322
323
324
325
326
327void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
328{
329 env->fullacc = false;
330
331
332 assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
333 assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
334 NUMBER_OF_CPU_REGISTERS);
335
336 if (addr < NUMBER_OF_CPU_REGISTERS) {
337
338 env->r[addr] = data;
339 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
340
341 helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
342 } else {
343
344 address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
345 MEMTXATTRS_UNSPECIFIED, NULL);
346 }
347}
348