1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include "qemu/osdep.h"
19#include "qemu/qemu-print.h"
20#include "cpu.h"
21#include "internal.h"
22#include "exec/exec-all.h"
23#include "qapi/error.h"
24#include "hw/qdev-properties.h"
25#include "fpu/softfloat-helpers.h"
26
27static void hexagon_v67_cpu_init(Object *obj)
28{
29}
30
31static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
32{
33 ObjectClass *oc;
34 char *typename;
35 char **cpuname;
36
37 cpuname = g_strsplit(cpu_model, ",", 1);
38 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]);
39 oc = object_class_by_name(typename);
40 g_strfreev(cpuname);
41 g_free(typename);
42 if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) ||
43 object_class_is_abstract(oc)) {
44 return NULL;
45 }
46 return oc;
47}
48
49static Property hexagon_lldb_compat_property =
50 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false);
51static Property hexagon_lldb_stack_adjust_property =
52 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
53 0, qdev_prop_uint32, target_ulong);
54
55const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
56 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
59 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
60 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1",
61 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15",
62 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23",
63 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31",
64};
65
66
67
68
69
70
71
72static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
73{
74 HexagonCPU *cpu = env_archcpu(env);
75 target_ulong stack_adjust = cpu->lldb_stack_adjust;
76 target_ulong stack_start = env->stack_start;
77 target_ulong stack_size = 0x10000;
78
79 if (stack_adjust == 0) {
80 return addr;
81 }
82
83 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) {
84 return addr - stack_adjust;
85 }
86 return addr;
87}
88
89
90static target_ulong read_p3_0(CPUHexagonState *env)
91{
92 int32_t control_reg = 0;
93 int i;
94 for (i = NUM_PREGS - 1; i >= 0; i--) {
95 control_reg <<= 8;
96 control_reg |= env->pred[i] & 0xff;
97 }
98 return control_reg;
99}
100
101static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
102{
103 target_ulong value;
104
105 if (regnum == HEX_REG_P3_0) {
106 value = read_p3_0(env);
107 } else {
108 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
109 : env->gpr[regnum];
110 }
111
112 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n",
113 hexagon_regnames[regnum], value);
114}
115
116static void print_vreg(FILE *f, CPUHexagonState *env, int regnum,
117 bool skip_if_zero)
118{
119 if (skip_if_zero) {
120 bool nonzero_found = false;
121 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) {
122 if (env->VRegs[regnum].ub[i] != 0) {
123 nonzero_found = true;
124 break;
125 }
126 }
127 if (!nonzero_found) {
128 return;
129 }
130 }
131
132 qemu_fprintf(f, " v%d = ( ", regnum);
133 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]);
134 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) {
135 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]);
136 }
137 qemu_fprintf(f, " )\n");
138}
139
140void hexagon_debug_vreg(CPUHexagonState *env, int regnum)
141{
142 print_vreg(stdout, env, regnum, false);
143}
144
145static void print_qreg(FILE *f, CPUHexagonState *env, int regnum,
146 bool skip_if_zero)
147{
148 if (skip_if_zero) {
149 bool nonzero_found = false;
150 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) {
151 if (env->QRegs[regnum].ub[i] != 0) {
152 nonzero_found = true;
153 break;
154 }
155 }
156 if (!nonzero_found) {
157 return;
158 }
159 }
160
161 qemu_fprintf(f, " q%d = ( ", regnum);
162 qemu_fprintf(f, "0x%02x",
163 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]);
164 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) {
165 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]);
166 }
167 qemu_fprintf(f, " )\n");
168}
169
170void hexagon_debug_qreg(CPUHexagonState *env, int regnum)
171{
172 print_qreg(stdout, env, regnum, false);
173}
174
175static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
176{
177 HexagonCPU *cpu = env_archcpu(env);
178
179 if (cpu->lldb_compat) {
180
181
182
183
184 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) {
185 return;
186 }
187 env->last_pc_dumped = env->gpr[HEX_REG_PC];
188 }
189
190 qemu_fprintf(f, "General Purpose Registers = {\n");
191 for (int i = 0; i < 32; i++) {
192 print_reg(f, env, i);
193 }
194 print_reg(f, env, HEX_REG_SA0);
195 print_reg(f, env, HEX_REG_LC0);
196 print_reg(f, env, HEX_REG_SA1);
197 print_reg(f, env, HEX_REG_LC1);
198 print_reg(f, env, HEX_REG_M0);
199 print_reg(f, env, HEX_REG_M1);
200 print_reg(f, env, HEX_REG_USR);
201 print_reg(f, env, HEX_REG_P3_0);
202 print_reg(f, env, HEX_REG_GP);
203 print_reg(f, env, HEX_REG_UGP);
204 print_reg(f, env, HEX_REG_PC);
205#ifdef CONFIG_USER_ONLY
206
207
208
209
210 qemu_fprintf(f, " cause = 0x000000db\n");
211 qemu_fprintf(f, " badva = 0x00000000\n");
212 qemu_fprintf(f, " cs0 = 0x00000000\n");
213 qemu_fprintf(f, " cs1 = 0x00000000\n");
214#else
215 print_reg(f, env, HEX_REG_CAUSE);
216 print_reg(f, env, HEX_REG_BADVA);
217 print_reg(f, env, HEX_REG_CS0);
218 print_reg(f, env, HEX_REG_CS1);
219#endif
220 qemu_fprintf(f, "}\n");
221
222 if (flags & CPU_DUMP_FPU) {
223 qemu_fprintf(f, "Vector Registers = {\n");
224 for (int i = 0; i < NUM_VREGS; i++) {
225 print_vreg(f, env, i, true);
226 }
227 for (int i = 0; i < NUM_QREGS; i++) {
228 print_qreg(f, env, i, true);
229 }
230 qemu_fprintf(f, "}\n");
231 }
232}
233
234static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
235{
236 HexagonCPU *cpu = HEXAGON_CPU(cs);
237 CPUHexagonState *env = &cpu->env;
238
239 hexagon_dump(env, f, flags);
240}
241
242void hexagon_debug(CPUHexagonState *env)
243{
244 hexagon_dump(env, stdout, CPU_DUMP_FPU);
245}
246
247static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
248{
249 HexagonCPU *cpu = HEXAGON_CPU(cs);
250 CPUHexagonState *env = &cpu->env;
251 env->gpr[HEX_REG_PC] = value;
252}
253
254static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
255 const TranslationBlock *tb)
256{
257 HexagonCPU *cpu = HEXAGON_CPU(cs);
258 CPUHexagonState *env = &cpu->env;
259 env->gpr[HEX_REG_PC] = tb->pc;
260}
261
262static bool hexagon_cpu_has_work(CPUState *cs)
263{
264 return true;
265}
266
267void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb,
268 target_ulong *data)
269{
270 env->gpr[HEX_REG_PC] = data[0];
271}
272
273static void hexagon_cpu_reset(DeviceState *dev)
274{
275 CPUState *cs = CPU(dev);
276 HexagonCPU *cpu = HEXAGON_CPU(cs);
277 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
278 CPUHexagonState *env = &cpu->env;
279
280 mcc->parent_reset(dev);
281
282 set_default_nan_mode(1, &env->fp_status);
283 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
284}
285
286static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
287{
288 info->print_insn = print_insn_hexagon;
289}
290
291static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
292{
293 CPUState *cs = CPU(dev);
294 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
295 Error *local_err = NULL;
296
297 cpu_exec_realizefn(cs, &local_err);
298 if (local_err != NULL) {
299 error_propagate(errp, local_err);
300 return;
301 }
302
303 qemu_init_vcpu(cs);
304 cpu_reset(cs);
305
306 mcc->parent_realize(dev, errp);
307}
308
309static void hexagon_cpu_init(Object *obj)
310{
311 HexagonCPU *cpu = HEXAGON_CPU(obj);
312
313 cpu_set_cpustate_pointers(cpu);
314 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
315 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
316}
317
318#include "hw/core/tcg-cpu-ops.h"
319
320static const struct TCGCPUOps hexagon_tcg_ops = {
321 .initialize = hexagon_translate_init,
322 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
323};
324
325static void hexagon_cpu_class_init(ObjectClass *c, void *data)
326{
327 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
328 CPUClass *cc = CPU_CLASS(c);
329 DeviceClass *dc = DEVICE_CLASS(c);
330
331 device_class_set_parent_realize(dc, hexagon_cpu_realize,
332 &mcc->parent_realize);
333
334 device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
335
336 cc->class_by_name = hexagon_cpu_class_by_name;
337 cc->has_work = hexagon_cpu_has_work;
338 cc->dump_state = hexagon_dump_state;
339 cc->set_pc = hexagon_cpu_set_pc;
340 cc->gdb_read_register = hexagon_gdb_read_register;
341 cc->gdb_write_register = hexagon_gdb_write_register;
342 cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
343 cc->gdb_stop_before_watchpoint = true;
344 cc->disas_set_info = hexagon_cpu_disas_set_info;
345 cc->tcg_ops = &hexagon_tcg_ops;
346}
347
348#define DEFINE_CPU(type_name, initfn) \
349 { \
350 .name = type_name, \
351 .parent = TYPE_HEXAGON_CPU, \
352 .instance_init = initfn \
353 }
354
355static const TypeInfo hexagon_cpu_type_infos[] = {
356 {
357 .name = TYPE_HEXAGON_CPU,
358 .parent = TYPE_CPU,
359 .instance_size = sizeof(HexagonCPU),
360 .instance_init = hexagon_cpu_init,
361 .abstract = true,
362 .class_size = sizeof(HexagonCPUClass),
363 .class_init = hexagon_cpu_class_init,
364 },
365 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
366};
367
368DEFINE_TYPES(hexagon_cpu_type_infos)
369
