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19#include "qemu/osdep.h"
20#include "cpu.h"
21#include "exec/exec-all.h"
22#include "../internal.h"
23
24static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
25{
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37
38
39 int32_t adetlb_mask;
40
41 switch (mmu_idx) {
42 case 3:
43
44 if (eu) {
45 return 0;
46 }
47
48 case MIPS_HFLAG_KM:
49
50 adetlb_mask = 0x70000000;
51 goto check_tlb;
52
53 case MIPS_HFLAG_SM:
54
55 adetlb_mask = 0xc0380000;
56 goto check_ade;
57
58 case MIPS_HFLAG_UM:
59
60 adetlb_mask = 0xe4180000;
61
62 check_ade:
63
64 if ((adetlb_mask << am) < 0) {
65 return TLBRET_BADADDR;
66 }
67 adetlb_mask <<= 8;
68
69 check_tlb:
70
71 return ((adetlb_mask << am) < 0);
72 default:
73 assert(0);
74 return TLBRET_BADADDR;
75 };
76}
77
78static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
79 int *prot, target_ulong real_address,
80 MMUAccessType access_type, int mmu_idx,
81 unsigned int am, bool eu,
82 target_ulong segmask,
83 hwaddr physical_base)
84{
85 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
86
87 if (mapped < 0) {
88
89 return mapped;
90 } else if (mapped) {
91
92 return env->tlb->map_address(env, physical, prot, real_address,
93 access_type);
94 } else {
95
96 *physical = physical_base | (real_address & segmask);
97 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
98 return TLBRET_MATCH;
99 }
100}
101
102static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
103 int *prot, target_ulong real_address,
104 MMUAccessType access_type, int mmu_idx,
105 uint16_t segctl, target_ulong segmask)
106{
107 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
108 bool eu = (segctl >> CP0SC_EU) & 1;
109 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
110
111 return get_seg_physical_address(env, physical, prot, real_address,
112 access_type, mmu_idx, am, eu, segmask,
113 pa & ~(hwaddr)segmask);
114}
115
116int get_physical_address(CPUMIPSState *env, hwaddr *physical,
117 int *prot, target_ulong real_address,
118 MMUAccessType access_type, int mmu_idx)
119{
120
121#if defined(TARGET_MIPS64)
122 int user_mode = mmu_idx == MIPS_HFLAG_UM;
123 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
124 int kernel_mode = !user_mode && !supervisor_mode;
125 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
126 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
127 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
128#endif
129 int ret = TLBRET_MATCH;
130
131 target_ulong address = real_address;
132
133 if (mips_um_ksegs_enabled()) {
134
135 if (real_address >= KVM_KSEG0_BASE) {
136 if (real_address < KVM_KSEG2_BASE) {
137
138 address += KSEG0_BASE - KVM_KSEG0_BASE;
139 } else if (real_address <= USEG_LIMIT) {
140
141 address += KSEG2_BASE - KVM_KSEG2_BASE;
142 }
143 }
144 }
145
146 if (address <= USEG_LIMIT) {
147
148 uint16_t segctl;
149
150 if (address >= 0x40000000UL) {
151 segctl = env->CP0_SegCtl2;
152 } else {
153 segctl = env->CP0_SegCtl2 >> 16;
154 }
155 ret = get_segctl_physical_address(env, physical, prot,
156 real_address, access_type,
157 mmu_idx, segctl, 0x3FFFFFFF);
158#if defined(TARGET_MIPS64)
159 } else if (address < 0x4000000000000000ULL) {
160
161 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
162 ret = env->tlb->map_address(env, physical, prot,
163 real_address, access_type);
164 } else {
165 ret = TLBRET_BADADDR;
166 }
167 } else if (address < 0x8000000000000000ULL) {
168
169 if ((supervisor_mode || kernel_mode) &&
170 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
171 ret = env->tlb->map_address(env, physical, prot,
172 real_address, access_type);
173 } else {
174 ret = TLBRET_BADADDR;
175 }
176 } else if (address < 0xC000000000000000ULL) {
177
178 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
179
180 static const uint8_t am_ksux[8] = {
181 [CP0SC_AM_UK] = (1u << CP0St_KX),
182 [CP0SC_AM_MK] = (1u << CP0St_KX),
183 [CP0SC_AM_MSK] = (1u << CP0St_SX),
184 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
185 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
186 [CP0SC_AM_USK] = (1u << CP0St_SX),
187 [6] = (1u << CP0St_KX),
188 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
189 };
190 unsigned int am = CP0SC_AM_UK;
191 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
192
193 if (xr & (1 << ((address >> 59) & 0x7))) {
194 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
195 }
196
197 if (env->CP0_Status & am_ksux[am]) {
198 ret = get_seg_physical_address(env, physical, prot,
199 real_address, access_type,
200 mmu_idx, am, false, env->PAMask,
201 0);
202 } else {
203 ret = TLBRET_BADADDR;
204 }
205 } else {
206 ret = TLBRET_BADADDR;
207 }
208 } else if (address < 0xFFFFFFFF80000000ULL) {
209
210 if (kernel_mode && KX &&
211 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
212 ret = env->tlb->map_address(env, physical, prot,
213 real_address, access_type);
214 } else {
215 ret = TLBRET_BADADDR;
216 }
217#endif
218 } else if (address < KSEG1_BASE) {
219
220 ret = get_segctl_physical_address(env, physical, prot, real_address,
221 access_type, mmu_idx,
222 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
223 } else if (address < KSEG2_BASE) {
224
225 ret = get_segctl_physical_address(env, physical, prot, real_address,
226 access_type, mmu_idx,
227 env->CP0_SegCtl1, 0x1FFFFFFF);
228 } else if (address < KSEG3_BASE) {
229
230 ret = get_segctl_physical_address(env, physical, prot, real_address,
231 access_type, mmu_idx,
232 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
233 } else {
234
235
236
237
238 ret = get_segctl_physical_address(env, physical, prot, real_address,
239 access_type, mmu_idx,
240 env->CP0_SegCtl0, 0x1FFFFFFF);
241 }
242 return ret;
243}
244
245hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
246{
247 MIPSCPU *cpu = MIPS_CPU(cs);
248 CPUMIPSState *env = &cpu->env;
249 hwaddr phys_addr;
250 int prot;
251
252 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
253 cpu_mmu_index(env, false)) != 0) {
254 return -1;
255 }
256 return phys_addr;
257}
258