qemu/target/mips/translate.c
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   1/*
   2 *  MIPS emulation for QEMU - main translation routines
   3 *
   4 *  Copyright (c) 2004-2005 Jocelyn Mayer
   5 *  Copyright (c) 2006 Marius Groeger (FPU operations)
   6 *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
   7 *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
   8 *  Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
   9 *
  10 * This library is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU Lesser General Public
  12 * License as published by the Free Software Foundation; either
  13 * version 2 of the License, or (at your option) any later version.
  14 *
  15 * This library is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18 * Lesser General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU Lesser General Public
  21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  22 */
  23
  24#include "qemu/osdep.h"
  25#include "cpu.h"
  26#include "internal.h"
  27#include "disas/disas.h"
  28#include "exec/exec-all.h"
  29#include "tcg-op.h"
  30#include "exec/cpu_ldst.h"
  31#include "hw/mips/cpudevs.h"
  32
  33#include "exec/helper-proto.h"
  34#include "exec/helper-gen.h"
  35#include "hw/semihosting/semihost.h"
  36
  37#include "target/mips/trace.h"
  38#include "trace-tcg.h"
  39#include "exec/translator.h"
  40#include "exec/log.h"
  41#include "qemu/qemu-print.h"
  42
  43#define MIPS_DEBUG_DISAS 0
  44
  45/* MIPS major opcodes */
  46#define MASK_OP_MAJOR(op)       (op & (0x3F << 26))
  47
  48enum {
  49    /* indirect opcode tables */
  50    OPC_SPECIAL  = (0x00 << 26),
  51    OPC_REGIMM   = (0x01 << 26),
  52    OPC_CP0      = (0x10 << 26),
  53    OPC_CP1      = (0x11 << 26),
  54    OPC_CP2      = (0x12 << 26),
  55    OPC_CP3      = (0x13 << 26),
  56    OPC_SPECIAL2 = (0x1C << 26),
  57    OPC_SPECIAL3 = (0x1F << 26),
  58    /* arithmetic with immediate */
  59    OPC_ADDI     = (0x08 << 26),
  60    OPC_ADDIU    = (0x09 << 26),
  61    OPC_SLTI     = (0x0A << 26),
  62    OPC_SLTIU    = (0x0B << 26),
  63    /* logic with immediate */
  64    OPC_ANDI     = (0x0C << 26),
  65    OPC_ORI      = (0x0D << 26),
  66    OPC_XORI     = (0x0E << 26),
  67    OPC_LUI      = (0x0F << 26),
  68    /* arithmetic with immediate */
  69    OPC_DADDI    = (0x18 << 26),
  70    OPC_DADDIU   = (0x19 << 26),
  71    /* Jump and branches */
  72    OPC_J        = (0x02 << 26),
  73    OPC_JAL      = (0x03 << 26),
  74    OPC_BEQ      = (0x04 << 26),  /* Unconditional if rs = rt = 0 (B) */
  75    OPC_BEQL     = (0x14 << 26),
  76    OPC_BNE      = (0x05 << 26),
  77    OPC_BNEL     = (0x15 << 26),
  78    OPC_BLEZ     = (0x06 << 26),
  79    OPC_BLEZL    = (0x16 << 26),
  80    OPC_BGTZ     = (0x07 << 26),
  81    OPC_BGTZL    = (0x17 << 26),
  82    OPC_JALX     = (0x1D << 26),
  83    OPC_DAUI     = (0x1D << 26),
  84    /* Load and stores */
  85    OPC_LDL      = (0x1A << 26),
  86    OPC_LDR      = (0x1B << 26),
  87    OPC_LB       = (0x20 << 26),
  88    OPC_LH       = (0x21 << 26),
  89    OPC_LWL      = (0x22 << 26),
  90    OPC_LW       = (0x23 << 26),
  91    OPC_LWPC     = OPC_LW | 0x5,
  92    OPC_LBU      = (0x24 << 26),
  93    OPC_LHU      = (0x25 << 26),
  94    OPC_LWR      = (0x26 << 26),
  95    OPC_LWU      = (0x27 << 26),
  96    OPC_SB       = (0x28 << 26),
  97    OPC_SH       = (0x29 << 26),
  98    OPC_SWL      = (0x2A << 26),
  99    OPC_SW       = (0x2B << 26),
 100    OPC_SDL      = (0x2C << 26),
 101    OPC_SDR      = (0x2D << 26),
 102    OPC_SWR      = (0x2E << 26),
 103    OPC_LL       = (0x30 << 26),
 104    OPC_LLD      = (0x34 << 26),
 105    OPC_LD       = (0x37 << 26),
 106    OPC_LDPC     = OPC_LD | 0x5,
 107    OPC_SC       = (0x38 << 26),
 108    OPC_SCD      = (0x3C << 26),
 109    OPC_SD       = (0x3F << 26),
 110    /* Floating point load/store */
 111    OPC_LWC1     = (0x31 << 26),
 112    OPC_LWC2     = (0x32 << 26),
 113    OPC_LDC1     = (0x35 << 26),
 114    OPC_LDC2     = (0x36 << 26),
 115    OPC_SWC1     = (0x39 << 26),
 116    OPC_SWC2     = (0x3A << 26),
 117    OPC_SDC1     = (0x3D << 26),
 118    OPC_SDC2     = (0x3E << 26),
 119    /* Compact Branches */
 120    OPC_BLEZALC  = (0x06 << 26),
 121    OPC_BGEZALC  = (0x06 << 26),
 122    OPC_BGEUC    = (0x06 << 26),
 123    OPC_BGTZALC  = (0x07 << 26),
 124    OPC_BLTZALC  = (0x07 << 26),
 125    OPC_BLTUC    = (0x07 << 26),
 126    OPC_BOVC     = (0x08 << 26),
 127    OPC_BEQZALC  = (0x08 << 26),
 128    OPC_BEQC     = (0x08 << 26),
 129    OPC_BLEZC    = (0x16 << 26),
 130    OPC_BGEZC    = (0x16 << 26),
 131    OPC_BGEC     = (0x16 << 26),
 132    OPC_BGTZC    = (0x17 << 26),
 133    OPC_BLTZC    = (0x17 << 26),
 134    OPC_BLTC     = (0x17 << 26),
 135    OPC_BNVC     = (0x18 << 26),
 136    OPC_BNEZALC  = (0x18 << 26),
 137    OPC_BNEC     = (0x18 << 26),
 138    OPC_BC       = (0x32 << 26),
 139    OPC_BEQZC    = (0x36 << 26),
 140    OPC_JIC      = (0x36 << 26),
 141    OPC_BALC     = (0x3A << 26),
 142    OPC_BNEZC    = (0x3E << 26),
 143    OPC_JIALC    = (0x3E << 26),
 144    /* MDMX ASE specific */
 145    OPC_MDMX     = (0x1E << 26),
 146    /* MSA ASE, same as MDMX */
 147    OPC_MSA      = OPC_MDMX,
 148    /* Cache and prefetch */
 149    OPC_CACHE    = (0x2F << 26),
 150    OPC_PREF     = (0x33 << 26),
 151    /* PC-relative address computation / loads */
 152    OPC_PCREL    = (0x3B << 26),
 153};
 154
 155/* PC-relative address computation / loads  */
 156#define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
 157#define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
 158enum {
 159    /* Instructions determined by bits 19 and 20 */
 160    OPC_ADDIUPC = OPC_PCREL | (0 << 19),
 161    R6_OPC_LWPC = OPC_PCREL | (1 << 19),
 162    OPC_LWUPC   = OPC_PCREL | (2 << 19),
 163
 164    /* Instructions determined by bits 16 ... 20 */
 165    OPC_AUIPC   = OPC_PCREL | (0x1e << 16),
 166    OPC_ALUIPC  = OPC_PCREL | (0x1f << 16),
 167
 168    /* Other */
 169    R6_OPC_LDPC = OPC_PCREL | (6 << 18),
 170};
 171
 172/* MIPS special opcodes */
 173#define MASK_SPECIAL(op)            (MASK_OP_MAJOR(op) | (op & 0x3F))
 174
 175enum {
 176    /* Shifts */
 177    OPC_SLL      = 0x00 | OPC_SPECIAL,
 178    /* NOP is SLL r0, r0, 0   */
 179    /* SSNOP is SLL r0, r0, 1 */
 180    /* EHB is SLL r0, r0, 3 */
 181    OPC_SRL      = 0x02 | OPC_SPECIAL, /* also ROTR */
 182    OPC_ROTR     = OPC_SRL | (1 << 21),
 183    OPC_SRA      = 0x03 | OPC_SPECIAL,
 184    OPC_SLLV     = 0x04 | OPC_SPECIAL,
 185    OPC_SRLV     = 0x06 | OPC_SPECIAL, /* also ROTRV */
 186    OPC_ROTRV    = OPC_SRLV | (1 << 6),
 187    OPC_SRAV     = 0x07 | OPC_SPECIAL,
 188    OPC_DSLLV    = 0x14 | OPC_SPECIAL,
 189    OPC_DSRLV    = 0x16 | OPC_SPECIAL, /* also DROTRV */
 190    OPC_DROTRV   = OPC_DSRLV | (1 << 6),
 191    OPC_DSRAV    = 0x17 | OPC_SPECIAL,
 192    OPC_DSLL     = 0x38 | OPC_SPECIAL,
 193    OPC_DSRL     = 0x3A | OPC_SPECIAL, /* also DROTR */
 194    OPC_DROTR    = OPC_DSRL | (1 << 21),
 195    OPC_DSRA     = 0x3B | OPC_SPECIAL,
 196    OPC_DSLL32   = 0x3C | OPC_SPECIAL,
 197    OPC_DSRL32   = 0x3E | OPC_SPECIAL, /* also DROTR32 */
 198    OPC_DROTR32  = OPC_DSRL32 | (1 << 21),
 199    OPC_DSRA32   = 0x3F | OPC_SPECIAL,
 200    /* Multiplication / division */
 201    OPC_MULT     = 0x18 | OPC_SPECIAL,
 202    OPC_MULTU    = 0x19 | OPC_SPECIAL,
 203    OPC_DIV      = 0x1A | OPC_SPECIAL,
 204    OPC_DIVU     = 0x1B | OPC_SPECIAL,
 205    OPC_DMULT    = 0x1C | OPC_SPECIAL,
 206    OPC_DMULTU   = 0x1D | OPC_SPECIAL,
 207    OPC_DDIV     = 0x1E | OPC_SPECIAL,
 208    OPC_DDIVU    = 0x1F | OPC_SPECIAL,
 209
 210    /* 2 registers arithmetic / logic */
 211    OPC_ADD      = 0x20 | OPC_SPECIAL,
 212    OPC_ADDU     = 0x21 | OPC_SPECIAL,
 213    OPC_SUB      = 0x22 | OPC_SPECIAL,
 214    OPC_SUBU     = 0x23 | OPC_SPECIAL,
 215    OPC_AND      = 0x24 | OPC_SPECIAL,
 216    OPC_OR       = 0x25 | OPC_SPECIAL,
 217    OPC_XOR      = 0x26 | OPC_SPECIAL,
 218    OPC_NOR      = 0x27 | OPC_SPECIAL,
 219    OPC_SLT      = 0x2A | OPC_SPECIAL,
 220    OPC_SLTU     = 0x2B | OPC_SPECIAL,
 221    OPC_DADD     = 0x2C | OPC_SPECIAL,
 222    OPC_DADDU    = 0x2D | OPC_SPECIAL,
 223    OPC_DSUB     = 0x2E | OPC_SPECIAL,
 224    OPC_DSUBU    = 0x2F | OPC_SPECIAL,
 225    /* Jumps */
 226    OPC_JR       = 0x08 | OPC_SPECIAL, /* Also JR.HB */
 227    OPC_JALR     = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
 228    /* Traps */
 229    OPC_TGE      = 0x30 | OPC_SPECIAL,
 230    OPC_TGEU     = 0x31 | OPC_SPECIAL,
 231    OPC_TLT      = 0x32 | OPC_SPECIAL,
 232    OPC_TLTU     = 0x33 | OPC_SPECIAL,
 233    OPC_TEQ      = 0x34 | OPC_SPECIAL,
 234    OPC_TNE      = 0x36 | OPC_SPECIAL,
 235    /* HI / LO registers load & stores */
 236    OPC_MFHI     = 0x10 | OPC_SPECIAL,
 237    OPC_MTHI     = 0x11 | OPC_SPECIAL,
 238    OPC_MFLO     = 0x12 | OPC_SPECIAL,
 239    OPC_MTLO     = 0x13 | OPC_SPECIAL,
 240    /* Conditional moves */
 241    OPC_MOVZ     = 0x0A | OPC_SPECIAL,
 242    OPC_MOVN     = 0x0B | OPC_SPECIAL,
 243
 244    OPC_SELEQZ   = 0x35 | OPC_SPECIAL,
 245    OPC_SELNEZ   = 0x37 | OPC_SPECIAL,
 246
 247    OPC_MOVCI    = 0x01 | OPC_SPECIAL,
 248
 249    /* Special */
 250    OPC_PMON     = 0x05 | OPC_SPECIAL, /* unofficial */
 251    OPC_SYSCALL  = 0x0C | OPC_SPECIAL,
 252    OPC_BREAK    = 0x0D | OPC_SPECIAL,
 253    OPC_SPIM     = 0x0E | OPC_SPECIAL, /* unofficial */
 254    OPC_SYNC     = 0x0F | OPC_SPECIAL,
 255
 256    OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
 257    OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
 258    OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
 259    OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
 260};
 261
 262/*
 263 * R6 Multiply and Divide instructions have the same opcode
 264 * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
 265 */
 266#define MASK_R6_MULDIV(op)          (MASK_SPECIAL(op) | (op & (0x7ff)))
 267
 268enum {
 269    R6_OPC_MUL   = OPC_MULT  | (2 << 6),
 270    R6_OPC_MUH   = OPC_MULT  | (3 << 6),
 271    R6_OPC_MULU  = OPC_MULTU | (2 << 6),
 272    R6_OPC_MUHU  = OPC_MULTU | (3 << 6),
 273    R6_OPC_DIV   = OPC_DIV   | (2 << 6),
 274    R6_OPC_MOD   = OPC_DIV   | (3 << 6),
 275    R6_OPC_DIVU  = OPC_DIVU  | (2 << 6),
 276    R6_OPC_MODU  = OPC_DIVU  | (3 << 6),
 277
 278    R6_OPC_DMUL   = OPC_DMULT  | (2 << 6),
 279    R6_OPC_DMUH   = OPC_DMULT  | (3 << 6),
 280    R6_OPC_DMULU  = OPC_DMULTU | (2 << 6),
 281    R6_OPC_DMUHU  = OPC_DMULTU | (3 << 6),
 282    R6_OPC_DDIV   = OPC_DDIV   | (2 << 6),
 283    R6_OPC_DMOD   = OPC_DDIV   | (3 << 6),
 284    R6_OPC_DDIVU  = OPC_DDIVU  | (2 << 6),
 285    R6_OPC_DMODU  = OPC_DDIVU  | (3 << 6),
 286
 287    R6_OPC_CLZ      = 0x10 | OPC_SPECIAL,
 288    R6_OPC_CLO      = 0x11 | OPC_SPECIAL,
 289    R6_OPC_DCLZ     = 0x12 | OPC_SPECIAL,
 290    R6_OPC_DCLO     = 0x13 | OPC_SPECIAL,
 291    R6_OPC_SDBBP    = 0x0e | OPC_SPECIAL,
 292
 293    OPC_LSA  = 0x05 | OPC_SPECIAL,
 294    OPC_DLSA = 0x15 | OPC_SPECIAL,
 295};
 296
 297/* Multiplication variants of the vr54xx. */
 298#define MASK_MUL_VR54XX(op)         (MASK_SPECIAL(op) | (op & (0x1F << 6)))
 299
 300enum {
 301    OPC_VR54XX_MULS    = (0x03 << 6) | OPC_MULT,
 302    OPC_VR54XX_MULSU   = (0x03 << 6) | OPC_MULTU,
 303    OPC_VR54XX_MACC    = (0x05 << 6) | OPC_MULT,
 304    OPC_VR54XX_MACCU   = (0x05 << 6) | OPC_MULTU,
 305    OPC_VR54XX_MSAC    = (0x07 << 6) | OPC_MULT,
 306    OPC_VR54XX_MSACU   = (0x07 << 6) | OPC_MULTU,
 307    OPC_VR54XX_MULHI   = (0x09 << 6) | OPC_MULT,
 308    OPC_VR54XX_MULHIU  = (0x09 << 6) | OPC_MULTU,
 309    OPC_VR54XX_MULSHI  = (0x0B << 6) | OPC_MULT,
 310    OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
 311    OPC_VR54XX_MACCHI  = (0x0D << 6) | OPC_MULT,
 312    OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
 313    OPC_VR54XX_MSACHI  = (0x0F << 6) | OPC_MULT,
 314    OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
 315};
 316
 317/* REGIMM (rt field) opcodes */
 318#define MASK_REGIMM(op)             (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
 319
 320enum {
 321    OPC_BLTZ     = (0x00 << 16) | OPC_REGIMM,
 322    OPC_BLTZL    = (0x02 << 16) | OPC_REGIMM,
 323    OPC_BGEZ     = (0x01 << 16) | OPC_REGIMM,
 324    OPC_BGEZL    = (0x03 << 16) | OPC_REGIMM,
 325    OPC_BLTZAL   = (0x10 << 16) | OPC_REGIMM,
 326    OPC_BLTZALL  = (0x12 << 16) | OPC_REGIMM,
 327    OPC_BGEZAL   = (0x11 << 16) | OPC_REGIMM,
 328    OPC_BGEZALL  = (0x13 << 16) | OPC_REGIMM,
 329    OPC_TGEI     = (0x08 << 16) | OPC_REGIMM,
 330    OPC_TGEIU    = (0x09 << 16) | OPC_REGIMM,
 331    OPC_TLTI     = (0x0A << 16) | OPC_REGIMM,
 332    OPC_TLTIU    = (0x0B << 16) | OPC_REGIMM,
 333    OPC_TEQI     = (0x0C << 16) | OPC_REGIMM,
 334    OPC_TNEI     = (0x0E << 16) | OPC_REGIMM,
 335    OPC_SIGRIE   = (0x17 << 16) | OPC_REGIMM,
 336    OPC_SYNCI    = (0x1F << 16) | OPC_REGIMM,
 337
 338    OPC_DAHI     = (0x06 << 16) | OPC_REGIMM,
 339    OPC_DATI     = (0x1e << 16) | OPC_REGIMM,
 340};
 341
 342/* Special2 opcodes */
 343#define MASK_SPECIAL2(op)           (MASK_OP_MAJOR(op) | (op & 0x3F))
 344
 345enum {
 346    /* Multiply & xxx operations */
 347    OPC_MADD     = 0x00 | OPC_SPECIAL2,
 348    OPC_MADDU    = 0x01 | OPC_SPECIAL2,
 349    OPC_MUL      = 0x02 | OPC_SPECIAL2,
 350    OPC_MSUB     = 0x04 | OPC_SPECIAL2,
 351    OPC_MSUBU    = 0x05 | OPC_SPECIAL2,
 352    /* Loongson 2F */
 353    OPC_MULT_G_2F   = 0x10 | OPC_SPECIAL2,
 354    OPC_DMULT_G_2F  = 0x11 | OPC_SPECIAL2,
 355    OPC_MULTU_G_2F  = 0x12 | OPC_SPECIAL2,
 356    OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
 357    OPC_DIV_G_2F    = 0x14 | OPC_SPECIAL2,
 358    OPC_DDIV_G_2F   = 0x15 | OPC_SPECIAL2,
 359    OPC_DIVU_G_2F   = 0x16 | OPC_SPECIAL2,
 360    OPC_DDIVU_G_2F  = 0x17 | OPC_SPECIAL2,
 361    OPC_MOD_G_2F    = 0x1c | OPC_SPECIAL2,
 362    OPC_DMOD_G_2F   = 0x1d | OPC_SPECIAL2,
 363    OPC_MODU_G_2F   = 0x1e | OPC_SPECIAL2,
 364    OPC_DMODU_G_2F  = 0x1f | OPC_SPECIAL2,
 365    /* Misc */
 366    OPC_CLZ      = 0x20 | OPC_SPECIAL2,
 367    OPC_CLO      = 0x21 | OPC_SPECIAL2,
 368    OPC_DCLZ     = 0x24 | OPC_SPECIAL2,
 369    OPC_DCLO     = 0x25 | OPC_SPECIAL2,
 370    /* Special */
 371    OPC_SDBBP    = 0x3F | OPC_SPECIAL2,
 372};
 373
 374/* Special3 opcodes */
 375#define MASK_SPECIAL3(op)           (MASK_OP_MAJOR(op) | (op & 0x3F))
 376
 377enum {
 378    OPC_EXT      = 0x00 | OPC_SPECIAL3,
 379    OPC_DEXTM    = 0x01 | OPC_SPECIAL3,
 380    OPC_DEXTU    = 0x02 | OPC_SPECIAL3,
 381    OPC_DEXT     = 0x03 | OPC_SPECIAL3,
 382    OPC_INS      = 0x04 | OPC_SPECIAL3,
 383    OPC_DINSM    = 0x05 | OPC_SPECIAL3,
 384    OPC_DINSU    = 0x06 | OPC_SPECIAL3,
 385    OPC_DINS     = 0x07 | OPC_SPECIAL3,
 386    OPC_FORK     = 0x08 | OPC_SPECIAL3,
 387    OPC_YIELD    = 0x09 | OPC_SPECIAL3,
 388    OPC_BSHFL    = 0x20 | OPC_SPECIAL3,
 389    OPC_DBSHFL   = 0x24 | OPC_SPECIAL3,
 390    OPC_RDHWR    = 0x3B | OPC_SPECIAL3,
 391
 392    /* Loongson 2E */
 393    OPC_MULT_G_2E   = 0x18 | OPC_SPECIAL3,
 394    OPC_MULTU_G_2E  = 0x19 | OPC_SPECIAL3,
 395    OPC_DIV_G_2E    = 0x1A | OPC_SPECIAL3,
 396    OPC_DIVU_G_2E   = 0x1B | OPC_SPECIAL3,
 397    OPC_DMULT_G_2E  = 0x1C | OPC_SPECIAL3,
 398    OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
 399    OPC_DDIV_G_2E   = 0x1E | OPC_SPECIAL3,
 400    OPC_DDIVU_G_2E  = 0x1F | OPC_SPECIAL3,
 401    OPC_MOD_G_2E    = 0x22 | OPC_SPECIAL3,
 402    OPC_MODU_G_2E   = 0x23 | OPC_SPECIAL3,
 403    OPC_DMOD_G_2E   = 0x26 | OPC_SPECIAL3,
 404    OPC_DMODU_G_2E  = 0x27 | OPC_SPECIAL3,
 405
 406    /* MIPS DSP Load */
 407    OPC_LX_DSP         = 0x0A | OPC_SPECIAL3,
 408    /* MIPS DSP Arithmetic */
 409    OPC_ADDU_QB_DSP    = 0x10 | OPC_SPECIAL3,
 410    OPC_ADDU_OB_DSP    = 0x14 | OPC_SPECIAL3,
 411    OPC_ABSQ_S_PH_DSP  = 0x12 | OPC_SPECIAL3,
 412    OPC_ABSQ_S_QH_DSP  = 0x16 | OPC_SPECIAL3,
 413    /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E.  */
 414    /* OPC_ADDUH_QB_DSP   = 0x18 | OPC_SPECIAL3,  */
 415    OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
 416    OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
 417    /* MIPS DSP GPR-Based Shift Sub-class */
 418    OPC_SHLL_QB_DSP    = 0x13 | OPC_SPECIAL3,
 419    OPC_SHLL_OB_DSP    = 0x17 | OPC_SPECIAL3,
 420    /* MIPS DSP Multiply Sub-class insns */
 421    /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP.  */
 422    /* OPC_MUL_PH_DSP     = 0x18 | OPC_SPECIAL3,  */
 423    OPC_DPA_W_PH_DSP   = 0x30 | OPC_SPECIAL3,
 424    OPC_DPAQ_W_QH_DSP  = 0x34 | OPC_SPECIAL3,
 425    /* DSP Bit/Manipulation Sub-class */
 426    OPC_INSV_DSP       = 0x0C | OPC_SPECIAL3,
 427    OPC_DINSV_DSP      = 0x0D | OPC_SPECIAL3,
 428    /* MIPS DSP Append Sub-class */
 429    OPC_APPEND_DSP     = 0x31 | OPC_SPECIAL3,
 430    OPC_DAPPEND_DSP    = 0x35 | OPC_SPECIAL3,
 431    /* MIPS DSP Accumulator and DSPControl Access Sub-class */
 432    OPC_EXTR_W_DSP     = 0x38 | OPC_SPECIAL3,
 433    OPC_DEXTR_W_DSP    = 0x3C | OPC_SPECIAL3,
 434
 435    /* EVA */
 436    OPC_LWLE           = 0x19 | OPC_SPECIAL3,
 437    OPC_LWRE           = 0x1A | OPC_SPECIAL3,
 438    OPC_CACHEE         = 0x1B | OPC_SPECIAL3,
 439    OPC_SBE            = 0x1C | OPC_SPECIAL3,
 440    OPC_SHE            = 0x1D | OPC_SPECIAL3,
 441    OPC_SCE            = 0x1E | OPC_SPECIAL3,
 442    OPC_SWE            = 0x1F | OPC_SPECIAL3,
 443    OPC_SWLE           = 0x21 | OPC_SPECIAL3,
 444    OPC_SWRE           = 0x22 | OPC_SPECIAL3,
 445    OPC_PREFE          = 0x23 | OPC_SPECIAL3,
 446    OPC_LBUE           = 0x28 | OPC_SPECIAL3,
 447    OPC_LHUE           = 0x29 | OPC_SPECIAL3,
 448    OPC_LBE            = 0x2C | OPC_SPECIAL3,
 449    OPC_LHE            = 0x2D | OPC_SPECIAL3,
 450    OPC_LLE            = 0x2E | OPC_SPECIAL3,
 451    OPC_LWE            = 0x2F | OPC_SPECIAL3,
 452
 453    /* R6 */
 454    R6_OPC_PREF        = 0x35 | OPC_SPECIAL3,
 455    R6_OPC_CACHE       = 0x25 | OPC_SPECIAL3,
 456    R6_OPC_LL          = 0x36 | OPC_SPECIAL3,
 457    R6_OPC_SC          = 0x26 | OPC_SPECIAL3,
 458    R6_OPC_LLD         = 0x37 | OPC_SPECIAL3,
 459    R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
 460};
 461
 462/* BSHFL opcodes */
 463#define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 464
 465enum {
 466    OPC_WSBH      = (0x02 << 6) | OPC_BSHFL,
 467    OPC_SEB       = (0x10 << 6) | OPC_BSHFL,
 468    OPC_SEH       = (0x18 << 6) | OPC_BSHFL,
 469    OPC_ALIGN     = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
 470    OPC_ALIGN_1   = (0x09 << 6) | OPC_BSHFL,
 471    OPC_ALIGN_2   = (0x0A << 6) | OPC_BSHFL,
 472    OPC_ALIGN_3   = (0x0B << 6) | OPC_BSHFL,
 473    OPC_BITSWAP   = (0x00 << 6) | OPC_BSHFL  /* 00000 */
 474};
 475
 476/* DBSHFL opcodes */
 477#define MASK_DBSHFL(op)             (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 478
 479enum {
 480    OPC_DSBH       = (0x02 << 6) | OPC_DBSHFL,
 481    OPC_DSHD       = (0x05 << 6) | OPC_DBSHFL,
 482    OPC_DALIGN     = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
 483    OPC_DALIGN_1   = (0x09 << 6) | OPC_DBSHFL,
 484    OPC_DALIGN_2   = (0x0A << 6) | OPC_DBSHFL,
 485    OPC_DALIGN_3   = (0x0B << 6) | OPC_DBSHFL,
 486    OPC_DALIGN_4   = (0x0C << 6) | OPC_DBSHFL,
 487    OPC_DALIGN_5   = (0x0D << 6) | OPC_DBSHFL,
 488    OPC_DALIGN_6   = (0x0E << 6) | OPC_DBSHFL,
 489    OPC_DALIGN_7   = (0x0F << 6) | OPC_DBSHFL,
 490    OPC_DBITSWAP   = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
 491};
 492
 493/* MIPS DSP REGIMM opcodes */
 494enum {
 495    OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
 496    OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
 497};
 498
 499#define MASK_LX(op)                 (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 500/* MIPS DSP Load */
 501enum {
 502    OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
 503    OPC_LHX  = (0x04 << 6) | OPC_LX_DSP,
 504    OPC_LWX  = (0x00 << 6) | OPC_LX_DSP,
 505    OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
 506};
 507
 508#define MASK_ADDU_QB(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 509enum {
 510    /* MIPS DSP Arithmetic Sub-class */
 511    OPC_ADDQ_PH        = (0x0A << 6) | OPC_ADDU_QB_DSP,
 512    OPC_ADDQ_S_PH      = (0x0E << 6) | OPC_ADDU_QB_DSP,
 513    OPC_ADDQ_S_W       = (0x16 << 6) | OPC_ADDU_QB_DSP,
 514    OPC_ADDU_QB        = (0x00 << 6) | OPC_ADDU_QB_DSP,
 515    OPC_ADDU_S_QB      = (0x04 << 6) | OPC_ADDU_QB_DSP,
 516    OPC_ADDU_PH        = (0x08 << 6) | OPC_ADDU_QB_DSP,
 517    OPC_ADDU_S_PH      = (0x0C << 6) | OPC_ADDU_QB_DSP,
 518    OPC_SUBQ_PH        = (0x0B << 6) | OPC_ADDU_QB_DSP,
 519    OPC_SUBQ_S_PH      = (0x0F << 6) | OPC_ADDU_QB_DSP,
 520    OPC_SUBQ_S_W       = (0x17 << 6) | OPC_ADDU_QB_DSP,
 521    OPC_SUBU_QB        = (0x01 << 6) | OPC_ADDU_QB_DSP,
 522    OPC_SUBU_S_QB      = (0x05 << 6) | OPC_ADDU_QB_DSP,
 523    OPC_SUBU_PH        = (0x09 << 6) | OPC_ADDU_QB_DSP,
 524    OPC_SUBU_S_PH      = (0x0D << 6) | OPC_ADDU_QB_DSP,
 525    OPC_ADDSC          = (0x10 << 6) | OPC_ADDU_QB_DSP,
 526    OPC_ADDWC          = (0x11 << 6) | OPC_ADDU_QB_DSP,
 527    OPC_MODSUB         = (0x12 << 6) | OPC_ADDU_QB_DSP,
 528    OPC_RADDU_W_QB     = (0x14 << 6) | OPC_ADDU_QB_DSP,
 529    /* MIPS DSP Multiply Sub-class insns */
 530    OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
 531    OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
 532    OPC_MULQ_RS_PH     = (0x1F << 6) | OPC_ADDU_QB_DSP,
 533    OPC_MULEQ_S_W_PHL  = (0x1C << 6) | OPC_ADDU_QB_DSP,
 534    OPC_MULEQ_S_W_PHR  = (0x1D << 6) | OPC_ADDU_QB_DSP,
 535    OPC_MULQ_S_PH      = (0x1E << 6) | OPC_ADDU_QB_DSP,
 536};
 537
 538#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
 539#define MASK_ADDUH_QB(op)           (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 540enum {
 541    /* MIPS DSP Arithmetic Sub-class */
 542    OPC_ADDUH_QB   = (0x00 << 6) | OPC_ADDUH_QB_DSP,
 543    OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
 544    OPC_ADDQH_PH   = (0x08 << 6) | OPC_ADDUH_QB_DSP,
 545    OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
 546    OPC_ADDQH_W    = (0x10 << 6) | OPC_ADDUH_QB_DSP,
 547    OPC_ADDQH_R_W  = (0x12 << 6) | OPC_ADDUH_QB_DSP,
 548    OPC_SUBUH_QB   = (0x01 << 6) | OPC_ADDUH_QB_DSP,
 549    OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
 550    OPC_SUBQH_PH   = (0x09 << 6) | OPC_ADDUH_QB_DSP,
 551    OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
 552    OPC_SUBQH_W    = (0x11 << 6) | OPC_ADDUH_QB_DSP,
 553    OPC_SUBQH_R_W  = (0x13 << 6) | OPC_ADDUH_QB_DSP,
 554    /* MIPS DSP Multiply Sub-class insns */
 555    OPC_MUL_PH     = (0x0C << 6) | OPC_ADDUH_QB_DSP,
 556    OPC_MUL_S_PH   = (0x0E << 6) | OPC_ADDUH_QB_DSP,
 557    OPC_MULQ_S_W   = (0x16 << 6) | OPC_ADDUH_QB_DSP,
 558    OPC_MULQ_RS_W  = (0x17 << 6) | OPC_ADDUH_QB_DSP,
 559};
 560
 561#define MASK_ABSQ_S_PH(op)          (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 562enum {
 563    /* MIPS DSP Arithmetic Sub-class */
 564    OPC_ABSQ_S_QB       = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
 565    OPC_ABSQ_S_PH       = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
 566    OPC_ABSQ_S_W        = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
 567    OPC_PRECEQ_W_PHL    = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
 568    OPC_PRECEQ_W_PHR    = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
 569    OPC_PRECEQU_PH_QBL  = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
 570    OPC_PRECEQU_PH_QBR  = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
 571    OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
 572    OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
 573    OPC_PRECEU_PH_QBL   = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
 574    OPC_PRECEU_PH_QBR   = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
 575    OPC_PRECEU_PH_QBLA  = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
 576    OPC_PRECEU_PH_QBRA  = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
 577    /* DSP Bit/Manipulation Sub-class */
 578    OPC_BITREV          = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
 579    OPC_REPL_QB         = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
 580    OPC_REPLV_QB        = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
 581    OPC_REPL_PH         = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
 582    OPC_REPLV_PH        = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
 583};
 584
 585#define MASK_CMPU_EQ_QB(op)         (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 586enum {
 587    /* MIPS DSP Arithmetic Sub-class */
 588    OPC_PRECR_QB_PH      = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
 589    OPC_PRECRQ_QB_PH     = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
 590    OPC_PRECR_SRA_PH_W   = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
 591    OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
 592    OPC_PRECRQ_PH_W      = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
 593    OPC_PRECRQ_RS_PH_W   = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
 594    OPC_PRECRQU_S_QB_PH  = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
 595    /* DSP Compare-Pick Sub-class */
 596    OPC_CMPU_EQ_QB       = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
 597    OPC_CMPU_LT_QB       = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
 598    OPC_CMPU_LE_QB       = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
 599    OPC_CMPGU_EQ_QB      = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
 600    OPC_CMPGU_LT_QB      = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
 601    OPC_CMPGU_LE_QB      = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
 602    OPC_CMPGDU_EQ_QB     = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
 603    OPC_CMPGDU_LT_QB     = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
 604    OPC_CMPGDU_LE_QB     = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
 605    OPC_CMP_EQ_PH        = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
 606    OPC_CMP_LT_PH        = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
 607    OPC_CMP_LE_PH        = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
 608    OPC_PICK_QB          = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
 609    OPC_PICK_PH          = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
 610    OPC_PACKRL_PH        = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
 611};
 612
 613#define MASK_SHLL_QB(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 614enum {
 615    /* MIPS DSP GPR-Based Shift Sub-class */
 616    OPC_SHLL_QB    = (0x00 << 6) | OPC_SHLL_QB_DSP,
 617    OPC_SHLLV_QB   = (0x02 << 6) | OPC_SHLL_QB_DSP,
 618    OPC_SHLL_PH    = (0x08 << 6) | OPC_SHLL_QB_DSP,
 619    OPC_SHLLV_PH   = (0x0A << 6) | OPC_SHLL_QB_DSP,
 620    OPC_SHLL_S_PH  = (0x0C << 6) | OPC_SHLL_QB_DSP,
 621    OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
 622    OPC_SHLL_S_W   = (0x14 << 6) | OPC_SHLL_QB_DSP,
 623    OPC_SHLLV_S_W  = (0x16 << 6) | OPC_SHLL_QB_DSP,
 624    OPC_SHRL_QB    = (0x01 << 6) | OPC_SHLL_QB_DSP,
 625    OPC_SHRLV_QB   = (0x03 << 6) | OPC_SHLL_QB_DSP,
 626    OPC_SHRL_PH    = (0x19 << 6) | OPC_SHLL_QB_DSP,
 627    OPC_SHRLV_PH   = (0x1B << 6) | OPC_SHLL_QB_DSP,
 628    OPC_SHRA_QB    = (0x04 << 6) | OPC_SHLL_QB_DSP,
 629    OPC_SHRA_R_QB  = (0x05 << 6) | OPC_SHLL_QB_DSP,
 630    OPC_SHRAV_QB   = (0x06 << 6) | OPC_SHLL_QB_DSP,
 631    OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
 632    OPC_SHRA_PH    = (0x09 << 6) | OPC_SHLL_QB_DSP,
 633    OPC_SHRAV_PH   = (0x0B << 6) | OPC_SHLL_QB_DSP,
 634    OPC_SHRA_R_PH  = (0x0D << 6) | OPC_SHLL_QB_DSP,
 635    OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
 636    OPC_SHRA_R_W   = (0x15 << 6) | OPC_SHLL_QB_DSP,
 637    OPC_SHRAV_R_W  = (0x17 << 6) | OPC_SHLL_QB_DSP,
 638};
 639
 640#define MASK_DPA_W_PH(op)           (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 641enum {
 642    /* MIPS DSP Multiply Sub-class insns */
 643    OPC_DPAU_H_QBL    = (0x03 << 6) | OPC_DPA_W_PH_DSP,
 644    OPC_DPAU_H_QBR    = (0x07 << 6) | OPC_DPA_W_PH_DSP,
 645    OPC_DPSU_H_QBL    = (0x0B << 6) | OPC_DPA_W_PH_DSP,
 646    OPC_DPSU_H_QBR    = (0x0F << 6) | OPC_DPA_W_PH_DSP,
 647    OPC_DPA_W_PH      = (0x00 << 6) | OPC_DPA_W_PH_DSP,
 648    OPC_DPAX_W_PH     = (0x08 << 6) | OPC_DPA_W_PH_DSP,
 649    OPC_DPAQ_S_W_PH   = (0x04 << 6) | OPC_DPA_W_PH_DSP,
 650    OPC_DPAQX_S_W_PH  = (0x18 << 6) | OPC_DPA_W_PH_DSP,
 651    OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
 652    OPC_DPS_W_PH      = (0x01 << 6) | OPC_DPA_W_PH_DSP,
 653    OPC_DPSX_W_PH     = (0x09 << 6) | OPC_DPA_W_PH_DSP,
 654    OPC_DPSQ_S_W_PH   = (0x05 << 6) | OPC_DPA_W_PH_DSP,
 655    OPC_DPSQX_S_W_PH  = (0x19 << 6) | OPC_DPA_W_PH_DSP,
 656    OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
 657    OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
 658    OPC_DPAQ_SA_L_W   = (0x0C << 6) | OPC_DPA_W_PH_DSP,
 659    OPC_DPSQ_SA_L_W   = (0x0D << 6) | OPC_DPA_W_PH_DSP,
 660    OPC_MAQ_S_W_PHL   = (0x14 << 6) | OPC_DPA_W_PH_DSP,
 661    OPC_MAQ_S_W_PHR   = (0x16 << 6) | OPC_DPA_W_PH_DSP,
 662    OPC_MAQ_SA_W_PHL  = (0x10 << 6) | OPC_DPA_W_PH_DSP,
 663    OPC_MAQ_SA_W_PHR  = (0x12 << 6) | OPC_DPA_W_PH_DSP,
 664    OPC_MULSA_W_PH    = (0x02 << 6) | OPC_DPA_W_PH_DSP,
 665};
 666
 667#define MASK_INSV(op)               (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 668enum {
 669    /* DSP Bit/Manipulation Sub-class */
 670    OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
 671};
 672
 673#define MASK_APPEND(op)             (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 674enum {
 675    /* MIPS DSP Append Sub-class */
 676    OPC_APPEND  = (0x00 << 6) | OPC_APPEND_DSP,
 677    OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
 678    OPC_BALIGN  = (0x10 << 6) | OPC_APPEND_DSP,
 679};
 680
 681#define MASK_EXTR_W(op)             (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 682enum {
 683    /* MIPS DSP Accumulator and DSPControl Access Sub-class */
 684    OPC_EXTR_W     = (0x00 << 6) | OPC_EXTR_W_DSP,
 685    OPC_EXTR_R_W   = (0x04 << 6) | OPC_EXTR_W_DSP,
 686    OPC_EXTR_RS_W  = (0x06 << 6) | OPC_EXTR_W_DSP,
 687    OPC_EXTR_S_H   = (0x0E << 6) | OPC_EXTR_W_DSP,
 688    OPC_EXTRV_S_H  = (0x0F << 6) | OPC_EXTR_W_DSP,
 689    OPC_EXTRV_W    = (0x01 << 6) | OPC_EXTR_W_DSP,
 690    OPC_EXTRV_R_W  = (0x05 << 6) | OPC_EXTR_W_DSP,
 691    OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
 692    OPC_EXTP       = (0x02 << 6) | OPC_EXTR_W_DSP,
 693    OPC_EXTPV      = (0x03 << 6) | OPC_EXTR_W_DSP,
 694    OPC_EXTPDP     = (0x0A << 6) | OPC_EXTR_W_DSP,
 695    OPC_EXTPDPV    = (0x0B << 6) | OPC_EXTR_W_DSP,
 696    OPC_SHILO      = (0x1A << 6) | OPC_EXTR_W_DSP,
 697    OPC_SHILOV     = (0x1B << 6) | OPC_EXTR_W_DSP,
 698    OPC_MTHLIP     = (0x1F << 6) | OPC_EXTR_W_DSP,
 699    OPC_WRDSP      = (0x13 << 6) | OPC_EXTR_W_DSP,
 700    OPC_RDDSP      = (0x12 << 6) | OPC_EXTR_W_DSP,
 701};
 702
 703#define MASK_ABSQ_S_QH(op)          (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 704enum {
 705    /* MIPS DSP Arithmetic Sub-class */
 706    OPC_PRECEQ_L_PWL    = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
 707    OPC_PRECEQ_L_PWR    = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
 708    OPC_PRECEQ_PW_QHL   = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
 709    OPC_PRECEQ_PW_QHR   = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
 710    OPC_PRECEQ_PW_QHLA  = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
 711    OPC_PRECEQ_PW_QHRA  = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
 712    OPC_PRECEQU_QH_OBL  = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
 713    OPC_PRECEQU_QH_OBR  = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
 714    OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
 715    OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
 716    OPC_PRECEU_QH_OBL   = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
 717    OPC_PRECEU_QH_OBR   = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
 718    OPC_PRECEU_QH_OBLA  = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
 719    OPC_PRECEU_QH_OBRA  = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
 720    OPC_ABSQ_S_OB       = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
 721    OPC_ABSQ_S_PW       = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
 722    OPC_ABSQ_S_QH       = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
 723    /* DSP Bit/Manipulation Sub-class */
 724    OPC_REPL_OB         = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
 725    OPC_REPL_PW         = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
 726    OPC_REPL_QH         = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
 727    OPC_REPLV_OB        = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
 728    OPC_REPLV_PW        = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
 729    OPC_REPLV_QH        = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
 730};
 731
 732#define MASK_ADDU_OB(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 733enum {
 734    /* MIPS DSP Multiply Sub-class insns */
 735    OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
 736    OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
 737    OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
 738    OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
 739    OPC_MULQ_RS_QH     = (0x1F << 6) | OPC_ADDU_OB_DSP,
 740    /* MIPS DSP Arithmetic Sub-class */
 741    OPC_RADDU_L_OB     = (0x14 << 6) | OPC_ADDU_OB_DSP,
 742    OPC_SUBQ_PW        = (0x13 << 6) | OPC_ADDU_OB_DSP,
 743    OPC_SUBQ_S_PW      = (0x17 << 6) | OPC_ADDU_OB_DSP,
 744    OPC_SUBQ_QH        = (0x0B << 6) | OPC_ADDU_OB_DSP,
 745    OPC_SUBQ_S_QH      = (0x0F << 6) | OPC_ADDU_OB_DSP,
 746    OPC_SUBU_OB        = (0x01 << 6) | OPC_ADDU_OB_DSP,
 747    OPC_SUBU_S_OB      = (0x05 << 6) | OPC_ADDU_OB_DSP,
 748    OPC_SUBU_QH        = (0x09 << 6) | OPC_ADDU_OB_DSP,
 749    OPC_SUBU_S_QH      = (0x0D << 6) | OPC_ADDU_OB_DSP,
 750    OPC_SUBUH_OB       = (0x19 << 6) | OPC_ADDU_OB_DSP,
 751    OPC_SUBUH_R_OB     = (0x1B << 6) | OPC_ADDU_OB_DSP,
 752    OPC_ADDQ_PW        = (0x12 << 6) | OPC_ADDU_OB_DSP,
 753    OPC_ADDQ_S_PW      = (0x16 << 6) | OPC_ADDU_OB_DSP,
 754    OPC_ADDQ_QH        = (0x0A << 6) | OPC_ADDU_OB_DSP,
 755    OPC_ADDQ_S_QH      = (0x0E << 6) | OPC_ADDU_OB_DSP,
 756    OPC_ADDU_OB        = (0x00 << 6) | OPC_ADDU_OB_DSP,
 757    OPC_ADDU_S_OB      = (0x04 << 6) | OPC_ADDU_OB_DSP,
 758    OPC_ADDU_QH        = (0x08 << 6) | OPC_ADDU_OB_DSP,
 759    OPC_ADDU_S_QH      = (0x0C << 6) | OPC_ADDU_OB_DSP,
 760    OPC_ADDUH_OB       = (0x18 << 6) | OPC_ADDU_OB_DSP,
 761    OPC_ADDUH_R_OB     = (0x1A << 6) | OPC_ADDU_OB_DSP,
 762};
 763
 764#define MASK_CMPU_EQ_OB(op)         (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 765enum {
 766    /* DSP Compare-Pick Sub-class */
 767    OPC_CMP_EQ_PW         = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
 768    OPC_CMP_LT_PW         = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
 769    OPC_CMP_LE_PW         = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
 770    OPC_CMP_EQ_QH         = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
 771    OPC_CMP_LT_QH         = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
 772    OPC_CMP_LE_QH         = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
 773    OPC_CMPGDU_EQ_OB      = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
 774    OPC_CMPGDU_LT_OB      = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
 775    OPC_CMPGDU_LE_OB      = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
 776    OPC_CMPGU_EQ_OB       = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
 777    OPC_CMPGU_LT_OB       = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
 778    OPC_CMPGU_LE_OB       = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
 779    OPC_CMPU_EQ_OB        = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
 780    OPC_CMPU_LT_OB        = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
 781    OPC_CMPU_LE_OB        = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
 782    OPC_PACKRL_PW         = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
 783    OPC_PICK_OB           = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
 784    OPC_PICK_PW           = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
 785    OPC_PICK_QH           = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
 786    /* MIPS DSP Arithmetic Sub-class */
 787    OPC_PRECR_OB_QH       = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
 788    OPC_PRECR_SRA_QH_PW   = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
 789    OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
 790    OPC_PRECRQ_OB_QH      = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
 791    OPC_PRECRQ_PW_L       = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
 792    OPC_PRECRQ_QH_PW      = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
 793    OPC_PRECRQ_RS_QH_PW   = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
 794    OPC_PRECRQU_S_OB_QH   = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
 795};
 796
 797#define MASK_DAPPEND(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 798enum {
 799    /* DSP Append Sub-class */
 800    OPC_DAPPEND  = (0x00 << 6) | OPC_DAPPEND_DSP,
 801    OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
 802    OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
 803    OPC_DBALIGN  = (0x10 << 6) | OPC_DAPPEND_DSP,
 804};
 805
 806#define MASK_DEXTR_W(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 807enum {
 808    /* MIPS DSP Accumulator and DSPControl Access Sub-class */
 809    OPC_DMTHLIP     = (0x1F << 6) | OPC_DEXTR_W_DSP,
 810    OPC_DSHILO      = (0x1A << 6) | OPC_DEXTR_W_DSP,
 811    OPC_DEXTP       = (0x02 << 6) | OPC_DEXTR_W_DSP,
 812    OPC_DEXTPDP     = (0x0A << 6) | OPC_DEXTR_W_DSP,
 813    OPC_DEXTPDPV    = (0x0B << 6) | OPC_DEXTR_W_DSP,
 814    OPC_DEXTPV      = (0x03 << 6) | OPC_DEXTR_W_DSP,
 815    OPC_DEXTR_L     = (0x10 << 6) | OPC_DEXTR_W_DSP,
 816    OPC_DEXTR_R_L   = (0x14 << 6) | OPC_DEXTR_W_DSP,
 817    OPC_DEXTR_RS_L  = (0x16 << 6) | OPC_DEXTR_W_DSP,
 818    OPC_DEXTR_W     = (0x00 << 6) | OPC_DEXTR_W_DSP,
 819    OPC_DEXTR_R_W   = (0x04 << 6) | OPC_DEXTR_W_DSP,
 820    OPC_DEXTR_RS_W  = (0x06 << 6) | OPC_DEXTR_W_DSP,
 821    OPC_DEXTR_S_H   = (0x0E << 6) | OPC_DEXTR_W_DSP,
 822    OPC_DEXTRV_L    = (0x11 << 6) | OPC_DEXTR_W_DSP,
 823    OPC_DEXTRV_R_L  = (0x15 << 6) | OPC_DEXTR_W_DSP,
 824    OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
 825    OPC_DEXTRV_S_H  = (0x0F << 6) | OPC_DEXTR_W_DSP,
 826    OPC_DEXTRV_W    = (0x01 << 6) | OPC_DEXTR_W_DSP,
 827    OPC_DEXTRV_R_W  = (0x05 << 6) | OPC_DEXTR_W_DSP,
 828    OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
 829    OPC_DSHILOV     = (0x1B << 6) | OPC_DEXTR_W_DSP,
 830};
 831
 832#define MASK_DINSV(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 833enum {
 834    /* DSP Bit/Manipulation Sub-class */
 835    OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
 836};
 837
 838#define MASK_DPAQ_W_QH(op)          (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 839enum {
 840    /* MIPS DSP Multiply Sub-class insns */
 841    OPC_DMADD         = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
 842    OPC_DMADDU        = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
 843    OPC_DMSUB         = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
 844    OPC_DMSUBU        = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
 845    OPC_DPA_W_QH      = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
 846    OPC_DPAQ_S_W_QH   = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
 847    OPC_DPAQ_SA_L_PW  = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
 848    OPC_DPAU_H_OBL    = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
 849    OPC_DPAU_H_OBR    = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
 850    OPC_DPS_W_QH      = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
 851    OPC_DPSQ_S_W_QH   = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
 852    OPC_DPSQ_SA_L_PW  = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
 853    OPC_DPSU_H_OBL    = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
 854    OPC_DPSU_H_OBR    = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
 855    OPC_MAQ_S_L_PWL   = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
 856    OPC_MAQ_S_L_PWR   = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
 857    OPC_MAQ_S_W_QHLL  = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
 858    OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
 859    OPC_MAQ_S_W_QHLR  = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
 860    OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
 861    OPC_MAQ_S_W_QHRL  = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
 862    OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
 863    OPC_MAQ_S_W_QHRR  = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
 864    OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
 865    OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
 866    OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
 867};
 868
 869#define MASK_SHLL_OB(op)            (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 870enum {
 871    /* MIPS DSP GPR-Based Shift Sub-class */
 872    OPC_SHLL_PW    = (0x10 << 6) | OPC_SHLL_OB_DSP,
 873    OPC_SHLL_S_PW  = (0x14 << 6) | OPC_SHLL_OB_DSP,
 874    OPC_SHLLV_OB   = (0x02 << 6) | OPC_SHLL_OB_DSP,
 875    OPC_SHLLV_PW   = (0x12 << 6) | OPC_SHLL_OB_DSP,
 876    OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
 877    OPC_SHLLV_QH   = (0x0A << 6) | OPC_SHLL_OB_DSP,
 878    OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
 879    OPC_SHRA_PW    = (0x11 << 6) | OPC_SHLL_OB_DSP,
 880    OPC_SHRA_R_PW  = (0x15 << 6) | OPC_SHLL_OB_DSP,
 881    OPC_SHRAV_OB   = (0x06 << 6) | OPC_SHLL_OB_DSP,
 882    OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
 883    OPC_SHRAV_PW   = (0x13 << 6) | OPC_SHLL_OB_DSP,
 884    OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
 885    OPC_SHRAV_QH   = (0x0B << 6) | OPC_SHLL_OB_DSP,
 886    OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
 887    OPC_SHRLV_OB   = (0x03 << 6) | OPC_SHLL_OB_DSP,
 888    OPC_SHRLV_QH   = (0x1B << 6) | OPC_SHLL_OB_DSP,
 889    OPC_SHLL_OB    = (0x00 << 6) | OPC_SHLL_OB_DSP,
 890    OPC_SHLL_QH    = (0x08 << 6) | OPC_SHLL_OB_DSP,
 891    OPC_SHLL_S_QH  = (0x0C << 6) | OPC_SHLL_OB_DSP,
 892    OPC_SHRA_OB    = (0x04 << 6) | OPC_SHLL_OB_DSP,
 893    OPC_SHRA_R_OB  = (0x05 << 6) | OPC_SHLL_OB_DSP,
 894    OPC_SHRA_QH    = (0x09 << 6) | OPC_SHLL_OB_DSP,
 895    OPC_SHRA_R_QH  = (0x0D << 6) | OPC_SHLL_OB_DSP,
 896    OPC_SHRL_OB    = (0x01 << 6) | OPC_SHLL_OB_DSP,
 897    OPC_SHRL_QH    = (0x19 << 6) | OPC_SHLL_OB_DSP,
 898};
 899
 900/* Coprocessor 0 (rs field) */
 901#define MASK_CP0(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
 902
 903enum {
 904    OPC_MFC0     = (0x00 << 21) | OPC_CP0,
 905    OPC_DMFC0    = (0x01 << 21) | OPC_CP0,
 906    OPC_MFHC0    = (0x02 << 21) | OPC_CP0,
 907    OPC_MTC0     = (0x04 << 21) | OPC_CP0,
 908    OPC_DMTC0    = (0x05 << 21) | OPC_CP0,
 909    OPC_MTHC0    = (0x06 << 21) | OPC_CP0,
 910    OPC_MFTR     = (0x08 << 21) | OPC_CP0,
 911    OPC_RDPGPR   = (0x0A << 21) | OPC_CP0,
 912    OPC_MFMC0    = (0x0B << 21) | OPC_CP0,
 913    OPC_MTTR     = (0x0C << 21) | OPC_CP0,
 914    OPC_WRPGPR   = (0x0E << 21) | OPC_CP0,
 915    OPC_C0       = (0x10 << 21) | OPC_CP0,
 916    OPC_C0_1     = (0x11 << 21) | OPC_CP0,
 917    OPC_C0_2     = (0x12 << 21) | OPC_CP0,
 918    OPC_C0_3     = (0x13 << 21) | OPC_CP0,
 919    OPC_C0_4     = (0x14 << 21) | OPC_CP0,
 920    OPC_C0_5     = (0x15 << 21) | OPC_CP0,
 921    OPC_C0_6     = (0x16 << 21) | OPC_CP0,
 922    OPC_C0_7     = (0x17 << 21) | OPC_CP0,
 923    OPC_C0_8     = (0x18 << 21) | OPC_CP0,
 924    OPC_C0_9     = (0x19 << 21) | OPC_CP0,
 925    OPC_C0_A     = (0x1A << 21) | OPC_CP0,
 926    OPC_C0_B     = (0x1B << 21) | OPC_CP0,
 927    OPC_C0_C     = (0x1C << 21) | OPC_CP0,
 928    OPC_C0_D     = (0x1D << 21) | OPC_CP0,
 929    OPC_C0_E     = (0x1E << 21) | OPC_CP0,
 930    OPC_C0_F     = (0x1F << 21) | OPC_CP0,
 931};
 932
 933/* MFMC0 opcodes */
 934#define MASK_MFMC0(op)              (MASK_CP0(op) | (op & 0xFFFF))
 935
 936enum {
 937    OPC_DMT      = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
 938    OPC_EMT      = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
 939    OPC_DVPE     = 0x01 | (0 << 5) | OPC_MFMC0,
 940    OPC_EVPE     = 0x01 | (1 << 5) | OPC_MFMC0,
 941    OPC_DI       = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
 942    OPC_EI       = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
 943    OPC_DVP      = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0,
 944    OPC_EVP      = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0,
 945};
 946
 947/* Coprocessor 0 (with rs == C0) */
 948#define MASK_C0(op)                 (MASK_CP0(op) | (op & 0x3F))
 949
 950enum {
 951    OPC_TLBR     = 0x01 | OPC_C0,
 952    OPC_TLBWI    = 0x02 | OPC_C0,
 953    OPC_TLBINV   = 0x03 | OPC_C0,
 954    OPC_TLBINVF  = 0x04 | OPC_C0,
 955    OPC_TLBWR    = 0x06 | OPC_C0,
 956    OPC_TLBP     = 0x08 | OPC_C0,
 957    OPC_RFE      = 0x10 | OPC_C0,
 958    OPC_ERET     = 0x18 | OPC_C0,
 959    OPC_DERET    = 0x1F | OPC_C0,
 960    OPC_WAIT     = 0x20 | OPC_C0,
 961};
 962
 963/* Coprocessor 1 (rs field) */
 964#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
 965
 966/* Values for the fmt field in FP instructions */
 967enum {
 968    /* 0 - 15 are reserved */
 969    FMT_S = 16,          /* single fp */
 970    FMT_D = 17,          /* double fp */
 971    FMT_E = 18,          /* extended fp */
 972    FMT_Q = 19,          /* quad fp */
 973    FMT_W = 20,          /* 32-bit fixed */
 974    FMT_L = 21,          /* 64-bit fixed */
 975    FMT_PS = 22,         /* paired single fp */
 976    /* 23 - 31 are reserved */
 977};
 978
 979enum {
 980    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
 981    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
 982    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
 983    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
 984    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
 985    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
 986    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
 987    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
 988    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
 989    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
 990    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
 991    OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
 992    OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
 993    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
 994    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
 995    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
 996    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
 997    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
 998    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
 999    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
1000    OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
1001    OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
1002    OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
1003    OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
1004    OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
1005    OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
1006    OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
1007    OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
1008    OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
1009    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
1010};
1011
1012#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
1013#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
1014
1015enum {
1016    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
1017    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
1018    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
1019    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
1020};
1021
1022enum {
1023    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
1024    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
1025};
1026
1027enum {
1028    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
1029    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
1030};
1031
1032#define MASK_CP2(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
1033
1034enum {
1035    OPC_MFC2    = (0x00 << 21) | OPC_CP2,
1036    OPC_DMFC2   = (0x01 << 21) | OPC_CP2,
1037    OPC_CFC2    = (0x02 << 21) | OPC_CP2,
1038    OPC_MFHC2   = (0x03 << 21) | OPC_CP2,
1039    OPC_MTC2    = (0x04 << 21) | OPC_CP2,
1040    OPC_DMTC2   = (0x05 << 21) | OPC_CP2,
1041    OPC_CTC2    = (0x06 << 21) | OPC_CP2,
1042    OPC_MTHC2   = (0x07 << 21) | OPC_CP2,
1043    OPC_BC2     = (0x08 << 21) | OPC_CP2,
1044    OPC_BC2EQZ  = (0x09 << 21) | OPC_CP2,
1045    OPC_BC2NEZ  = (0x0D << 21) | OPC_CP2,
1046};
1047
1048#define MASK_LMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1049
1050enum {
1051    OPC_PADDSH      = (24 << 21) | (0x00) | OPC_CP2,
1052    OPC_PADDUSH     = (25 << 21) | (0x00) | OPC_CP2,
1053    OPC_PADDH       = (26 << 21) | (0x00) | OPC_CP2,
1054    OPC_PADDW       = (27 << 21) | (0x00) | OPC_CP2,
1055    OPC_PADDSB      = (28 << 21) | (0x00) | OPC_CP2,
1056    OPC_PADDUSB     = (29 << 21) | (0x00) | OPC_CP2,
1057    OPC_PADDB       = (30 << 21) | (0x00) | OPC_CP2,
1058    OPC_PADDD       = (31 << 21) | (0x00) | OPC_CP2,
1059
1060    OPC_PSUBSH      = (24 << 21) | (0x01) | OPC_CP2,
1061    OPC_PSUBUSH     = (25 << 21) | (0x01) | OPC_CP2,
1062    OPC_PSUBH       = (26 << 21) | (0x01) | OPC_CP2,
1063    OPC_PSUBW       = (27 << 21) | (0x01) | OPC_CP2,
1064    OPC_PSUBSB      = (28 << 21) | (0x01) | OPC_CP2,
1065    OPC_PSUBUSB     = (29 << 21) | (0x01) | OPC_CP2,
1066    OPC_PSUBB       = (30 << 21) | (0x01) | OPC_CP2,
1067    OPC_PSUBD       = (31 << 21) | (0x01) | OPC_CP2,
1068
1069    OPC_PSHUFH      = (24 << 21) | (0x02) | OPC_CP2,
1070    OPC_PACKSSWH    = (25 << 21) | (0x02) | OPC_CP2,
1071    OPC_PACKSSHB    = (26 << 21) | (0x02) | OPC_CP2,
1072    OPC_PACKUSHB    = (27 << 21) | (0x02) | OPC_CP2,
1073    OPC_XOR_CP2     = (28 << 21) | (0x02) | OPC_CP2,
1074    OPC_NOR_CP2     = (29 << 21) | (0x02) | OPC_CP2,
1075    OPC_AND_CP2     = (30 << 21) | (0x02) | OPC_CP2,
1076    OPC_PANDN       = (31 << 21) | (0x02) | OPC_CP2,
1077
1078    OPC_PUNPCKLHW   = (24 << 21) | (0x03) | OPC_CP2,
1079    OPC_PUNPCKHHW   = (25 << 21) | (0x03) | OPC_CP2,
1080    OPC_PUNPCKLBH   = (26 << 21) | (0x03) | OPC_CP2,
1081    OPC_PUNPCKHBH   = (27 << 21) | (0x03) | OPC_CP2,
1082    OPC_PINSRH_0    = (28 << 21) | (0x03) | OPC_CP2,
1083    OPC_PINSRH_1    = (29 << 21) | (0x03) | OPC_CP2,
1084    OPC_PINSRH_2    = (30 << 21) | (0x03) | OPC_CP2,
1085    OPC_PINSRH_3    = (31 << 21) | (0x03) | OPC_CP2,
1086
1087    OPC_PAVGH       = (24 << 21) | (0x08) | OPC_CP2,
1088    OPC_PAVGB       = (25 << 21) | (0x08) | OPC_CP2,
1089    OPC_PMAXSH      = (26 << 21) | (0x08) | OPC_CP2,
1090    OPC_PMINSH      = (27 << 21) | (0x08) | OPC_CP2,
1091    OPC_PMAXUB      = (28 << 21) | (0x08) | OPC_CP2,
1092    OPC_PMINUB      = (29 << 21) | (0x08) | OPC_CP2,
1093
1094    OPC_PCMPEQW     = (24 << 21) | (0x09) | OPC_CP2,
1095    OPC_PCMPGTW     = (25 << 21) | (0x09) | OPC_CP2,
1096    OPC_PCMPEQH     = (26 << 21) | (0x09) | OPC_CP2,
1097    OPC_PCMPGTH     = (27 << 21) | (0x09) | OPC_CP2,
1098    OPC_PCMPEQB     = (28 << 21) | (0x09) | OPC_CP2,
1099    OPC_PCMPGTB     = (29 << 21) | (0x09) | OPC_CP2,
1100
1101    OPC_PSLLW       = (24 << 21) | (0x0A) | OPC_CP2,
1102    OPC_PSLLH       = (25 << 21) | (0x0A) | OPC_CP2,
1103    OPC_PMULLH      = (26 << 21) | (0x0A) | OPC_CP2,
1104    OPC_PMULHH      = (27 << 21) | (0x0A) | OPC_CP2,
1105    OPC_PMULUW      = (28 << 21) | (0x0A) | OPC_CP2,
1106    OPC_PMULHUH     = (29 << 21) | (0x0A) | OPC_CP2,
1107
1108    OPC_PSRLW       = (24 << 21) | (0x0B) | OPC_CP2,
1109    OPC_PSRLH       = (25 << 21) | (0x0B) | OPC_CP2,
1110    OPC_PSRAW       = (26 << 21) | (0x0B) | OPC_CP2,
1111    OPC_PSRAH       = (27 << 21) | (0x0B) | OPC_CP2,
1112    OPC_PUNPCKLWD   = (28 << 21) | (0x0B) | OPC_CP2,
1113    OPC_PUNPCKHWD   = (29 << 21) | (0x0B) | OPC_CP2,
1114
1115    OPC_ADDU_CP2    = (24 << 21) | (0x0C) | OPC_CP2,
1116    OPC_OR_CP2      = (25 << 21) | (0x0C) | OPC_CP2,
1117    OPC_ADD_CP2     = (26 << 21) | (0x0C) | OPC_CP2,
1118    OPC_DADD_CP2    = (27 << 21) | (0x0C) | OPC_CP2,
1119    OPC_SEQU_CP2    = (28 << 21) | (0x0C) | OPC_CP2,
1120    OPC_SEQ_CP2     = (29 << 21) | (0x0C) | OPC_CP2,
1121
1122    OPC_SUBU_CP2    = (24 << 21) | (0x0D) | OPC_CP2,
1123    OPC_PASUBUB     = (25 << 21) | (0x0D) | OPC_CP2,
1124    OPC_SUB_CP2     = (26 << 21) | (0x0D) | OPC_CP2,
1125    OPC_DSUB_CP2    = (27 << 21) | (0x0D) | OPC_CP2,
1126    OPC_SLTU_CP2    = (28 << 21) | (0x0D) | OPC_CP2,
1127    OPC_SLT_CP2     = (29 << 21) | (0x0D) | OPC_CP2,
1128
1129    OPC_SLL_CP2     = (24 << 21) | (0x0E) | OPC_CP2,
1130    OPC_DSLL_CP2    = (25 << 21) | (0x0E) | OPC_CP2,
1131    OPC_PEXTRH      = (26 << 21) | (0x0E) | OPC_CP2,
1132    OPC_PMADDHW     = (27 << 21) | (0x0E) | OPC_CP2,
1133    OPC_SLEU_CP2    = (28 << 21) | (0x0E) | OPC_CP2,
1134    OPC_SLE_CP2     = (29 << 21) | (0x0E) | OPC_CP2,
1135
1136    OPC_SRL_CP2     = (24 << 21) | (0x0F) | OPC_CP2,
1137    OPC_DSRL_CP2    = (25 << 21) | (0x0F) | OPC_CP2,
1138    OPC_SRA_CP2     = (26 << 21) | (0x0F) | OPC_CP2,
1139    OPC_DSRA_CP2    = (27 << 21) | (0x0F) | OPC_CP2,
1140    OPC_BIADD       = (28 << 21) | (0x0F) | OPC_CP2,
1141    OPC_PMOVMSKB    = (29 << 21) | (0x0F) | OPC_CP2,
1142};
1143
1144
1145#define MASK_CP3(op)                (MASK_OP_MAJOR(op) | (op & 0x3F))
1146
1147enum {
1148    OPC_LWXC1       = 0x00 | OPC_CP3,
1149    OPC_LDXC1       = 0x01 | OPC_CP3,
1150    OPC_LUXC1       = 0x05 | OPC_CP3,
1151    OPC_SWXC1       = 0x08 | OPC_CP3,
1152    OPC_SDXC1       = 0x09 | OPC_CP3,
1153    OPC_SUXC1       = 0x0D | OPC_CP3,
1154    OPC_PREFX       = 0x0F | OPC_CP3,
1155    OPC_ALNV_PS     = 0x1E | OPC_CP3,
1156    OPC_MADD_S      = 0x20 | OPC_CP3,
1157    OPC_MADD_D      = 0x21 | OPC_CP3,
1158    OPC_MADD_PS     = 0x26 | OPC_CP3,
1159    OPC_MSUB_S      = 0x28 | OPC_CP3,
1160    OPC_MSUB_D      = 0x29 | OPC_CP3,
1161    OPC_MSUB_PS     = 0x2E | OPC_CP3,
1162    OPC_NMADD_S     = 0x30 | OPC_CP3,
1163    OPC_NMADD_D     = 0x31 | OPC_CP3,
1164    OPC_NMADD_PS    = 0x36 | OPC_CP3,
1165    OPC_NMSUB_S     = 0x38 | OPC_CP3,
1166    OPC_NMSUB_D     = 0x39 | OPC_CP3,
1167    OPC_NMSUB_PS    = 0x3E | OPC_CP3,
1168};
1169
1170/* MSA Opcodes */
1171#define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
1172enum {
1173    OPC_MSA_I8_00   = 0x00 | OPC_MSA,
1174    OPC_MSA_I8_01   = 0x01 | OPC_MSA,
1175    OPC_MSA_I8_02   = 0x02 | OPC_MSA,
1176    OPC_MSA_I5_06   = 0x06 | OPC_MSA,
1177    OPC_MSA_I5_07   = 0x07 | OPC_MSA,
1178    OPC_MSA_BIT_09  = 0x09 | OPC_MSA,
1179    OPC_MSA_BIT_0A  = 0x0A | OPC_MSA,
1180    OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
1181    OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
1182    OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
1183    OPC_MSA_3R_10   = 0x10 | OPC_MSA,
1184    OPC_MSA_3R_11   = 0x11 | OPC_MSA,
1185    OPC_MSA_3R_12   = 0x12 | OPC_MSA,
1186    OPC_MSA_3R_13   = 0x13 | OPC_MSA,
1187    OPC_MSA_3R_14   = 0x14 | OPC_MSA,
1188    OPC_MSA_3R_15   = 0x15 | OPC_MSA,
1189    OPC_MSA_ELM     = 0x19 | OPC_MSA,
1190    OPC_MSA_3RF_1A  = 0x1A | OPC_MSA,
1191    OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
1192    OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
1193    OPC_MSA_VEC     = 0x1E | OPC_MSA,
1194
1195    /* MI10 instruction */
1196    OPC_LD_B        = (0x20) | OPC_MSA,
1197    OPC_LD_H        = (0x21) | OPC_MSA,
1198    OPC_LD_W        = (0x22) | OPC_MSA,
1199    OPC_LD_D        = (0x23) | OPC_MSA,
1200    OPC_ST_B        = (0x24) | OPC_MSA,
1201    OPC_ST_H        = (0x25) | OPC_MSA,
1202    OPC_ST_W        = (0x26) | OPC_MSA,
1203    OPC_ST_D        = (0x27) | OPC_MSA,
1204};
1205
1206enum {
1207    /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
1208    OPC_ADDVI_df    = (0x0 << 23) | OPC_MSA_I5_06,
1209    OPC_CEQI_df     = (0x0 << 23) | OPC_MSA_I5_07,
1210    OPC_SUBVI_df    = (0x1 << 23) | OPC_MSA_I5_06,
1211    OPC_MAXI_S_df   = (0x2 << 23) | OPC_MSA_I5_06,
1212    OPC_CLTI_S_df   = (0x2 << 23) | OPC_MSA_I5_07,
1213    OPC_MAXI_U_df   = (0x3 << 23) | OPC_MSA_I5_06,
1214    OPC_CLTI_U_df   = (0x3 << 23) | OPC_MSA_I5_07,
1215    OPC_MINI_S_df   = (0x4 << 23) | OPC_MSA_I5_06,
1216    OPC_CLEI_S_df   = (0x4 << 23) | OPC_MSA_I5_07,
1217    OPC_MINI_U_df   = (0x5 << 23) | OPC_MSA_I5_06,
1218    OPC_CLEI_U_df   = (0x5 << 23) | OPC_MSA_I5_07,
1219    OPC_LDI_df      = (0x6 << 23) | OPC_MSA_I5_07,
1220
1221    /* I8 instruction */
1222    OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
1223    OPC_BMNZI_B     = (0x0 << 24) | OPC_MSA_I8_01,
1224    OPC_SHF_B       = (0x0 << 24) | OPC_MSA_I8_02,
1225    OPC_ORI_B       = (0x1 << 24) | OPC_MSA_I8_00,
1226    OPC_BMZI_B      = (0x1 << 24) | OPC_MSA_I8_01,
1227    OPC_SHF_H       = (0x1 << 24) | OPC_MSA_I8_02,
1228    OPC_NORI_B      = (0x2 << 24) | OPC_MSA_I8_00,
1229    OPC_BSELI_B     = (0x2 << 24) | OPC_MSA_I8_01,
1230    OPC_SHF_W       = (0x2 << 24) | OPC_MSA_I8_02,
1231    OPC_XORI_B      = (0x3 << 24) | OPC_MSA_I8_00,
1232
1233    /* VEC/2R/2RF instruction */
1234    OPC_AND_V       = (0x00 << 21) | OPC_MSA_VEC,
1235    OPC_OR_V        = (0x01 << 21) | OPC_MSA_VEC,
1236    OPC_NOR_V       = (0x02 << 21) | OPC_MSA_VEC,
1237    OPC_XOR_V       = (0x03 << 21) | OPC_MSA_VEC,
1238    OPC_BMNZ_V      = (0x04 << 21) | OPC_MSA_VEC,
1239    OPC_BMZ_V       = (0x05 << 21) | OPC_MSA_VEC,
1240    OPC_BSEL_V      = (0x06 << 21) | OPC_MSA_VEC,
1241
1242    OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
1243    OPC_MSA_2RF     = (0x19 << 21) | OPC_MSA_VEC,
1244
1245    /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
1246    OPC_FILL_df     = (0x00 << 18) | OPC_MSA_2R,
1247    OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
1248    OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
1249    OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
1250
1251    /* 2RF instruction df(bit 16) = _w, _d */
1252    OPC_FCLASS_df   = (0x00 << 17) | OPC_MSA_2RF,
1253    OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
1254    OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
1255    OPC_FSQRT_df    = (0x03 << 17) | OPC_MSA_2RF,
1256    OPC_FRSQRT_df   = (0x04 << 17) | OPC_MSA_2RF,
1257    OPC_FRCP_df     = (0x05 << 17) | OPC_MSA_2RF,
1258    OPC_FRINT_df    = (0x06 << 17) | OPC_MSA_2RF,
1259    OPC_FLOG2_df    = (0x07 << 17) | OPC_MSA_2RF,
1260    OPC_FEXUPL_df   = (0x08 << 17) | OPC_MSA_2RF,
1261    OPC_FEXUPR_df   = (0x09 << 17) | OPC_MSA_2RF,
1262    OPC_FFQL_df     = (0x0A << 17) | OPC_MSA_2RF,
1263    OPC_FFQR_df     = (0x0B << 17) | OPC_MSA_2RF,
1264    OPC_FTINT_S_df  = (0x0C << 17) | OPC_MSA_2RF,
1265    OPC_FTINT_U_df  = (0x0D << 17) | OPC_MSA_2RF,
1266    OPC_FFINT_S_df  = (0x0E << 17) | OPC_MSA_2RF,
1267    OPC_FFINT_U_df  = (0x0F << 17) | OPC_MSA_2RF,
1268
1269    /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
1270    OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
1271    OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
1272    OPC_CEQ_df      = (0x0 << 23) | OPC_MSA_3R_0F,
1273    OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
1274    OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
1275    OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
1276    OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
1277    OPC_SLD_df      = (0x0 << 23) | OPC_MSA_3R_14,
1278    OPC_VSHF_df     = (0x0 << 23) | OPC_MSA_3R_15,
1279    OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
1280    OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
1281    OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
1282    OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
1283    OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
1284    OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
1285    OPC_SPLAT_df    = (0x1 << 23) | OPC_MSA_3R_14,
1286    OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
1287    OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
1288    OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
1289    OPC_CLT_S_df    = (0x2 << 23) | OPC_MSA_3R_0F,
1290    OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
1291    OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
1292    OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
1293    OPC_DPADD_S_df  = (0x2 << 23) | OPC_MSA_3R_13,
1294    OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
1295    OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
1296    OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
1297    OPC_MAX_U_df    = (0x3 << 23) | OPC_MSA_3R_0E,
1298    OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
1299    OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
1300    OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
1301    OPC_DPADD_U_df  = (0x3 << 23) | OPC_MSA_3R_13,
1302    OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
1303    OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
1304    OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
1305    OPC_CLE_S_df    = (0x4 << 23) | OPC_MSA_3R_0F,
1306    OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
1307    OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
1308    OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
1309    OPC_DPSUB_S_df  = (0x4 << 23) | OPC_MSA_3R_13,
1310    OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
1311    OPC_HADD_S_df   = (0x4 << 23) | OPC_MSA_3R_15,
1312    OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
1313    OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
1314    OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
1315    OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
1316    OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
1317    OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
1318    OPC_DPSUB_U_df  = (0x5 << 23) | OPC_MSA_3R_13,
1319    OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
1320    OPC_HADD_U_df   = (0x5 << 23) | OPC_MSA_3R_15,
1321    OPC_BINSL_df    = (0x6 << 23) | OPC_MSA_3R_0D,
1322    OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
1323    OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
1324    OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
1325    OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
1326    OPC_HSUB_S_df   = (0x6 << 23) | OPC_MSA_3R_15,
1327    OPC_BINSR_df    = (0x7 << 23) | OPC_MSA_3R_0D,
1328    OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
1329    OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
1330    OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
1331    OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
1332    OPC_HSUB_U_df   = (0x7 << 23) | OPC_MSA_3R_15,
1333
1334    /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
1335    OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1336    OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1337    OPC_SPLATI_df   = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1338    OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1339    OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1340    OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1341    OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1342    OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1343    OPC_INSVE_df    = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1344
1345    /* 3RF instruction _df(bit 21) = _w, _d */
1346    OPC_FCAF_df     = (0x0 << 22) | OPC_MSA_3RF_1A,
1347    OPC_FADD_df     = (0x0 << 22) | OPC_MSA_3RF_1B,
1348    OPC_FCUN_df     = (0x1 << 22) | OPC_MSA_3RF_1A,
1349    OPC_FSUB_df     = (0x1 << 22) | OPC_MSA_3RF_1B,
1350    OPC_FCOR_df     = (0x1 << 22) | OPC_MSA_3RF_1C,
1351    OPC_FCEQ_df     = (0x2 << 22) | OPC_MSA_3RF_1A,
1352    OPC_FMUL_df     = (0x2 << 22) | OPC_MSA_3RF_1B,
1353    OPC_FCUNE_df    = (0x2 << 22) | OPC_MSA_3RF_1C,
1354    OPC_FCUEQ_df    = (0x3 << 22) | OPC_MSA_3RF_1A,
1355    OPC_FDIV_df     = (0x3 << 22) | OPC_MSA_3RF_1B,
1356    OPC_FCNE_df     = (0x3 << 22) | OPC_MSA_3RF_1C,
1357    OPC_FCLT_df     = (0x4 << 22) | OPC_MSA_3RF_1A,
1358    OPC_FMADD_df    = (0x4 << 22) | OPC_MSA_3RF_1B,
1359    OPC_MUL_Q_df    = (0x4 << 22) | OPC_MSA_3RF_1C,
1360    OPC_FCULT_df    = (0x5 << 22) | OPC_MSA_3RF_1A,
1361    OPC_FMSUB_df    = (0x5 << 22) | OPC_MSA_3RF_1B,
1362    OPC_MADD_Q_df   = (0x5 << 22) | OPC_MSA_3RF_1C,
1363    OPC_FCLE_df     = (0x6 << 22) | OPC_MSA_3RF_1A,
1364    OPC_MSUB_Q_df   = (0x6 << 22) | OPC_MSA_3RF_1C,
1365    OPC_FCULE_df    = (0x7 << 22) | OPC_MSA_3RF_1A,
1366    OPC_FEXP2_df    = (0x7 << 22) | OPC_MSA_3RF_1B,
1367    OPC_FSAF_df     = (0x8 << 22) | OPC_MSA_3RF_1A,
1368    OPC_FEXDO_df    = (0x8 << 22) | OPC_MSA_3RF_1B,
1369    OPC_FSUN_df     = (0x9 << 22) | OPC_MSA_3RF_1A,
1370    OPC_FSOR_df     = (0x9 << 22) | OPC_MSA_3RF_1C,
1371    OPC_FSEQ_df     = (0xA << 22) | OPC_MSA_3RF_1A,
1372    OPC_FTQ_df      = (0xA << 22) | OPC_MSA_3RF_1B,
1373    OPC_FSUNE_df    = (0xA << 22) | OPC_MSA_3RF_1C,
1374    OPC_FSUEQ_df    = (0xB << 22) | OPC_MSA_3RF_1A,
1375    OPC_FSNE_df     = (0xB << 22) | OPC_MSA_3RF_1C,
1376    OPC_FSLT_df     = (0xC << 22) | OPC_MSA_3RF_1A,
1377    OPC_FMIN_df     = (0xC << 22) | OPC_MSA_3RF_1B,
1378    OPC_MULR_Q_df   = (0xC << 22) | OPC_MSA_3RF_1C,
1379    OPC_FSULT_df    = (0xD << 22) | OPC_MSA_3RF_1A,
1380    OPC_FMIN_A_df   = (0xD << 22) | OPC_MSA_3RF_1B,
1381    OPC_MADDR_Q_df  = (0xD << 22) | OPC_MSA_3RF_1C,
1382    OPC_FSLE_df     = (0xE << 22) | OPC_MSA_3RF_1A,
1383    OPC_FMAX_df     = (0xE << 22) | OPC_MSA_3RF_1B,
1384    OPC_MSUBR_Q_df  = (0xE << 22) | OPC_MSA_3RF_1C,
1385    OPC_FSULE_df    = (0xF << 22) | OPC_MSA_3RF_1A,
1386    OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
1387
1388    /* BIT instruction df(bits 22..16) = _B _H _W _D */
1389    OPC_SLLI_df     = (0x0 << 23) | OPC_MSA_BIT_09,
1390    OPC_SAT_S_df    = (0x0 << 23) | OPC_MSA_BIT_0A,
1391    OPC_SRAI_df     = (0x1 << 23) | OPC_MSA_BIT_09,
1392    OPC_SAT_U_df    = (0x1 << 23) | OPC_MSA_BIT_0A,
1393    OPC_SRLI_df     = (0x2 << 23) | OPC_MSA_BIT_09,
1394    OPC_SRARI_df    = (0x2 << 23) | OPC_MSA_BIT_0A,
1395    OPC_BCLRI_df    = (0x3 << 23) | OPC_MSA_BIT_09,
1396    OPC_SRLRI_df    = (0x3 << 23) | OPC_MSA_BIT_0A,
1397    OPC_BSETI_df    = (0x4 << 23) | OPC_MSA_BIT_09,
1398    OPC_BNEGI_df    = (0x5 << 23) | OPC_MSA_BIT_09,
1399    OPC_BINSLI_df   = (0x6 << 23) | OPC_MSA_BIT_09,
1400    OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
1401};
1402
1403
1404/*
1405 *
1406 *       AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
1407 *       ============================================
1408 *
1409 *
1410 * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MIPS32
1411 * instructions set. It is designed to fit the needs of signal, graphical and
1412 * video processing applications. MXU instruction set is used in Xburst family
1413 * of microprocessors by Ingenic.
1414 *
1415 * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
1416 * the control register.
1417 *
1418 *
1419 *     The notation used in MXU assembler mnemonics
1420 *     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1421 *
1422 *  Register operands:
1423 *
1424 *   XRa, XRb, XRc, XRd - MXU registers
1425 *   Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
1426 *
1427 *  Non-register operands:
1428 *
1429 *   aptn1 - 1-bit accumulate add/subtract pattern
1430 *   aptn2 - 2-bit accumulate add/subtract pattern
1431 *   eptn2 - 2-bit execute add/subtract pattern
1432 *   optn2 - 2-bit operand pattern
1433 *   optn3 - 3-bit operand pattern
1434 *   sft4  - 4-bit shift amount
1435 *   strd2 - 2-bit stride amount
1436 *
1437 *  Prefixes:
1438 *
1439 *   Level of parallelism:                Operand size:
1440 *    S - single operation at a time       32 - word
1441 *    D - two operations in parallel       16 - half word
1442 *    Q - four operations in parallel       8 - byte
1443 *
1444 *  Operations:
1445 *
1446 *   ADD   - Add or subtract
1447 *   ADDC  - Add with carry-in
1448 *   ACC   - Accumulate
1449 *   ASUM  - Sum together then accumulate (add or subtract)
1450 *   ASUMC - Sum together then accumulate (add or subtract) with carry-in
1451 *   AVG   - Average between 2 operands
1452 *   ABD   - Absolute difference
1453 *   ALN   - Align data
1454 *   AND   - Logical bitwise 'and' operation
1455 *   CPS   - Copy sign
1456 *   EXTR  - Extract bits
1457 *   I2M   - Move from GPR register to MXU register
1458 *   LDD   - Load data from memory to XRF
1459 *   LDI   - Load data from memory to XRF (and increase the address base)
1460 *   LUI   - Load unsigned immediate
1461 *   MUL   - Multiply
1462 *   MULU  - Unsigned multiply
1463 *   MADD  - 64-bit operand add 32x32 product
1464 *   MSUB  - 64-bit operand subtract 32x32 product
1465 *   MAC   - Multiply and accumulate (add or subtract)
1466 *   MAD   - Multiply and add or subtract
1467 *   MAX   - Maximum between 2 operands
1468 *   MIN   - Minimum between 2 operands
1469 *   M2I   - Move from MXU register to GPR register
1470 *   MOVZ  - Move if zero
1471 *   MOVN  - Move if non-zero
1472 *   NOR   - Logical bitwise 'nor' operation
1473 *   OR    - Logical bitwise 'or' operation
1474 *   STD   - Store data from XRF to memory
1475 *   SDI   - Store data from XRF to memory (and increase the address base)
1476 *   SLT   - Set of less than comparison
1477 *   SAD   - Sum of absolute differences
1478 *   SLL   - Logical shift left
1479 *   SLR   - Logical shift right
1480 *   SAR   - Arithmetic shift right
1481 *   SAT   - Saturation
1482 *   SFL   - Shuffle
1483 *   SCOP  - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0)
1484 *   XOR   - Logical bitwise 'exclusive or' operation
1485 *
1486 *  Suffixes:
1487 *
1488 *   E - Expand results
1489 *   F - Fixed point multiplication
1490 *   L - Low part result
1491 *   R - Doing rounding
1492 *   V - Variable instead of immediate
1493 *   W - Combine above L and V
1494 *
1495 *
1496 *     The list of MXU instructions grouped by functionality
1497 *     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1498 *
1499 * Load/Store instructions           Multiplication instructions
1500 * -----------------------           ---------------------------
1501 *
1502 *  S32LDD XRa, Rb, s12               S32MADD XRa, XRd, Rs, Rt
1503 *  S32STD XRa, Rb, s12               S32MADDU XRa, XRd, Rs, Rt
1504 *  S32LDDV XRa, Rb, rc, strd2        S32MSUB XRa, XRd, Rs, Rt
1505 *  S32STDV XRa, Rb, rc, strd2        S32MSUBU XRa, XRd, Rs, Rt
1506 *  S32LDI XRa, Rb, s12               S32MUL XRa, XRd, Rs, Rt
1507 *  S32SDI XRa, Rb, s12               S32MULU XRa, XRd, Rs, Rt
1508 *  S32LDIV XRa, Rb, rc, strd2        D16MUL XRa, XRb, XRc, XRd, optn2
1509 *  S32SDIV XRa, Rb, rc, strd2        D16MULE XRa, XRb, XRc, optn2
1510 *  S32LDDR XRa, Rb, s12              D16MULF XRa, XRb, XRc, optn2
1511 *  S32STDR XRa, Rb, s12              D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
1512 *  S32LDDVR XRa, Rb, rc, strd2       D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
1513 *  S32STDVR XRa, Rb, rc, strd2       D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
1514 *  S32LDIR XRa, Rb, s12              D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
1515 *  S32SDIR XRa, Rb, s12              S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
1516 *  S32LDIVR XRa, Rb, rc, strd2       Q8MUL XRa, XRb, XRc, XRd
1517 *  S32SDIVR XRa, Rb, rc, strd2       Q8MULSU XRa, XRb, XRc, XRd
1518 *  S16LDD XRa, Rb, s10, eptn2        Q8MAC XRa, XRb, XRc, XRd, aptn2
1519 *  S16STD XRa, Rb, s10, eptn2        Q8MACSU XRa, XRb, XRc, XRd, aptn2
1520 *  S16LDI XRa, Rb, s10, eptn2        Q8MADL XRa, XRb, XRc, XRd, aptn2
1521 *  S16SDI XRa, Rb, s10, eptn2
1522 *  S8LDD XRa, Rb, s8, eptn3
1523 *  S8STD XRa, Rb, s8, eptn3         Addition and subtraction instructions
1524 *  S8LDI XRa, Rb, s8, eptn3         -------------------------------------
1525 *  S8SDI XRa, Rb, s8, eptn3
1526 *  LXW Rd, Rs, Rt, strd2             D32ADD XRa, XRb, XRc, XRd, eptn2
1527 *  LXH Rd, Rs, Rt, strd2             D32ADDC XRa, XRb, XRc, XRd
1528 *  LXHU Rd, Rs, Rt, strd2            D32ACC XRa, XRb, XRc, XRd, eptn2
1529 *  LXB Rd, Rs, Rt, strd2             D32ACCM XRa, XRb, XRc, XRd, eptn2
1530 *  LXBU Rd, Rs, Rt, strd2            D32ASUM XRa, XRb, XRc, XRd, eptn2
1531 *                                    S32CPS XRa, XRb, XRc
1532 *                                    Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
1533 * Comparison instructions            Q16ACC XRa, XRb, XRc, XRd, eptn2
1534 * -----------------------            Q16ACCM XRa, XRb, XRc, XRd, eptn2
1535 *                                    D16ASUM XRa, XRb, XRc, XRd, eptn2
1536 *  S32MAX XRa, XRb, XRc              D16CPS XRa, XRb,
1537 *  S32MIN XRa, XRb, XRc              D16AVG XRa, XRb, XRc
1538 *  S32SLT XRa, XRb, XRc              D16AVGR XRa, XRb, XRc
1539 *  S32MOVZ XRa, XRb, XRc             Q8ADD XRa, XRb, XRc, eptn2
1540 *  S32MOVN XRa, XRb, XRc             Q8ADDE XRa, XRb, XRc, XRd, eptn2
1541 *  D16MAX XRa, XRb, XRc              Q8ACCE XRa, XRb, XRc, XRd, eptn2
1542 *  D16MIN XRa, XRb, XRc              Q8ABD XRa, XRb, XRc
1543 *  D16SLT XRa, XRb, XRc              Q8SAD XRa, XRb, XRc, XRd
1544 *  D16MOVZ XRa, XRb, XRc             Q8AVG XRa, XRb, XRc
1545 *  D16MOVN XRa, XRb, XRc             Q8AVGR XRa, XRb, XRc
1546 *  Q8MAX XRa, XRb, XRc               D8SUM XRa, XRb, XRc, XRd
1547 *  Q8MIN XRa, XRb, XRc               D8SUMC XRa, XRb, XRc, XRd
1548 *  Q8SLT XRa, XRb, XRc
1549 *  Q8SLTU XRa, XRb, XRc
1550 *  Q8MOVZ XRa, XRb, XRc             Shift instructions
1551 *  Q8MOVN XRa, XRb, XRc             ------------------
1552 *
1553 *                                    D32SLL XRa, XRb, XRc, XRd, sft4
1554 * Bitwise instructions               D32SLR XRa, XRb, XRc, XRd, sft4
1555 * --------------------               D32SAR XRa, XRb, XRc, XRd, sft4
1556 *                                    D32SARL XRa, XRb, XRc, sft4
1557 *  S32NOR XRa, XRb, XRc              D32SLLV XRa, XRb, Rb
1558 *  S32AND XRa, XRb, XRc              D32SLRV XRa, XRb, Rb
1559 *  S32XOR XRa, XRb, XRc              D32SARV XRa, XRb, Rb
1560 *  S32OR XRa, XRb, XRc               D32SARW XRa, XRb, XRc, Rb
1561 *                                    Q16SLL XRa, XRb, XRc, XRd, sft4
1562 *                                    Q16SLR XRa, XRb, XRc, XRd, sft4
1563 * Miscellaneous instructions         Q16SAR XRa, XRb, XRc, XRd, sft4
1564 * -------------------------          Q16SLLV XRa, XRb, Rb
1565 *                                    Q16SLRV XRa, XRb, Rb
1566 *  S32SFL XRa, XRb, XRc, XRd, optn2  Q16SARV XRa, XRb, Rb
1567 *  S32ALN XRa, XRb, XRc, Rb
1568 *  S32ALNI XRa, XRb, XRc, s3
1569 *  S32LUI XRa, s8, optn3            Move instructions
1570 *  S32EXTR XRa, XRb, Rb, bits5      -----------------
1571 *  S32EXTRV XRa, XRb, Rs, Rt
1572 *  Q16SCOP XRa, XRb, XRc, XRd        S32M2I XRa, Rb
1573 *  Q16SAT XRa, XRb, XRc              S32I2M XRa, Rb
1574 *
1575 *
1576 *     The opcode organization of MXU instructions
1577 *     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1578 *
1579 * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred
1580 * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of
1581 * other bits up to the instruction level is as follows:
1582 *
1583 *              bits
1584 *             05..00
1585 *
1586 *          ┌─ 000000 ─ OPC_MXU_S32MADD
1587 *          ├─ 000001 ─ OPC_MXU_S32MADDU
1588 *          ├─ 000010 ─ <not assigned>   (non-MXU OPC_MUL)
1589 *          │
1590 *          │                               20..18
1591 *          ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
1592 *          │                            ├─ 001 ─ OPC_MXU_S32MIN
1593 *          │                            ├─ 010 ─ OPC_MXU_D16MAX
1594 *          │                            ├─ 011 ─ OPC_MXU_D16MIN
1595 *          │                            ├─ 100 ─ OPC_MXU_Q8MAX
1596 *          │                            ├─ 101 ─ OPC_MXU_Q8MIN
1597 *          │                            ├─ 110 ─ OPC_MXU_Q8SLT
1598 *          │                            └─ 111 ─ OPC_MXU_Q8SLTU
1599 *          ├─ 000100 ─ OPC_MXU_S32MSUB
1600 *          ├─ 000101 ─ OPC_MXU_S32MSUBU    20..18
1601 *          ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
1602 *          │                            ├─ 001 ─ OPC_MXU_D16SLT
1603 *          │                            ├─ 010 ─ OPC_MXU_D16AVG
1604 *          │                            ├─ 011 ─ OPC_MXU_D16AVGR
1605 *          │                            ├─ 100 ─ OPC_MXU_Q8AVG
1606 *          │                            ├─ 101 ─ OPC_MXU_Q8AVGR
1607 *          │                            └─ 111 ─ OPC_MXU_Q8ADD
1608 *          │
1609 *          │                               20..18
1610 *          ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
1611 *          │                            ├─ 010 ─ OPC_MXU_D16CPS
1612 *          │                            ├─ 100 ─ OPC_MXU_Q8ABD
1613 *          │                            └─ 110 ─ OPC_MXU_Q16SAT
1614 *          ├─ 001000 ─ OPC_MXU_D16MUL
1615 *          │                               25..24
1616 *          ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
1617 *          │                            └─ 01 ─ OPC_MXU_D16MULE
1618 *          ├─ 001010 ─ OPC_MXU_D16MAC
1619 *          ├─ 001011 ─ OPC_MXU_D16MACF
1620 *          ├─ 001100 ─ OPC_MXU_D16MADL
1621 *          ├─ 001101 ─ OPC_MXU_S16MAD
1622 *          ├─ 001110 ─ OPC_MXU_Q16ADD
1623 *          ├─ 001111 ─ OPC_MXU_D16MACE     23
1624 *          │                            ┌─ 0 ─ OPC_MXU_S32LDD
1625 *          ├─ 010000 ─ OPC_MXU__POOL04 ─┴─ 1 ─ OPC_MXU_S32LDDR
1626 *          │
1627 *          │                               23
1628 *          ├─ 010001 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32STD
1629 *          │                            └─ 1 ─ OPC_MXU_S32STDR
1630 *          │
1631 *          │                               13..10
1632 *          ├─ 010010 ─ OPC_MXU__POOL06 ─┬─ 0000 ─ OPC_MXU_S32LDDV
1633 *          │                            └─ 0001 ─ OPC_MXU_S32LDDVR
1634 *          │
1635 *          │                               13..10
1636 *          ├─ 010011 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32STDV
1637 *          │                            └─ 0001 ─ OPC_MXU_S32STDVR
1638 *          │
1639 *          │                               23
1640 *          ├─ 010100 ─ OPC_MXU__POOL08 ─┬─ 0 ─ OPC_MXU_S32LDI
1641 *          │                            └─ 1 ─ OPC_MXU_S32LDIR
1642 *          │
1643 *          │                               23
1644 *          ├─ 010101 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32SDI
1645 *          │                            └─ 1 ─ OPC_MXU_S32SDIR
1646 *          │
1647 *          │                               13..10
1648 *          ├─ 010110 ─ OPC_MXU__POOL10 ─┬─ 0000 ─ OPC_MXU_S32LDIV
1649 *          │                            └─ 0001 ─ OPC_MXU_S32LDIVR
1650 *          │
1651 *          │                               13..10
1652 *          ├─ 010111 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32SDIV
1653 *          │                            └─ 0001 ─ OPC_MXU_S32SDIVR
1654 *          ├─ 011000 ─ OPC_MXU_D32ADD
1655 *          │                               23..22
1656 *   MXU    ├─ 011001 ─ OPC_MXU__POOL12 ─┬─ 00 ─ OPC_MXU_D32ACC
1657 * opcodes ─┤                            ├─ 01 ─ OPC_MXU_D32ACCM
1658 *          │                            └─ 10 ─ OPC_MXU_D32ASUM
1659 *          ├─ 011010 ─ <not assigned>
1660 *          │                               23..22
1661 *          ├─ 011011 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_Q16ACC
1662 *          │                            ├─ 01 ─ OPC_MXU_Q16ACCM
1663 *          │                            └─ 10 ─ OPC_MXU_Q16ASUM
1664 *          │
1665 *          │                               23..22
1666 *          ├─ 011100 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q8ADDE
1667 *          │                            ├─ 01 ─ OPC_MXU_D8SUM
1668 *          ├─ 011101 ─ OPC_MXU_Q8ACCE   └─ 10 ─ OPC_MXU_D8SUMC
1669 *          ├─ 011110 ─ <not assigned>
1670 *          ├─ 011111 ─ <not assigned>
1671 *          ├─ 100000 ─ <not assigned>   (overlaps with CLZ)
1672 *          ├─ 100001 ─ <not assigned>   (overlaps with CLO)
1673 *          ├─ 100010 ─ OPC_MXU_S8LDD
1674 *          ├─ 100011 ─ OPC_MXU_S8STD       15..14
1675 *          ├─ 100100 ─ OPC_MXU_S8LDI    ┌─ 00 ─ OPC_MXU_S32MUL
1676 *          ├─ 100101 ─ OPC_MXU_S8SDI    ├─ 00 ─ OPC_MXU_S32MULU
1677 *          │                            ├─ 00 ─ OPC_MXU_S32EXTR
1678 *          ├─ 100110 ─ OPC_MXU__POOL15 ─┴─ 00 ─ OPC_MXU_S32EXTRV
1679 *          │
1680 *          │                               20..18
1681 *          ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
1682 *          │                            ├─ 001 ─ OPC_MXU_S32ALN
1683 *          │                            ├─ 010 ─ OPC_MXU_S32ALNI
1684 *          │                            ├─ 011 ─ OPC_MXU_S32LUI
1685 *          │                            ├─ 100 ─ OPC_MXU_S32NOR
1686 *          │                            ├─ 101 ─ OPC_MXU_S32AND
1687 *          │                            ├─ 110 ─ OPC_MXU_S32OR
1688 *          │                            └─ 111 ─ OPC_MXU_S32XOR
1689 *          │
1690 *          │                               7..5
1691 *          ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
1692 *          │                            ├─ 001 ─ OPC_MXU_LXH
1693 *          ├─ 101001 ─ <not assigned>   ├─ 011 ─ OPC_MXU_LXW
1694 *          ├─ 101010 ─ OPC_MXU_S16LDD   ├─ 100 ─ OPC_MXU_LXBU
1695 *          ├─ 101011 ─ OPC_MXU_S16STD   └─ 101 ─ OPC_MXU_LXHU
1696 *          ├─ 101100 ─ OPC_MXU_S16LDI
1697 *          ├─ 101101 ─ OPC_MXU_S16SDI
1698 *          ├─ 101110 ─ OPC_MXU_S32M2I
1699 *          ├─ 101111 ─ OPC_MXU_S32I2M
1700 *          ├─ 110000 ─ OPC_MXU_D32SLL
1701 *          ├─ 110001 ─ OPC_MXU_D32SLR      20..18
1702 *          ├─ 110010 ─ OPC_MXU_D32SARL  ┌─ 000 ─ OPC_MXU_D32SLLV
1703 *          ├─ 110011 ─ OPC_MXU_D32SAR   ├─ 001 ─ OPC_MXU_D32SLRV
1704 *          ├─ 110100 ─ OPC_MXU_Q16SLL   ├─ 010 ─ OPC_MXU_D32SARV
1705 *          ├─ 110101 ─ OPC_MXU_Q16SLR   ├─ 011 ─ OPC_MXU_Q16SLLV
1706 *          │                            ├─ 100 ─ OPC_MXU_Q16SLRV
1707 *          ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV
1708 *          │
1709 *          ├─ 110111 ─ OPC_MXU_Q16SAR
1710 *          │                               23..22
1711 *          ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
1712 *          │                            └─ 01 ─ OPC_MXU_Q8MULSU
1713 *          │
1714 *          │                               20..18
1715 *          ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
1716 *          │                            ├─ 001 ─ OPC_MXU_Q8MOVN
1717 *          │                            ├─ 010 ─ OPC_MXU_D16MOVZ
1718 *          │                            ├─ 011 ─ OPC_MXU_D16MOVN
1719 *          │                            ├─ 100 ─ OPC_MXU_S32MOVZ
1720 *          │                            └─ 101 ─ OPC_MXU_S32MOVN
1721 *          │
1722 *          │                               23..22
1723 *          ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
1724 *          │                            └─ 10 ─ OPC_MXU_Q8MACSU
1725 *          ├─ 111011 ─ OPC_MXU_Q16SCOP
1726 *          ├─ 111100 ─ OPC_MXU_Q8MADL
1727 *          ├─ 111101 ─ OPC_MXU_S32SFL
1728 *          ├─ 111110 ─ OPC_MXU_Q8SAD
1729 *          └─ 111111 ─ <not assigned>   (overlaps with SDBBP)
1730 *
1731 *
1732 * Compiled after:
1733 *
1734 *   "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
1735 *   Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2, 2017
1736 */
1737
1738enum {
1739    OPC_MXU_S32MADD  = 0x00,
1740    OPC_MXU_S32MADDU = 0x01,
1741    OPC__MXU_MUL     = 0x02,
1742    OPC_MXU__POOL00  = 0x03,
1743    OPC_MXU_S32MSUB  = 0x04,
1744    OPC_MXU_S32MSUBU = 0x05,
1745    OPC_MXU__POOL01  = 0x06,
1746    OPC_MXU__POOL02  = 0x07,
1747    OPC_MXU_D16MUL   = 0x08,
1748    OPC_MXU__POOL03  = 0x09,
1749    OPC_MXU_D16MAC   = 0x0A,
1750    OPC_MXU_D16MACF  = 0x0B,
1751    OPC_MXU_D16MADL  = 0x0C,
1752    OPC_MXU_S16MAD   = 0x0D,
1753    OPC_MXU_Q16ADD   = 0x0E,
1754    OPC_MXU_D16MACE  = 0x0F,
1755    OPC_MXU__POOL04  = 0x10,
1756    OPC_MXU__POOL05  = 0x11,
1757    OPC_MXU__POOL06  = 0x12,
1758    OPC_MXU__POOL07  = 0x13,
1759    OPC_MXU__POOL08  = 0x14,
1760    OPC_MXU__POOL09  = 0x15,
1761    OPC_MXU__POOL10  = 0x16,
1762    OPC_MXU__POOL11  = 0x17,
1763    OPC_MXU_D32ADD   = 0x18,
1764    OPC_MXU__POOL12  = 0x19,
1765    /* not assigned 0x1A */
1766    OPC_MXU__POOL13  = 0x1B,
1767    OPC_MXU__POOL14  = 0x1C,
1768    OPC_MXU_Q8ACCE   = 0x1D,
1769    /* not assigned 0x1E */
1770    /* not assigned 0x1F */
1771    /* not assigned 0x20 */
1772    /* not assigned 0x21 */
1773    OPC_MXU_S8LDD    = 0x22,
1774    OPC_MXU_S8STD    = 0x23,
1775    OPC_MXU_S8LDI    = 0x24,
1776    OPC_MXU_S8SDI    = 0x25,
1777    OPC_MXU__POOL15  = 0x26,
1778    OPC_MXU__POOL16  = 0x27,
1779    OPC_MXU__POOL17  = 0x28,
1780    /* not assigned 0x29 */
1781    OPC_MXU_S16LDD   = 0x2A,
1782    OPC_MXU_S16STD   = 0x2B,
1783    OPC_MXU_S16LDI   = 0x2C,
1784    OPC_MXU_S16SDI   = 0x2D,
1785    OPC_MXU_S32M2I   = 0x2E,
1786    OPC_MXU_S32I2M   = 0x2F,
1787    OPC_MXU_D32SLL   = 0x30,
1788    OPC_MXU_D32SLR   = 0x31,
1789    OPC_MXU_D32SARL  = 0x32,
1790    OPC_MXU_D32SAR   = 0x33,
1791    OPC_MXU_Q16SLL   = 0x34,
1792    OPC_MXU_Q16SLR   = 0x35,
1793    OPC_MXU__POOL18  = 0x36,
1794    OPC_MXU_Q16SAR   = 0x37,
1795    OPC_MXU__POOL19  = 0x38,
1796    OPC_MXU__POOL20  = 0x39,
1797    OPC_MXU__POOL21  = 0x3A,
1798    OPC_MXU_Q16SCOP  = 0x3B,
1799    OPC_MXU_Q8MADL   = 0x3C,
1800    OPC_MXU_S32SFL   = 0x3D,
1801    OPC_MXU_Q8SAD    = 0x3E,
1802    /* not assigned 0x3F */
1803};
1804
1805
1806/*
1807 * MXU pool 00
1808 */
1809enum {
1810    OPC_MXU_S32MAX   = 0x00,
1811    OPC_MXU_S32MIN   = 0x01,
1812    OPC_MXU_D16MAX   = 0x02,
1813    OPC_MXU_D16MIN   = 0x03,
1814    OPC_MXU_Q8MAX    = 0x04,
1815    OPC_MXU_Q8MIN    = 0x05,
1816    OPC_MXU_Q8SLT    = 0x06,
1817    OPC_MXU_Q8SLTU   = 0x07,
1818};
1819
1820/*
1821 * MXU pool 01
1822 */
1823enum {
1824    OPC_MXU_S32SLT   = 0x00,
1825    OPC_MXU_D16SLT   = 0x01,
1826    OPC_MXU_D16AVG   = 0x02,
1827    OPC_MXU_D16AVGR  = 0x03,
1828    OPC_MXU_Q8AVG    = 0x04,
1829    OPC_MXU_Q8AVGR   = 0x05,
1830    OPC_MXU_Q8ADD    = 0x07,
1831};
1832
1833/*
1834 * MXU pool 02
1835 */
1836enum {
1837    OPC_MXU_S32CPS   = 0x00,
1838    OPC_MXU_D16CPS   = 0x02,
1839    OPC_MXU_Q8ABD    = 0x04,
1840    OPC_MXU_Q16SAT   = 0x06,
1841};
1842
1843/*
1844 * MXU pool 03
1845 */
1846enum {
1847    OPC_MXU_D16MULF  = 0x00,
1848    OPC_MXU_D16MULE  = 0x01,
1849};
1850
1851/*
1852 * MXU pool 04
1853 */
1854enum {
1855    OPC_MXU_S32LDD   = 0x00,
1856    OPC_MXU_S32LDDR  = 0x01,
1857};
1858
1859/*
1860 * MXU pool 05
1861 */
1862enum {
1863    OPC_MXU_S32STD   = 0x00,
1864    OPC_MXU_S32STDR  = 0x01,
1865};
1866
1867/*
1868 * MXU pool 06
1869 */
1870enum {
1871    OPC_MXU_S32LDDV  = 0x00,
1872    OPC_MXU_S32LDDVR = 0x01,
1873};
1874
1875/*
1876 * MXU pool 07
1877 */
1878enum {
1879    OPC_MXU_S32STDV  = 0x00,
1880    OPC_MXU_S32STDVR = 0x01,
1881};
1882
1883/*
1884 * MXU pool 08
1885 */
1886enum {
1887    OPC_MXU_S32LDI   = 0x00,
1888    OPC_MXU_S32LDIR  = 0x01,
1889};
1890
1891/*
1892 * MXU pool 09
1893 */
1894enum {
1895    OPC_MXU_S32SDI   = 0x00,
1896    OPC_MXU_S32SDIR  = 0x01,
1897};
1898
1899/*
1900 * MXU pool 10
1901 */
1902enum {
1903    OPC_MXU_S32LDIV  = 0x00,
1904    OPC_MXU_S32LDIVR = 0x01,
1905};
1906
1907/*
1908 * MXU pool 11
1909 */
1910enum {
1911    OPC_MXU_S32SDIV  = 0x00,
1912    OPC_MXU_S32SDIVR = 0x01,
1913};
1914
1915/*
1916 * MXU pool 12
1917 */
1918enum {
1919    OPC_MXU_D32ACC   = 0x00,
1920    OPC_MXU_D32ACCM  = 0x01,
1921    OPC_MXU_D32ASUM  = 0x02,
1922};
1923
1924/*
1925 * MXU pool 13
1926 */
1927enum {
1928    OPC_MXU_Q16ACC   = 0x00,
1929    OPC_MXU_Q16ACCM  = 0x01,
1930    OPC_MXU_Q16ASUM  = 0x02,
1931};
1932
1933/*
1934 * MXU pool 14
1935 */
1936enum {
1937    OPC_MXU_Q8ADDE   = 0x00,
1938    OPC_MXU_D8SUM    = 0x01,
1939    OPC_MXU_D8SUMC   = 0x02,
1940};
1941
1942/*
1943 * MXU pool 15
1944 */
1945enum {
1946    OPC_MXU_S32MUL   = 0x00,
1947    OPC_MXU_S32MULU  = 0x01,
1948    OPC_MXU_S32EXTR  = 0x02,
1949    OPC_MXU_S32EXTRV = 0x03,
1950};
1951
1952/*
1953 * MXU pool 16
1954 */
1955enum {
1956    OPC_MXU_D32SARW  = 0x00,
1957    OPC_MXU_S32ALN   = 0x01,
1958    OPC_MXU_S32ALNI  = 0x02,
1959    OPC_MXU_S32LUI   = 0x03,
1960    OPC_MXU_S32NOR   = 0x04,
1961    OPC_MXU_S32AND   = 0x05,
1962    OPC_MXU_S32OR    = 0x06,
1963    OPC_MXU_S32XOR   = 0x07,
1964};
1965
1966/*
1967 * MXU pool 17
1968 */
1969enum {
1970    OPC_MXU_LXB      = 0x00,
1971    OPC_MXU_LXH      = 0x01,
1972    OPC_MXU_LXW      = 0x03,
1973    OPC_MXU_LXBU     = 0x04,
1974    OPC_MXU_LXHU     = 0x05,
1975};
1976
1977/*
1978 * MXU pool 18
1979 */
1980enum {
1981    OPC_MXU_D32SLLV  = 0x00,
1982    OPC_MXU_D32SLRV  = 0x01,
1983    OPC_MXU_D32SARV  = 0x03,
1984    OPC_MXU_Q16SLLV  = 0x04,
1985    OPC_MXU_Q16SLRV  = 0x05,
1986    OPC_MXU_Q16SARV  = 0x07,
1987};
1988
1989/*
1990 * MXU pool 19
1991 */
1992enum {
1993    OPC_MXU_Q8MUL    = 0x00,
1994    OPC_MXU_Q8MULSU  = 0x01,
1995};
1996
1997/*
1998 * MXU pool 20
1999 */
2000enum {
2001    OPC_MXU_Q8MOVZ   = 0x00,
2002    OPC_MXU_Q8MOVN   = 0x01,
2003    OPC_MXU_D16MOVZ  = 0x02,
2004    OPC_MXU_D16MOVN  = 0x03,
2005    OPC_MXU_S32MOVZ  = 0x04,
2006    OPC_MXU_S32MOVN  = 0x05,
2007};
2008
2009/*
2010 * MXU pool 21
2011 */
2012enum {
2013    OPC_MXU_Q8MAC    = 0x00,
2014    OPC_MXU_Q8MACSU  = 0x01,
2015};
2016
2017/*
2018 *     Overview of the TX79-specific instruction set
2019 *     =============================================
2020 *
2021 * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
2022 * are only used by the specific quadword (128-bit) LQ/SQ load/store
2023 * instructions and certain multimedia instructions (MMIs). These MMIs
2024 * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
2025 * or sixteen 8-bit paths.
2026 *
2027 * Reference:
2028 *
2029 * The Toshiba TX System RISC TX79 Core Architecture manual,
2030 * https://wiki.qemu.org/File:C790.pdf
2031 *
2032 *     Three-Operand Multiply and Multiply-Add (4 instructions)
2033 *     --------------------------------------------------------
2034 * MADD    [rd,] rs, rt      Multiply/Add
2035 * MADDU   [rd,] rs, rt      Multiply/Add Unsigned
2036 * MULT    [rd,] rs, rt      Multiply (3-operand)
2037 * MULTU   [rd,] rs, rt      Multiply Unsigned (3-operand)
2038 *
2039 *     Multiply Instructions for Pipeline 1 (10 instructions)
2040 *     ------------------------------------------------------
2041 * MULT1   [rd,] rs, rt      Multiply Pipeline 1
2042 * MULTU1  [rd,] rs, rt      Multiply Unsigned Pipeline 1
2043 * DIV1    rs, rt            Divide Pipeline 1
2044 * DIVU1   rs, rt            Divide Unsigned Pipeline 1
2045 * MADD1   [rd,] rs, rt      Multiply-Add Pipeline 1
2046 * MADDU1  [rd,] rs, rt      Multiply-Add Unsigned Pipeline 1
2047 * MFHI1   rd                Move From HI1 Register
2048 * MFLO1   rd                Move From LO1 Register
2049 * MTHI1   rs                Move To HI1 Register
2050 * MTLO1   rs                Move To LO1 Register
2051 *
2052 *     Arithmetic (19 instructions)
2053 *     ----------------------------
2054 * PADDB   rd, rs, rt        Parallel Add Byte
2055 * PSUBB   rd, rs, rt        Parallel Subtract Byte
2056 * PADDH   rd, rs, rt        Parallel Add Halfword
2057 * PSUBH   rd, rs, rt        Parallel Subtract Halfword
2058 * PADDW   rd, rs, rt        Parallel Add Word
2059 * PSUBW   rd, rs, rt        Parallel Subtract Word
2060 * PADSBH  rd, rs, rt        Parallel Add/Subtract Halfword
2061 * PADDSB  rd, rs, rt        Parallel Add with Signed Saturation Byte
2062 * PSUBSB  rd, rs, rt        Parallel Subtract with Signed Saturation Byte
2063 * PADDSH  rd, rs, rt        Parallel Add with Signed Saturation Halfword
2064 * PSUBSH  rd, rs, rt        Parallel Subtract with Signed Saturation Halfword
2065 * PADDSW  rd, rs, rt        Parallel Add with Signed Saturation Word
2066 * PSUBSW  rd, rs, rt        Parallel Subtract with Signed Saturation Word
2067 * PADDUB  rd, rs, rt        Parallel Add with Unsigned saturation Byte
2068 * PSUBUB  rd, rs, rt        Parallel Subtract with Unsigned saturation Byte
2069 * PADDUH  rd, rs, rt        Parallel Add with Unsigned saturation Halfword
2070 * PSUBUH  rd, rs, rt        Parallel Subtract with Unsigned saturation Halfword
2071 * PADDUW  rd, rs, rt        Parallel Add with Unsigned saturation Word
2072 * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
2073 *
2074 *     Min/Max (4 instructions)
2075 *     ------------------------
2076 * PMAXH   rd, rs, rt        Parallel Maximum Halfword
2077 * PMINH   rd, rs, rt        Parallel Minimum Halfword
2078 * PMAXW   rd, rs, rt        Parallel Maximum Word
2079 * PMINW   rd, rs, rt        Parallel Minimum Word
2080 *
2081 *     Absolute (2 instructions)
2082 *     -------------------------
2083 * PABSH   rd, rt            Parallel Absolute Halfword
2084 * PABSW   rd, rt            Parallel Absolute Word
2085 *
2086 *     Logical (4 instructions)
2087 *     ------------------------
2088 * PAND    rd, rs, rt        Parallel AND
2089 * POR     rd, rs, rt        Parallel OR
2090 * PXOR    rd, rs, rt        Parallel XOR
2091 * PNOR    rd, rs, rt        Parallel NOR
2092 *
2093 *     Shift (9 instructions)
2094 *     ----------------------
2095 * PSLLH   rd, rt, sa        Parallel Shift Left Logical Halfword
2096 * PSRLH   rd, rt, sa        Parallel Shift Right Logical Halfword
2097 * PSRAH   rd, rt, sa        Parallel Shift Right Arithmetic Halfword
2098 * PSLLW   rd, rt, sa        Parallel Shift Left Logical Word
2099 * PSRLW   rd, rt, sa        Parallel Shift Right Logical Word
2100 * PSRAW   rd, rt, sa        Parallel Shift Right Arithmetic Word
2101 * PSLLVW  rd, rt, rs        Parallel Shift Left Logical Variable Word
2102 * PSRLVW  rd, rt, rs        Parallel Shift Right Logical Variable Word
2103 * PSRAVW  rd, rt, rs        Parallel Shift Right Arithmetic Variable Word
2104 *
2105 *     Compare (6 instructions)
2106 *     ------------------------
2107 * PCGTB   rd, rs, rt        Parallel Compare for Greater Than Byte
2108 * PCEQB   rd, rs, rt        Parallel Compare for Equal Byte
2109 * PCGTH   rd, rs, rt        Parallel Compare for Greater Than Halfword
2110 * PCEQH   rd, rs, rt        Parallel Compare for Equal Halfword
2111 * PCGTW   rd, rs, rt        Parallel Compare for Greater Than Word
2112 * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
2113 *
2114 *     LZC (1 instruction)
2115 *     -------------------
2116 * PLZCW   rd, rs            Parallel Leading Zero or One Count Word
2117 *
2118 *     Quadword Load and Store (2 instructions)
2119 *     ----------------------------------------
2120 * LQ      rt, offset(base)  Load Quadword
2121 * SQ      rt, offset(base)  Store Quadword
2122 *
2123 *     Multiply and Divide (19 instructions)
2124 *     -------------------------------------
2125 * PMULTW  rd, rs, rt        Parallel Multiply Word
2126 * PMULTUW rd, rs, rt        Parallel Multiply Unsigned Word
2127 * PDIVW   rs, rt            Parallel Divide Word
2128 * PDIVUW  rs, rt            Parallel Divide Unsigned Word
2129 * PMADDW  rd, rs, rt        Parallel Multiply-Add Word
2130 * PMADDUW rd, rs, rt        Parallel Multiply-Add Unsigned Word
2131 * PMSUBW  rd, rs, rt        Parallel Multiply-Subtract Word
2132 * PMULTH  rd, rs, rt        Parallel Multiply Halfword
2133 * PMADDH  rd, rs, rt        Parallel Multiply-Add Halfword
2134 * PMSUBH  rd, rs, rt        Parallel Multiply-Subtract Halfword
2135 * PHMADH  rd, rs, rt        Parallel Horizontal Multiply-Add Halfword
2136 * PHMSBH  rd, rs, rt        Parallel Horizontal Multiply-Subtract Halfword
2137 * PDIVBW  rs, rt            Parallel Divide Broadcast Word
2138 * PMFHI   rd                Parallel Move From HI Register
2139 * PMFLO   rd                Parallel Move From LO Register
2140 * PMTHI   rs                Parallel Move To HI Register
2141 * PMTLO   rs                Parallel Move To LO Register
2142 * PMFHL   rd                Parallel Move From HI/LO Register
2143 * PMTHL   rs                Parallel Move To HI/LO Register
2144 *
2145 *     Pack/Extend (11 instructions)
2146 *     -----------------------------
2147 * PPAC5   rd, rt            Parallel Pack to 5 bits
2148 * PPACB   rd, rs, rt        Parallel Pack to Byte
2149 * PPACH   rd, rs, rt        Parallel Pack to Halfword
2150 * PPACW   rd, rs, rt        Parallel Pack to Word
2151 * PEXT5   rd, rt            Parallel Extend Upper from 5 bits
2152 * PEXTUB  rd, rs, rt        Parallel Extend Upper from Byte
2153 * PEXTLB  rd, rs, rt        Parallel Extend Lower from Byte
2154 * PEXTUH  rd, rs, rt        Parallel Extend Upper from Halfword
2155 * PEXTLH  rd, rs, rt        Parallel Extend Lower from Halfword
2156 * PEXTUW  rd, rs, rt        Parallel Extend Upper from Word
2157 * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
2158 *
2159 *     Others (16 instructions)
2160 *     ------------------------
2161 * PCPYH   rd, rt            Parallel Copy Halfword
2162 * PCPYLD  rd, rs, rt        Parallel Copy Lower Doubleword
2163 * PCPYUD  rd, rs, rt        Parallel Copy Upper Doubleword
2164 * PREVH   rd, rt            Parallel Reverse Halfword
2165 * PINTH   rd, rs, rt        Parallel Interleave Halfword
2166 * PINTEH  rd, rs, rt        Parallel Interleave Even Halfword
2167 * PEXEH   rd, rt            Parallel Exchange Even Halfword
2168 * PEXCH   rd, rt            Parallel Exchange Center Halfword
2169 * PEXEW   rd, rt            Parallel Exchange Even Word
2170 * PEXCW   rd, rt            Parallel Exchange Center Word
2171 * QFSRV   rd, rs, rt        Quadword Funnel Shift Right Variable
2172 * MFSA    rd                Move from Shift Amount Register
2173 * MTSA    rs                Move to Shift Amount Register
2174 * MTSAB   rs, immediate     Move Byte Count to Shift Amount Register
2175 * MTSAH   rs, immediate     Move Halfword Count to Shift Amount Register
2176 * PROT3W  rd, rt            Parallel Rotate 3 Words
2177 *
2178 *     MMI (MultiMedia Instruction) encodings
2179 *     ======================================
2180 *
2181 * MMI instructions encoding table keys:
2182 *
2183 *     *   This code is reserved for future use. An attempt to execute it
2184 *         causes a Reserved Instruction exception.
2185 *     %   This code indicates an instruction class. The instruction word
2186 *         must be further decoded by examining additional tables that show
2187 *         the values for other instruction fields.
2188 *     #   This code is reserved for the unsupported instructions DMULT,
2189 *         DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
2190 *         to execute it causes a Reserved Instruction exception.
2191 *
2192 * MMI instructions encoded by opcode field (MMI, LQ, SQ):
2193 *
2194 *  31    26                                        0
2195 * +--------+----------------------------------------+
2196 * | opcode |                                        |
2197 * +--------+----------------------------------------+
2198 *
2199 *   opcode  bits 28..26
2200 *     bits |   0   |   1   |   2   |   3   |   4   |   5   |   6   |   7
2201 *   31..29 |  000  |  001  |  010  |  011  |  100  |  101  |  110  |  111
2202 *   -------+-------+-------+-------+-------+-------+-------+-------+-------
2203 *    0 000 |SPECIAL| REGIMM|   J   |  JAL  |  BEQ  |  BNE  |  BLEZ |  BGTZ
2204 *    1 001 |  ADDI | ADDIU |  SLTI | SLTIU |  ANDI |  ORI  |  XORI |  LUI
2205 *    2 010 |  COP0 |  COP1 |   *   |   *   |  BEQL |  BNEL | BLEZL | BGTZL
2206 *    3 011 | DADDI | DADDIU|  LDL  |  LDR  |  MMI% |   *   |   LQ  |   SQ
2207 *    4 100 |   LB  |   LH  |  LWL  |   LW  |  LBU  |  LHU  |  LWR  |  LWU
2208 *    5 101 |   SB  |   SH  |  SWL  |   SW  |  SDL  |  SDR  |  SWR  | CACHE
2209 *    6 110 |   #   |  LWC1 |   #   |  PREF |   #   |  LDC1 |   #   |   LD
2210 *    7 111 |   #   |  SWC1 |   #   |   *   |   #   |  SDC1 |   #   |   SD
2211 */
2212
2213enum {
2214    MMI_OPC_CLASS_MMI = 0x1C << 26,    /* Same as OPC_SPECIAL2 */
2215    MMI_OPC_LQ        = 0x1E << 26,    /* Same as OPC_MSA */
2216    MMI_OPC_SQ        = 0x1F << 26,    /* Same as OPC_SPECIAL3 */
2217};
2218
2219/*
2220 * MMI instructions with opcode field = MMI:
2221 *
2222 *  31    26                                 5      0
2223 * +--------+-------------------------------+--------+
2224 * |   MMI  |                               |function|
2225 * +--------+-------------------------------+--------+
2226 *
2227 * function  bits 2..0
2228 *     bits |   0   |   1   |   2   |   3   |   4   |   5   |   6   |   7
2229 *     5..3 |  000  |  001  |  010  |  011  |  100  |  101  |  110  |  111
2230 *   -------+-------+-------+-------+-------+-------+-------+-------+-------
2231 *    0 000 |  MADD | MADDU |   *   |   *   | PLZCW |   *   |   *   |   *
2232 *    1 001 | MMI0% | MMI2% |   *   |   *   |   *   |   *   |   *   |   *
2233 *    2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 |   *   |   *   |   *   |   *
2234 *    3 011 | MULT1 | MULTU1|  DIV1 | DIVU1 |   *   |   *   |   *   |   *
2235 *    4 100 | MADD1 | MADDU1|   *   |   *   |   *   |   *   |   *   |   *
2236 *    5 101 | MMI1% | MMI3% |   *   |   *   |   *   |   *   |   *   |   *
2237 *    6 110 | PMFHL | PMTHL |   *   |   *   | PSLLH |   *   | PSRLH | PSRAH
2238 *    7 111 |   *   |   *   |   *   |   *   | PSLLW |   *   | PSRLW | PSRAW
2239 */
2240
2241#define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
2242enum {
2243    MMI_OPC_MADD       = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
2244    MMI_OPC_MADDU      = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
2245    MMI_OPC_PLZCW      = 0x04 | MMI_OPC_CLASS_MMI,
2246    MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
2247    MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
2248    MMI_OPC_MFHI1      = 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFHI */
2249    MMI_OPC_MTHI1      = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
2250    MMI_OPC_MFLO1      = 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFLO */
2251    MMI_OPC_MTLO1      = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
2252    MMI_OPC_MULT1      = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
2253    MMI_OPC_MULTU1     = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
2254    MMI_OPC_DIV1       = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV  */
2255    MMI_OPC_DIVU1      = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
2256    MMI_OPC_MADD1      = 0x20 | MMI_OPC_CLASS_MMI,
2257    MMI_OPC_MADDU1     = 0x21 | MMI_OPC_CLASS_MMI,
2258    MMI_OPC_CLASS_MMI1 = 0x28 | MMI_OPC_CLASS_MMI,
2259    MMI_OPC_CLASS_MMI3 = 0x29 | MMI_OPC_CLASS_MMI,
2260    MMI_OPC_PMFHL      = 0x30 | MMI_OPC_CLASS_MMI,
2261    MMI_OPC_PMTHL      = 0x31 | MMI_OPC_CLASS_MMI,
2262    MMI_OPC_PSLLH      = 0x34 | MMI_OPC_CLASS_MMI,
2263    MMI_OPC_PSRLH      = 0x36 | MMI_OPC_CLASS_MMI,
2264    MMI_OPC_PSRAH      = 0x37 | MMI_OPC_CLASS_MMI,
2265    MMI_OPC_PSLLW      = 0x3C | MMI_OPC_CLASS_MMI,
2266    MMI_OPC_PSRLW      = 0x3E | MMI_OPC_CLASS_MMI,
2267    MMI_OPC_PSRAW      = 0x3F | MMI_OPC_CLASS_MMI,
2268};
2269
2270/*
2271 * MMI instructions with opcode field = MMI and bits 5..0 = MMI0:
2272 *
2273 *  31    26                        10     6 5      0
2274 * +--------+----------------------+--------+--------+
2275 * |   MMI  |                      |function|  MMI0  |
2276 * +--------+----------------------+--------+--------+
2277 *
2278 * function  bits 7..6
2279 *     bits |   0   |   1   |   2   |   3
2280 *    10..8 |   00  |   01  |   10  |   11
2281 *   -------+-------+-------+-------+-------
2282 *    0 000 | PADDW | PSUBW | PCGTW | PMAXW
2283 *    1 001 | PADDH | PSUBH | PCGTH | PMAXH
2284 *    2 010 | PADDB | PSUBB | PCGTB |   *
2285 *    3 011 |   *   |   *   |   *   |   *
2286 *    4 100 | PADDSW| PSUBSW| PEXTLW| PPACW
2287 *    5 101 | PADDSH| PSUBSH| PEXTLH| PPACH
2288 *    6 110 | PADDSB| PSUBSB| PEXTLB| PPACB
2289 *    7 111 |   *   |   *   | PEXT5 | PPAC5
2290 */
2291
2292#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2293enum {
2294    MMI_OPC_0_PADDW  = (0x00 << 6) | MMI_OPC_CLASS_MMI0,
2295    MMI_OPC_0_PSUBW  = (0x01 << 6) | MMI_OPC_CLASS_MMI0,
2296    MMI_OPC_0_PCGTW  = (0x02 << 6) | MMI_OPC_CLASS_MMI0,
2297    MMI_OPC_0_PMAXW  = (0x03 << 6) | MMI_OPC_CLASS_MMI0,
2298    MMI_OPC_0_PADDH  = (0x04 << 6) | MMI_OPC_CLASS_MMI0,
2299    MMI_OPC_0_PSUBH  = (0x05 << 6) | MMI_OPC_CLASS_MMI0,
2300    MMI_OPC_0_PCGTH  = (0x06 << 6) | MMI_OPC_CLASS_MMI0,
2301    MMI_OPC_0_PMAXH  = (0x07 << 6) | MMI_OPC_CLASS_MMI0,
2302    MMI_OPC_0_PADDB  = (0x08 << 6) | MMI_OPC_CLASS_MMI0,
2303    MMI_OPC_0_PSUBB  = (0x09 << 6) | MMI_OPC_CLASS_MMI0,
2304    MMI_OPC_0_PCGTB  = (0x0A << 6) | MMI_OPC_CLASS_MMI0,
2305    MMI_OPC_0_PADDSW = (0x10 << 6) | MMI_OPC_CLASS_MMI0,
2306    MMI_OPC_0_PSUBSW = (0x11 << 6) | MMI_OPC_CLASS_MMI0,
2307    MMI_OPC_0_PEXTLW = (0x12 << 6) | MMI_OPC_CLASS_MMI0,
2308    MMI_OPC_0_PPACW  = (0x13 << 6) | MMI_OPC_CLASS_MMI0,
2309    MMI_OPC_0_PADDSH = (0x14 << 6) | MMI_OPC_CLASS_MMI0,
2310    MMI_OPC_0_PSUBSH = (0x15 << 6) | MMI_OPC_CLASS_MMI0,
2311    MMI_OPC_0_PEXTLH = (0x16 << 6) | MMI_OPC_CLASS_MMI0,
2312    MMI_OPC_0_PPACH  = (0x17 << 6) | MMI_OPC_CLASS_MMI0,
2313    MMI_OPC_0_PADDSB = (0x18 << 6) | MMI_OPC_CLASS_MMI0,
2314    MMI_OPC_0_PSUBSB = (0x19 << 6) | MMI_OPC_CLASS_MMI0,
2315    MMI_OPC_0_PEXTLB = (0x1A << 6) | MMI_OPC_CLASS_MMI0,
2316    MMI_OPC_0_PPACB  = (0x1B << 6) | MMI_OPC_CLASS_MMI0,
2317    MMI_OPC_0_PEXT5  = (0x1E << 6) | MMI_OPC_CLASS_MMI0,
2318    MMI_OPC_0_PPAC5  = (0x1F << 6) | MMI_OPC_CLASS_MMI0,
2319};
2320
2321/*
2322 * MMI instructions with opcode field = MMI and bits 5..0 = MMI1:
2323 *
2324 *  31    26                        10     6 5      0
2325 * +--------+----------------------+--------+--------+
2326 * |   MMI  |                      |function|  MMI1  |
2327 * +--------+----------------------+--------+--------+
2328 *
2329 * function  bits 7..6
2330 *     bits |   0   |   1   |   2   |   3
2331 *    10..8 |   00  |   01  |   10  |   11
2332 *   -------+-------+-------+-------+-------
2333 *    0 000 |   *   | PABSW | PCEQW | PMINW
2334 *    1 001 | PADSBH| PABSH | PCEQH | PMINH
2335 *    2 010 |   *   |   *   | PCEQB |   *
2336 *    3 011 |   *   |   *   |   *   |   *
2337 *    4 100 | PADDUW| PSUBUW| PEXTUW|   *
2338 *    5 101 | PADDUH| PSUBUH| PEXTUH|   *
2339 *    6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV
2340 *    7 111 |   *   |   *   |   *   |   *
2341 */
2342
2343#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2344enum {
2345    MMI_OPC_1_PABSW  = (0x01 << 6) | MMI_OPC_CLASS_MMI1,
2346    MMI_OPC_1_PCEQW  = (0x02 << 6) | MMI_OPC_CLASS_MMI1,
2347    MMI_OPC_1_PMINW  = (0x03 << 6) | MMI_OPC_CLASS_MMI1,
2348    MMI_OPC_1_PADSBH = (0x04 << 6) | MMI_OPC_CLASS_MMI1,
2349    MMI_OPC_1_PABSH  = (0x05 << 6) | MMI_OPC_CLASS_MMI1,
2350    MMI_OPC_1_PCEQH  = (0x06 << 6) | MMI_OPC_CLASS_MMI1,
2351    MMI_OPC_1_PMINH  = (0x07 << 6) | MMI_OPC_CLASS_MMI1,
2352    MMI_OPC_1_PCEQB  = (0x0A << 6) | MMI_OPC_CLASS_MMI1,
2353    MMI_OPC_1_PADDUW = (0x10 << 6) | MMI_OPC_CLASS_MMI1,
2354    MMI_OPC_1_PSUBUW = (0x11 << 6) | MMI_OPC_CLASS_MMI1,
2355    MMI_OPC_1_PEXTUW = (0x12 << 6) | MMI_OPC_CLASS_MMI1,
2356    MMI_OPC_1_PADDUH = (0x14 << 6) | MMI_OPC_CLASS_MMI1,
2357    MMI_OPC_1_PSUBUH = (0x15 << 6) | MMI_OPC_CLASS_MMI1,
2358    MMI_OPC_1_PEXTUH = (0x16 << 6) | MMI_OPC_CLASS_MMI1,
2359    MMI_OPC_1_PADDUB = (0x18 << 6) | MMI_OPC_CLASS_MMI1,
2360    MMI_OPC_1_PSUBUB = (0x19 << 6) | MMI_OPC_CLASS_MMI1,
2361    MMI_OPC_1_PEXTUB = (0x1A << 6) | MMI_OPC_CLASS_MMI1,
2362    MMI_OPC_1_QFSRV  = (0x1B << 6) | MMI_OPC_CLASS_MMI1,
2363};
2364
2365/*
2366 * MMI instructions with opcode field = MMI and bits 5..0 = MMI2:
2367 *
2368 *  31    26                        10     6 5      0
2369 * +--------+----------------------+--------+--------+
2370 * |   MMI  |                      |function|  MMI2  |
2371 * +--------+----------------------+--------+--------+
2372 *
2373 * function  bits 7..6
2374 *     bits |   0   |   1   |   2   |   3
2375 *    10..8 |   00  |   01  |   10  |   11
2376 *   -------+-------+-------+-------+-------
2377 *    0 000 | PMADDW|   *   | PSLLVW| PSRLVW
2378 *    1 001 | PMSUBW|   *   |   *   |   *
2379 *    2 010 | PMFHI | PMFLO | PINTH |   *
2380 *    3 011 | PMULTW| PDIVW | PCPYLD|   *
2381 *    4 100 | PMADDH| PHMADH|  PAND |  PXOR
2382 *    5 101 | PMSUBH| PHMSBH|   *   |   *
2383 *    6 110 |   *   |   *   | PEXEH | PREVH
2384 *    7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
2385 */
2386
2387#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2388enum {
2389    MMI_OPC_2_PMADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI2,
2390    MMI_OPC_2_PSLLVW = (0x02 << 6) | MMI_OPC_CLASS_MMI2,
2391    MMI_OPC_2_PSRLVW = (0x03 << 6) | MMI_OPC_CLASS_MMI2,
2392    MMI_OPC_2_PMSUBW = (0x04 << 6) | MMI_OPC_CLASS_MMI2,
2393    MMI_OPC_2_PMFHI  = (0x08 << 6) | MMI_OPC_CLASS_MMI2,
2394    MMI_OPC_2_PMFLO  = (0x09 << 6) | MMI_OPC_CLASS_MMI2,
2395    MMI_OPC_2_PINTH  = (0x0A << 6) | MMI_OPC_CLASS_MMI2,
2396    MMI_OPC_2_PMULTW = (0x0C << 6) | MMI_OPC_CLASS_MMI2,
2397    MMI_OPC_2_PDIVW  = (0x0D << 6) | MMI_OPC_CLASS_MMI2,
2398    MMI_OPC_2_PCPYLD = (0x0E << 6) | MMI_OPC_CLASS_MMI2,
2399    MMI_OPC_2_PMADDH = (0x10 << 6) | MMI_OPC_CLASS_MMI2,
2400    MMI_OPC_2_PHMADH = (0x11 << 6) | MMI_OPC_CLASS_MMI2,
2401    MMI_OPC_2_PAND   = (0x12 << 6) | MMI_OPC_CLASS_MMI2,
2402    MMI_OPC_2_PXOR   = (0x13 << 6) | MMI_OPC_CLASS_MMI2,
2403    MMI_OPC_2_PMSUBH = (0x14 << 6) | MMI_OPC_CLASS_MMI2,
2404    MMI_OPC_2_PHMSBH = (0x15 << 6) | MMI_OPC_CLASS_MMI2,
2405    MMI_OPC_2_PEXEH  = (0x1A << 6) | MMI_OPC_CLASS_MMI2,
2406    MMI_OPC_2_PREVH  = (0x1B << 6) | MMI_OPC_CLASS_MMI2,
2407    MMI_OPC_2_PMULTH = (0x1C << 6) | MMI_OPC_CLASS_MMI2,
2408    MMI_OPC_2_PDIVBW = (0x1D << 6) | MMI_OPC_CLASS_MMI2,
2409    MMI_OPC_2_PEXEW  = (0x1E << 6) | MMI_OPC_CLASS_MMI2,
2410    MMI_OPC_2_PROT3W = (0x1F << 6) | MMI_OPC_CLASS_MMI2,
2411};
2412
2413/*
2414 * MMI instructions with opcode field = MMI and bits 5..0 = MMI3:
2415 *
2416 *  31    26                        10     6 5      0
2417 * +--------+----------------------+--------+--------+
2418 * |   MMI  |                      |function|  MMI3  |
2419 * +--------+----------------------+--------+--------+
2420 *
2421 * function  bits 7..6
2422 *     bits |   0   |   1   |   2   |   3
2423 *    10..8 |   00  |   01  |   10  |   11
2424 *   -------+-------+-------+-------+-------
2425 *    0 000 |PMADDUW|   *   |   *   | PSRAVW
2426 *    1 001 |   *   |   *   |   *   |   *
2427 *    2 010 | PMTHI | PMTLO | PINTEH|   *
2428 *    3 011 |PMULTUW| PDIVUW| PCPYUD|   *
2429 *    4 100 |   *   |   *   |  POR  |  PNOR
2430 *    5 101 |   *   |   *   |   *   |   *
2431 *    6 110 |   *   |   *   | PEXCH | PCPYH
2432 *    7 111 |   *   |   *   | PEXCW |   *
2433 */
2434
2435#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2436enum {
2437    MMI_OPC_3_PMADDUW = (0x00 << 6) | MMI_OPC_CLASS_MMI3,
2438    MMI_OPC_3_PSRAVW  = (0x03 << 6) | MMI_OPC_CLASS_MMI3,
2439    MMI_OPC_3_PMTHI   = (0x08 << 6) | MMI_OPC_CLASS_MMI3,
2440    MMI_OPC_3_PMTLO   = (0x09 << 6) | MMI_OPC_CLASS_MMI3,
2441    MMI_OPC_3_PINTEH  = (0x0A << 6) | MMI_OPC_CLASS_MMI3,
2442    MMI_OPC_3_PMULTUW = (0x0C << 6) | MMI_OPC_CLASS_MMI3,
2443    MMI_OPC_3_PDIVUW  = (0x0D << 6) | MMI_OPC_CLASS_MMI3,
2444    MMI_OPC_3_PCPYUD  = (0x0E << 6) | MMI_OPC_CLASS_MMI3,
2445    MMI_OPC_3_POR     = (0x12 << 6) | MMI_OPC_CLASS_MMI3,
2446    MMI_OPC_3_PNOR    = (0x13 << 6) | MMI_OPC_CLASS_MMI3,
2447    MMI_OPC_3_PEXCH   = (0x1A << 6) | MMI_OPC_CLASS_MMI3,
2448    MMI_OPC_3_PCPYH   = (0x1B << 6) | MMI_OPC_CLASS_MMI3,
2449    MMI_OPC_3_PEXCW   = (0x1E << 6) | MMI_OPC_CLASS_MMI3,
2450};
2451
2452/* global register indices */
2453static TCGv cpu_gpr[32], cpu_PC;
2454static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
2455static TCGv cpu_dspctrl, btarget, bcond;
2456static TCGv cpu_lladdr, cpu_llval;
2457static TCGv_i32 hflags;
2458static TCGv_i32 fpu_fcr0, fpu_fcr31;
2459static TCGv_i64 fpu_f64[32];
2460static TCGv_i64 msa_wr_d[64];
2461
2462#if defined(TARGET_MIPS64)
2463/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
2464static TCGv_i64 cpu_mmr[32];
2465#endif
2466
2467#if !defined(TARGET_MIPS64)
2468/* MXU registers */
2469static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
2470static TCGv mxu_CR;
2471#endif
2472
2473#include "exec/gen-icount.h"
2474
2475#define gen_helper_0e0i(name, arg) do {                           \
2476    TCGv_i32 helper_tmp = tcg_const_i32(arg);                     \
2477    gen_helper_##name(cpu_env, helper_tmp);                       \
2478    tcg_temp_free_i32(helper_tmp);                                \
2479    } while (0)
2480
2481#define gen_helper_0e1i(name, arg1, arg2) do {                    \
2482    TCGv_i32 helper_tmp = tcg_const_i32(arg2);                    \
2483    gen_helper_##name(cpu_env, arg1, helper_tmp);                 \
2484    tcg_temp_free_i32(helper_tmp);                                \
2485    } while (0)
2486
2487#define gen_helper_1e0i(name, ret, arg1) do {                     \
2488    TCGv_i32 helper_tmp = tcg_const_i32(arg1);                    \
2489    gen_helper_##name(ret, cpu_env, helper_tmp);                  \
2490    tcg_temp_free_i32(helper_tmp);                                \
2491    } while (0)
2492
2493#define gen_helper_1e1i(name, ret, arg1, arg2) do {               \
2494    TCGv_i32 helper_tmp = tcg_const_i32(arg2);                    \
2495    gen_helper_##name(ret, cpu_env, arg1, helper_tmp);            \
2496    tcg_temp_free_i32(helper_tmp);                                \
2497    } while (0)
2498
2499#define gen_helper_0e2i(name, arg1, arg2, arg3) do {              \
2500    TCGv_i32 helper_tmp = tcg_const_i32(arg3);                    \
2501    gen_helper_##name(cpu_env, arg1, arg2, helper_tmp);           \
2502    tcg_temp_free_i32(helper_tmp);                                \
2503    } while (0)
2504
2505#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do {         \
2506    TCGv_i32 helper_tmp = tcg_const_i32(arg3);                    \
2507    gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp);      \
2508    tcg_temp_free_i32(helper_tmp);                                \
2509    } while (0)
2510
2511#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do {        \
2512    TCGv_i32 helper_tmp = tcg_const_i32(arg4);                    \
2513    gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp);     \
2514    tcg_temp_free_i32(helper_tmp);                                \
2515    } while (0)
2516
2517typedef struct DisasContext {
2518    DisasContextBase base;
2519    target_ulong saved_pc;
2520    target_ulong page_start;
2521    uint32_t opcode;
2522    uint64_t insn_flags;
2523    int32_t CP0_Config1;
2524    int32_t CP0_Config2;
2525    int32_t CP0_Config3;
2526    int32_t CP0_Config5;
2527    /* Routine used to access memory */
2528    int mem_idx;
2529    MemOp default_tcg_memop_mask;
2530    uint32_t hflags, saved_hflags;
2531    target_ulong btarget;
2532    bool ulri;
2533    int kscrexist;
2534    bool rxi;
2535    int ie;
2536    bool bi;
2537    bool bp;
2538    uint64_t PAMask;
2539    bool mvh;
2540    bool eva;
2541    bool sc;
2542    int CP0_LLAddr_shift;
2543    bool ps;
2544    bool vp;
2545    bool cmgcr;
2546    bool mrp;
2547    bool nan2008;
2548    bool abs2008;
2549    bool saar;
2550} DisasContext;
2551
2552#define DISAS_STOP       DISAS_TARGET_0
2553#define DISAS_EXIT       DISAS_TARGET_1
2554
2555static const char * const regnames[] = {
2556    "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2557    "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2558    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2559    "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
2560};
2561
2562static const char * const regnames_HI[] = {
2563    "HI0", "HI1", "HI2", "HI3",
2564};
2565
2566static const char * const regnames_LO[] = {
2567    "LO0", "LO1", "LO2", "LO3",
2568};
2569
2570static const char * const fregnames[] = {
2571    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
2572    "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
2573    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2574    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2575};
2576
2577static const char * const msaregnames[] = {
2578    "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
2579    "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
2580    "w4.d0",  "w4.d1",  "w5.d0",  "w5.d1",
2581    "w6.d0",  "w6.d1",  "w7.d0",  "w7.d1",
2582    "w8.d0",  "w8.d1",  "w9.d0",  "w9.d1",
2583    "w10.d0", "w10.d1", "w11.d0", "w11.d1",
2584    "w12.d0", "w12.d1", "w13.d0", "w13.d1",
2585    "w14.d0", "w14.d1", "w15.d0", "w15.d1",
2586    "w16.d0", "w16.d1", "w17.d0", "w17.d1",
2587    "w18.d0", "w18.d1", "w19.d0", "w19.d1",
2588    "w20.d0", "w20.d1", "w21.d0", "w21.d1",
2589    "w22.d0", "w22.d1", "w23.d0", "w23.d1",
2590    "w24.d0", "w24.d1", "w25.d0", "w25.d1",
2591    "w26.d0", "w26.d1", "w27.d0", "w27.d1",
2592    "w28.d0", "w28.d1", "w29.d0", "w29.d1",
2593    "w30.d0", "w30.d1", "w31.d0", "w31.d1",
2594};
2595
2596#if !defined(TARGET_MIPS64)
2597static const char * const mxuregnames[] = {
2598    "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
2599    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
2600};
2601#endif
2602
2603#define LOG_DISAS(...)                                                        \
2604    do {                                                                      \
2605        if (MIPS_DEBUG_DISAS) {                                               \
2606            qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
2607        }                                                                     \
2608    } while (0)
2609
2610#define MIPS_INVAL(op)                                                        \
2611    do {                                                                      \
2612        if (MIPS_DEBUG_DISAS) {                                               \
2613            qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
2614                          TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
2615                          ctx->base.pc_next, ctx->opcode, op,                 \
2616                          ctx->opcode >> 26, ctx->opcode & 0x3F,              \
2617                          ((ctx->opcode >> 16) & 0x1F));                      \
2618        }                                                                     \
2619    } while (0)
2620
2621/* General purpose registers moves. */
2622static inline void gen_load_gpr(TCGv t, int reg)
2623{
2624    if (reg == 0) {
2625        tcg_gen_movi_tl(t, 0);
2626    } else {
2627        tcg_gen_mov_tl(t, cpu_gpr[reg]);
2628    }
2629}
2630
2631static inline void gen_store_gpr(TCGv t, int reg)
2632{
2633    if (reg != 0) {
2634        tcg_gen_mov_tl(cpu_gpr[reg], t);
2635    }
2636}
2637
2638/* Moves to/from shadow registers. */
2639static inline void gen_load_srsgpr(int from, int to)
2640{
2641    TCGv t0 = tcg_temp_new();
2642
2643    if (from == 0) {
2644        tcg_gen_movi_tl(t0, 0);
2645    } else {
2646        TCGv_i32 t2 = tcg_temp_new_i32();
2647        TCGv_ptr addr = tcg_temp_new_ptr();
2648
2649        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
2650        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
2651        tcg_gen_andi_i32(t2, t2, 0xf);
2652        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
2653        tcg_gen_ext_i32_ptr(addr, t2);
2654        tcg_gen_add_ptr(addr, cpu_env, addr);
2655
2656        tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
2657        tcg_temp_free_ptr(addr);
2658        tcg_temp_free_i32(t2);
2659    }
2660    gen_store_gpr(t0, to);
2661    tcg_temp_free(t0);
2662}
2663
2664static inline void gen_store_srsgpr(int from, int to)
2665{
2666    if (to != 0) {
2667        TCGv t0 = tcg_temp_new();
2668        TCGv_i32 t2 = tcg_temp_new_i32();
2669        TCGv_ptr addr = tcg_temp_new_ptr();
2670
2671        gen_load_gpr(t0, from);
2672        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
2673        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
2674        tcg_gen_andi_i32(t2, t2, 0xf);
2675        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
2676        tcg_gen_ext_i32_ptr(addr, t2);
2677        tcg_gen_add_ptr(addr, cpu_env, addr);
2678
2679        tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
2680        tcg_temp_free_ptr(addr);
2681        tcg_temp_free_i32(t2);
2682        tcg_temp_free(t0);
2683    }
2684}
2685
2686#if !defined(TARGET_MIPS64)
2687/* MXU General purpose registers moves. */
2688static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg)
2689{
2690    if (reg == 0) {
2691        tcg_gen_movi_tl(t, 0);
2692    } else if (reg <= 15) {
2693        tcg_gen_mov_tl(t, mxu_gpr[reg - 1]);
2694    }
2695}
2696
2697static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg)
2698{
2699    if (reg > 0 && reg <= 15) {
2700        tcg_gen_mov_tl(mxu_gpr[reg - 1], t);
2701    }
2702}
2703
2704/* MXU control register moves. */
2705static inline void gen_load_mxu_cr(TCGv t)
2706{
2707    tcg_gen_mov_tl(t, mxu_CR);
2708}
2709
2710static inline void gen_store_mxu_cr(TCGv t)
2711{
2712    /* TODO: Add handling of RW rules for MXU_CR. */
2713    tcg_gen_mov_tl(mxu_CR, t);
2714}
2715#endif
2716
2717
2718/* Tests */
2719static inline void gen_save_pc(target_ulong pc)
2720{
2721    tcg_gen_movi_tl(cpu_PC, pc);
2722}
2723
2724static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
2725{
2726    LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
2727    if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
2728        gen_save_pc(ctx->base.pc_next);
2729        ctx->saved_pc = ctx->base.pc_next;
2730    }
2731    if (ctx->hflags != ctx->saved_hflags) {
2732        tcg_gen_movi_i32(hflags, ctx->hflags);
2733        ctx->saved_hflags = ctx->hflags;
2734        switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
2735        case MIPS_HFLAG_BR:
2736            break;
2737        case MIPS_HFLAG_BC:
2738        case MIPS_HFLAG_BL:
2739        case MIPS_HFLAG_B:
2740            tcg_gen_movi_tl(btarget, ctx->btarget);
2741            break;
2742        }
2743    }
2744}
2745
2746static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
2747{
2748    ctx->saved_hflags = ctx->hflags;
2749    switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
2750    case MIPS_HFLAG_BR:
2751        break;
2752    case MIPS_HFLAG_BC:
2753    case MIPS_HFLAG_BL:
2754    case MIPS_HFLAG_B:
2755        ctx->btarget = env->btarget;
2756        break;
2757    }
2758}
2759
2760static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
2761{
2762    TCGv_i32 texcp = tcg_const_i32(excp);
2763    TCGv_i32 terr = tcg_const_i32(err);
2764    save_cpu_state(ctx, 1);
2765    gen_helper_raise_exception_err(cpu_env, texcp, terr);
2766    tcg_temp_free_i32(terr);
2767    tcg_temp_free_i32(texcp);
2768    ctx->base.is_jmp = DISAS_NORETURN;
2769}
2770
2771static inline void generate_exception(DisasContext *ctx, int excp)
2772{
2773    gen_helper_0e0i(raise_exception, excp);
2774}
2775
2776static inline void generate_exception_end(DisasContext *ctx, int excp)
2777{
2778    generate_exception_err(ctx, excp, 0);
2779}
2780
2781/* Floating point register moves. */
2782static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
2783{
2784    if (ctx->hflags & MIPS_HFLAG_FRE) {
2785        generate_exception(ctx, EXCP_RI);
2786    }
2787    tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
2788}
2789
2790static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
2791{
2792    TCGv_i64 t64;
2793    if (ctx->hflags & MIPS_HFLAG_FRE) {
2794        generate_exception(ctx, EXCP_RI);
2795    }
2796    t64 = tcg_temp_new_i64();
2797    tcg_gen_extu_i32_i64(t64, t);
2798    tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
2799    tcg_temp_free_i64(t64);
2800}
2801
2802static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
2803{
2804    if (ctx->hflags & MIPS_HFLAG_F64) {
2805        tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
2806    } else {
2807        gen_load_fpr32(ctx, t, reg | 1);
2808    }
2809}
2810
2811static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
2812{
2813    if (ctx->hflags & MIPS_HFLAG_F64) {
2814        TCGv_i64 t64 = tcg_temp_new_i64();
2815        tcg_gen_extu_i32_i64(t64, t);
2816        tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
2817        tcg_temp_free_i64(t64);
2818    } else {
2819        gen_store_fpr32(ctx, t, reg | 1);
2820    }
2821}
2822
2823static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
2824{
2825    if (ctx->hflags & MIPS_HFLAG_F64) {
2826        tcg_gen_mov_i64(t, fpu_f64[reg]);
2827    } else {
2828        tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
2829    }
2830}
2831
2832static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
2833{
2834    if (ctx->hflags & MIPS_HFLAG_F64) {
2835        tcg_gen_mov_i64(fpu_f64[reg], t);
2836    } else {
2837        TCGv_i64 t0;
2838        tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
2839        t0 = tcg_temp_new_i64();
2840        tcg_gen_shri_i64(t0, t, 32);
2841        tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
2842        tcg_temp_free_i64(t0);
2843    }
2844}
2845
2846static inline int get_fp_bit(int cc)
2847{
2848    if (cc) {
2849        return 24 + cc;
2850    } else {
2851        return 23;
2852    }
2853}
2854
2855/* Addresses computation */
2856static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,
2857                                   TCGv arg1)
2858{
2859    tcg_gen_add_tl(ret, arg0, arg1);
2860
2861#if defined(TARGET_MIPS64)
2862    if (ctx->hflags & MIPS_HFLAG_AWRAP) {
2863        tcg_gen_ext32s_i64(ret, ret);
2864    }
2865#endif
2866}
2867
2868static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
2869                                    target_long ofs)
2870{
2871    tcg_gen_addi_tl(ret, base, ofs);
2872
2873#if defined(TARGET_MIPS64)
2874    if (ctx->hflags & MIPS_HFLAG_AWRAP) {
2875        tcg_gen_ext32s_i64(ret, ret);
2876    }
2877#endif
2878}
2879
2880/* Addresses computation (translation time) */
2881static target_long addr_add(DisasContext *ctx, target_long base,
2882                            target_long offset)
2883{
2884    target_long sum = base + offset;
2885
2886#if defined(TARGET_MIPS64)
2887    if (ctx->hflags & MIPS_HFLAG_AWRAP) {
2888        sum = (int32_t)sum;
2889    }
2890#endif
2891    return sum;
2892}
2893
2894/* Sign-extract the low 32-bits to a target_long.  */
2895static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
2896{
2897#if defined(TARGET_MIPS64)
2898    tcg_gen_ext32s_i64(ret, arg);
2899#else
2900    tcg_gen_extrl_i64_i32(ret, arg);
2901#endif
2902}
2903
2904/* Sign-extract the high 32-bits to a target_long.  */
2905static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
2906{
2907#if defined(TARGET_MIPS64)
2908    tcg_gen_sari_i64(ret, arg, 32);
2909#else
2910    tcg_gen_extrh_i64_i32(ret, arg);
2911#endif
2912}
2913
2914static inline void check_cp0_enabled(DisasContext *ctx)
2915{
2916    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
2917        generate_exception_err(ctx, EXCP_CpU, 0);
2918    }
2919}
2920
2921static inline void check_cp1_enabled(DisasContext *ctx)
2922{
2923    if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
2924        generate_exception_err(ctx, EXCP_CpU, 1);
2925    }
2926}
2927
2928/*
2929 * Verify that the processor is running with COP1X instructions enabled.
2930 * This is associated with the nabla symbol in the MIPS32 and MIPS64
2931 * opcode tables.
2932 */
2933static inline void check_cop1x(DisasContext *ctx)
2934{
2935    if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
2936        generate_exception_end(ctx, EXCP_RI);
2937    }
2938}
2939
2940/*
2941 * Verify that the processor is running with 64-bit floating-point
2942 * operations enabled.
2943 */
2944static inline void check_cp1_64bitmode(DisasContext *ctx)
2945{
2946    if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
2947        generate_exception_end(ctx, EXCP_RI);
2948    }
2949}
2950
2951/*
2952 * Verify if floating point register is valid; an operation is not defined
2953 * if bit 0 of any register specification is set and the FR bit in the
2954 * Status register equals zero, since the register numbers specify an
2955 * even-odd pair of adjacent coprocessor general registers. When the FR bit
2956 * in the Status register equals one, both even and odd register numbers
2957 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
2958 *
2959 * Multiple 64 bit wide registers can be checked by calling
2960 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
2961 */
2962static inline void check_cp1_registers(DisasContext *ctx, int regs)
2963{
2964    if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
2965        generate_exception_end(ctx, EXCP_RI);
2966    }
2967}
2968
2969/*
2970 * Verify that the processor is running with DSP instructions enabled.
2971 * This is enabled by CP0 Status register MX(24) bit.
2972 */
2973static inline void check_dsp(DisasContext *ctx)
2974{
2975    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
2976        if (ctx->insn_flags & ASE_DSP) {
2977            generate_exception_end(ctx, EXCP_DSPDIS);
2978        } else {
2979            generate_exception_end(ctx, EXCP_RI);
2980        }
2981    }
2982}
2983
2984static inline void check_dsp_r2(DisasContext *ctx)
2985{
2986    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
2987        if (ctx->insn_flags & ASE_DSP) {
2988            generate_exception_end(ctx, EXCP_DSPDIS);
2989        } else {
2990            generate_exception_end(ctx, EXCP_RI);
2991        }
2992    }
2993}
2994
2995static inline void check_dsp_r3(DisasContext *ctx)
2996{
2997    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
2998        if (ctx->insn_flags & ASE_DSP) {
2999            generate_exception_end(ctx, EXCP_DSPDIS);
3000        } else {
3001            generate_exception_end(ctx, EXCP_RI);
3002        }
3003    }
3004}
3005
3006/*
3007 * This code generates a "reserved instruction" exception if the
3008 * CPU does not support the instruction set corresponding to flags.
3009 */
3010static inline void check_insn(DisasContext *ctx, uint64_t flags)
3011{
3012    if (unlikely(!(ctx->insn_flags & flags))) {
3013        generate_exception_end(ctx, EXCP_RI);
3014    }
3015}
3016
3017/*
3018 * This code generates a "reserved instruction" exception if the
3019 * CPU has corresponding flag set which indicates that the instruction
3020 * has been removed.
3021 */
3022static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
3023{
3024    if (unlikely(ctx->insn_flags & flags)) {
3025        generate_exception_end(ctx, EXCP_RI);
3026    }
3027}
3028
3029/*
3030 * The Linux kernel traps certain reserved instruction exceptions to
3031 * emulate the corresponding instructions. QEMU is the kernel in user
3032 * mode, so those traps are emulated by accepting the instructions.
3033 *
3034 * A reserved instruction exception is generated for flagged CPUs if
3035 * QEMU runs in system mode.
3036 */
3037static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
3038{
3039#ifndef CONFIG_USER_ONLY
3040    check_insn_opc_removed(ctx, flags);
3041#endif
3042}
3043
3044/*
3045 * This code generates a "reserved instruction" exception if the
3046 * CPU does not support 64-bit paired-single (PS) floating point data type.
3047 */
3048static inline void check_ps(DisasContext *ctx)
3049{
3050    if (unlikely(!ctx->ps)) {
3051        generate_exception(ctx, EXCP_RI);
3052    }
3053    check_cp1_64bitmode(ctx);
3054}
3055
3056#ifdef TARGET_MIPS64
3057/*
3058 * This code generates a "reserved instruction" exception if 64-bit
3059 * instructions are not enabled.
3060 */
3061static inline void check_mips_64(DisasContext *ctx)
3062{
3063    if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
3064        generate_exception_end(ctx, EXCP_RI);
3065    }
3066}
3067#endif
3068
3069#ifndef CONFIG_USER_ONLY
3070static inline void check_mvh(DisasContext *ctx)
3071{
3072    if (unlikely(!ctx->mvh)) {
3073        generate_exception(ctx, EXCP_RI);
3074    }
3075}
3076#endif
3077
3078/*
3079 * This code generates a "reserved instruction" exception if the
3080 * Config5 XNP bit is set.
3081 */
3082static inline void check_xnp(DisasContext *ctx)
3083{
3084    if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
3085        generate_exception_end(ctx, EXCP_RI);
3086    }
3087}
3088
3089#ifndef CONFIG_USER_ONLY
3090/*
3091 * This code generates a "reserved instruction" exception if the
3092 * Config3 PW bit is NOT set.
3093 */
3094static inline void check_pw(DisasContext *ctx)
3095{
3096    if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
3097        generate_exception_end(ctx, EXCP_RI);
3098    }
3099}
3100#endif
3101
3102/*
3103 * This code generates a "reserved instruction" exception if the
3104 * Config3 MT bit is NOT set.
3105 */
3106static inline void check_mt(DisasContext *ctx)
3107{
3108    if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
3109        generate_exception_end(ctx, EXCP_RI);
3110    }
3111}
3112
3113#ifndef CONFIG_USER_ONLY
3114/*
3115 * This code generates a "coprocessor unusable" exception if CP0 is not
3116 * available, and, if that is not the case, generates a "reserved instruction"
3117 * exception if the Config5 MT bit is NOT set. This is needed for availability
3118 * control of some of MT ASE instructions.
3119 */
3120static inline void check_cp0_mt(DisasContext *ctx)
3121{
3122    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
3123        generate_exception_err(ctx, EXCP_CpU, 0);
3124    } else {
3125        if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
3126            generate_exception_err(ctx, EXCP_RI, 0);
3127        }
3128    }
3129}
3130#endif
3131
3132/*
3133 * This code generates a "reserved instruction" exception if the
3134 * Config5 NMS bit is set.
3135 */
3136static inline void check_nms(DisasContext *ctx)
3137{
3138    if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
3139        generate_exception_end(ctx, EXCP_RI);
3140    }
3141}
3142
3143/*
3144 * This code generates a "reserved instruction" exception if the
3145 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
3146 * Config2 TL, and Config5 L2C are unset.
3147 */
3148static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
3149{
3150    if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
3151                 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
3152                 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
3153                 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
3154                 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
3155                 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
3156        generate_exception_end(ctx, EXCP_RI);
3157    }
3158}
3159
3160/*
3161 * This code generates a "reserved instruction" exception if the
3162 * Config5 EVA bit is NOT set.
3163 */
3164static inline void check_eva(DisasContext *ctx)
3165{
3166    if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
3167        generate_exception_end(ctx, EXCP_RI);
3168    }
3169}
3170
3171
3172/*
3173 * Define small wrappers for gen_load_fpr* so that we have a uniform
3174 * calling interface for 32 and 64-bit FPRs.  No sense in changing
3175 * all callers for gen_load_fpr32 when we need the CTX parameter for
3176 * this one use.
3177 */
3178#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
3179#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
3180#define FOP_CONDS(type, abs, fmt, ifmt, bits)                                 \
3181static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n,      \
3182                                               int ft, int fs, int cc)        \
3183{                                                                             \
3184    TCGv_i##bits fp0 = tcg_temp_new_i##bits();                                \
3185    TCGv_i##bits fp1 = tcg_temp_new_i##bits();                                \
3186    switch (ifmt) {                                                           \
3187    case FMT_PS:                                                              \
3188        check_ps(ctx);                                                        \
3189        break;                                                                \
3190    case FMT_D:                                                               \
3191        if (abs) {                                                            \
3192            check_cop1x(ctx);                                                 \
3193        }                                                                     \
3194        check_cp1_registers(ctx, fs | ft);                                    \
3195        break;                                                                \
3196    case FMT_S:                                                               \
3197        if (abs) {                                                            \
3198            check_cop1x(ctx);                                                 \
3199        }                                                                     \
3200        break;                                                                \
3201    }                                                                         \
3202    gen_ldcmp_fpr##bits(ctx, fp0, fs);                                        \
3203    gen_ldcmp_fpr##bits(ctx, fp1, ft);                                        \
3204    switch (n) {                                                              \
3205    case  0:                                                                  \
3206        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc);         \
3207    break;                                                                    \
3208    case  1:                                                                  \
3209        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc);        \
3210    break;                                                                    \
3211    case  2:                                                                  \
3212        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc);        \
3213    break;                                                                    \
3214    case  3:                                                                  \
3215        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc);       \
3216    break;                                                                    \
3217    case  4:                                                                  \
3218        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc);       \
3219    break;                                                                    \
3220    case  5:                                                                  \
3221        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc);       \
3222    break;                                                                    \
3223    case  6:                                                                  \
3224        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc);       \
3225    break;                                                                    \
3226    case  7:                                                                  \
3227        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc);       \
3228    break;                                                                    \
3229    case  8:                                                                  \
3230        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc);        \
3231    break;                                                                    \
3232    case  9:                                                                  \
3233        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc);      \
3234    break;                                                                    \
3235    case 10:                                                                  \
3236        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc);       \
3237    break;                                                                    \
3238    case 11:                                                                  \
3239        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc);       \
3240    break;                                                                    \
3241    case 12:                                                                  \
3242        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc);        \
3243    break;                                                                    \
3244    case 13:                                                                  \
3245        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc);       \
3246    break;                                                                    \
3247    case 14:                                                                  \
3248        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc);        \
3249    break;                                                                    \
3250    case 15:                                                                  \
3251        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc);       \
3252    break;                                                                    \
3253    default:                                                                  \
3254        abort();                                                              \
3255    }                                                                         \
3256    tcg_temp_free_i##bits(fp0);                                               \
3257    tcg_temp_free_i##bits(fp1);                                               \
3258}
3259
3260FOP_CONDS(, 0, d, FMT_D, 64)
3261FOP_CONDS(abs, 1, d, FMT_D, 64)
3262FOP_CONDS(, 0, s, FMT_S, 32)
3263FOP_CONDS(abs, 1, s, FMT_S, 32)
3264FOP_CONDS(, 0, ps, FMT_PS, 64)
3265FOP_CONDS(abs, 1, ps, FMT_PS, 64)
3266#undef FOP_CONDS
3267
3268#define FOP_CONDNS(fmt, ifmt, bits, STORE)                              \
3269static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n,         \
3270                                      int ft, int fs, int fd)           \
3271{                                                                       \
3272    TCGv_i ## bits fp0 = tcg_temp_new_i ## bits();                      \
3273    TCGv_i ## bits fp1 = tcg_temp_new_i ## bits();                      \
3274    if (ifmt == FMT_D) {                                                \
3275        check_cp1_registers(ctx, fs | ft | fd);                         \
3276    }                                                                   \
3277    gen_ldcmp_fpr ## bits(ctx, fp0, fs);                                \
3278    gen_ldcmp_fpr ## bits(ctx, fp1, ft);                                \
3279    switch (n) {                                                        \
3280    case  0:                                                            \
3281        gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1);       \
3282        break;                                                          \
3283    case  1:                                                            \
3284        gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1);       \
3285        break;                                                          \
3286    case  2:                                                            \
3287        gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1);       \
3288        break;                                                          \
3289    case  3:                                                            \
3290        gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1);      \
3291        break;                                                          \
3292    case  4:                                                            \
3293        gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1);       \
3294        break;                                                          \
3295    case  5:                                                            \
3296        gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1);      \
3297        break;                                                          \
3298    case  6:                                                            \
3299        gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1);       \
3300        break;                                                          \
3301    case  7:                                                            \
3302        gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1);      \
3303        break;                                                          \
3304    case  8:                                                            \
3305        gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1);      \
3306        break;                                                          \
3307    case  9:                                                            \
3308        gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1);      \
3309        break;                                                          \
3310    case 10:                                                            \
3311        gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1);      \
3312        break;                                                          \
3313    case 11:                                                            \
3314        gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1);     \
3315        break;                                                          \
3316    case 12:                                                            \
3317        gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1);      \
3318        break;                                                          \
3319    case 13:                                                            \
3320        gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1);     \
3321        break;                                                          \
3322    case 14:                                                            \
3323        gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1);      \
3324        break;                                                          \
3325    case 15:                                                            \
3326        gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1);     \
3327        break;                                                          \
3328    case 17:                                                            \
3329        gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1);       \
3330        break;                                                          \
3331    case 18:                                                            \
3332        gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1);      \
3333        break;                                                          \
3334    case 19:                                                            \
3335        gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1);       \
3336        break;                                                          \
3337    case 25:                                                            \
3338        gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1);      \
3339        break;                                                          \
3340    case 26:                                                            \
3341        gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1);     \
3342        break;                                                          \
3343    case 27:                                                            \
3344        gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1);      \
3345        break;                                                          \
3346    default:                                                            \
3347        abort();                                                        \
3348    }                                                                   \
3349    STORE;                                                              \
3350    tcg_temp_free_i ## bits(fp0);                                       \
3351    tcg_temp_free_i ## bits(fp1);                                       \
3352}
3353
3354FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
3355FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
3356#undef FOP_CONDNS
3357#undef gen_ldcmp_fpr32
3358#undef gen_ldcmp_fpr64
3359
3360/* load/store instructions. */
3361#ifdef CONFIG_USER_ONLY
3362#define OP_LD_ATOMIC(insn, fname)                                          \
3363static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx,          \
3364                                DisasContext *ctx)                         \
3365{                                                                          \
3366    TCGv t0 = tcg_temp_new();                                              \
3367    tcg_gen_mov_tl(t0, arg1);                                              \
3368    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                         \
3369    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr));            \
3370    tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval));            \
3371    tcg_temp_free(t0);                                                     \
3372}
3373#else
3374#define OP_LD_ATOMIC(insn, fname)                                          \
3375static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx,          \
3376                                DisasContext *ctx)                         \
3377{                                                                          \
3378    gen_helper_1e1i(insn, ret, arg1, mem_idx);                             \
3379}
3380#endif
3381OP_LD_ATOMIC(ll, ld32s);
3382#if defined(TARGET_MIPS64)
3383OP_LD_ATOMIC(lld, ld64);
3384#endif
3385#undef OP_LD_ATOMIC
3386
3387static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
3388                                 int base, int offset)
3389{
3390    if (base == 0) {
3391        tcg_gen_movi_tl(addr, offset);
3392    } else if (offset == 0) {
3393        gen_load_gpr(addr, base);
3394    } else {
3395        tcg_gen_movi_tl(addr, offset);
3396        gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
3397    }
3398}
3399
3400static target_ulong pc_relative_pc(DisasContext *ctx)
3401{
3402    target_ulong pc = ctx->base.pc_next;
3403
3404    if (ctx->hflags & MIPS_HFLAG_BMASK) {
3405        int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
3406
3407        pc -= branch_bytes;
3408    }
3409
3410    pc &= ~(target_ulong)3;
3411    return pc;
3412}
3413
3414/* Load */
3415static void gen_ld(DisasContext *ctx, uint32_t opc,
3416                   int rt, int base, int offset)
3417{
3418    TCGv t0, t1, t2;
3419    int mem_idx = ctx->mem_idx;
3420
3421    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
3422        /*
3423         * Loongson CPU uses a load to zero register for prefetch.
3424         * We emulate it as a NOP. On other CPU we must perform the
3425         * actual memory access.
3426         */
3427        return;
3428    }
3429
3430    t0 = tcg_temp_new();
3431    gen_base_offset_addr(ctx, t0, base, offset);
3432
3433    switch (opc) {
3434#if defined(TARGET_MIPS64)
3435    case OPC_LWU:
3436        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
3437                           ctx->default_tcg_memop_mask);
3438        gen_store_gpr(t0, rt);
3439        break;
3440    case OPC_LD:
3441        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ |
3442                           ctx->default_tcg_memop_mask);
3443        gen_store_gpr(t0, rt);
3444        break;
3445    case OPC_LLD:
3446    case R6_OPC_LLD:
3447        op_ld_lld(t0, t0, mem_idx, ctx);
3448        gen_store_gpr(t0, rt);
3449        break;
3450    case OPC_LDL:
3451        t1 = tcg_temp_new();
3452        /*
3453         * Do a byte access to possibly trigger a page
3454         * fault with the unaligned address.
3455         */
3456        tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
3457        tcg_gen_andi_tl(t1, t0, 7);
3458#ifndef TARGET_WORDS_BIGENDIAN
3459        tcg_gen_xori_tl(t1, t1, 7);
3460#endif
3461        tcg_gen_shli_tl(t1, t1, 3);
3462        tcg_gen_andi_tl(t0, t0, ~7);
3463        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
3464        tcg_gen_shl_tl(t0, t0, t1);
3465        t2 = tcg_const_tl(-1);
3466        tcg_gen_shl_tl(t2, t2, t1);
3467        gen_load_gpr(t1, rt);
3468        tcg_gen_andc_tl(t1, t1, t2);
3469        tcg_temp_free(t2);
3470        tcg_gen_or_tl(t0, t0, t1);
3471        tcg_temp_free(t1);
3472        gen_store_gpr(t0, rt);
3473        break;
3474    case OPC_LDR:
3475        t1 = tcg_temp_new();
3476        /*
3477         * Do a byte access to possibly trigger a page
3478         * fault with the unaligned address.
3479         */
3480        tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
3481        tcg_gen_andi_tl(t1, t0, 7);
3482#ifdef TARGET_WORDS_BIGENDIAN
3483        tcg_gen_xori_tl(t1, t1, 7);
3484#endif
3485        tcg_gen_shli_tl(t1, t1, 3);
3486        tcg_gen_andi_tl(t0, t0, ~7);
3487        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
3488        tcg_gen_shr_tl(t0, t0, t1);
3489        tcg_gen_xori_tl(t1, t1, 63);
3490        t2 = tcg_const_tl(0xfffffffffffffffeull);
3491        tcg_gen_shl_tl(t2, t2, t1);
3492        gen_load_gpr(t1, rt);
3493        tcg_gen_and_tl(t1, t1, t2);
3494        tcg_temp_free(t2);
3495        tcg_gen_or_tl(t0, t0, t1);
3496        tcg_temp_free(t1);
3497        gen_store_gpr(t0, rt);
3498        break;
3499    case OPC_LDPC:
3500        t1 = tcg_const_tl(pc_relative_pc(ctx));
3501        gen_op_addr_add(ctx, t0, t0, t1);
3502        tcg_temp_free(t1);
3503        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
3504        gen_store_gpr(t0, rt);
3505        break;
3506#endif
3507    case OPC_LWPC:
3508        t1 = tcg_const_tl(pc_relative_pc(ctx));
3509        gen_op_addr_add(ctx, t0, t0, t1);
3510        tcg_temp_free(t1);
3511        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
3512        gen_store_gpr(t0, rt);
3513        break;
3514    case OPC_LWE:
3515        mem_idx = MIPS_HFLAG_UM;
3516        /* fall through */
3517    case OPC_LW:
3518        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
3519                           ctx->default_tcg_memop_mask);
3520        gen_store_gpr(t0, rt);
3521        break;
3522    case OPC_LHE:
3523        mem_idx = MIPS_HFLAG_UM;
3524        /* fall through */
3525    case OPC_LH:
3526        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
3527                           ctx->default_tcg_memop_mask);
3528        gen_store_gpr(t0, rt);
3529        break;
3530    case OPC_LHUE:
3531        mem_idx = MIPS_HFLAG_UM;
3532        /* fall through */
3533    case OPC_LHU:
3534        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
3535                           ctx->default_tcg_memop_mask);
3536        gen_store_gpr(t0, rt);
3537        break;
3538    case OPC_LBE:
3539        mem_idx = MIPS_HFLAG_UM;
3540        /* fall through */
3541    case OPC_LB:
3542        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB);
3543        gen_store_gpr(t0, rt);
3544        break;
3545    case OPC_LBUE:
3546        mem_idx = MIPS_HFLAG_UM;
3547        /* fall through */
3548    case OPC_LBU:
3549        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB);
3550        gen_store_gpr(t0, rt);
3551        break;
3552    case OPC_LWLE:
3553        mem_idx = MIPS_HFLAG_UM;
3554        /* fall through */
3555    case OPC_LWL:
3556        t1 = tcg_temp_new();
3557        /*
3558         * Do a byte access to possibly trigger a page
3559         * fault with the unaligned address.
3560         */
3561        tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
3562        tcg_gen_andi_tl(t1, t0, 3);
3563#ifndef TARGET_WORDS_BIGENDIAN
3564        tcg_gen_xori_tl(t1, t1, 3);
3565#endif
3566        tcg_gen_shli_tl(t1, t1, 3);
3567        tcg_gen_andi_tl(t0, t0, ~3);
3568        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
3569        tcg_gen_shl_tl(t0, t0, t1);
3570        t2 = tcg_const_tl(-1);
3571        tcg_gen_shl_tl(t2, t2, t1);
3572        gen_load_gpr(t1, rt);
3573        tcg_gen_andc_tl(t1, t1, t2);
3574        tcg_temp_free(t2);
3575        tcg_gen_or_tl(t0, t0, t1);
3576        tcg_temp_free(t1);
3577        tcg_gen_ext32s_tl(t0, t0);
3578        gen_store_gpr(t0, rt);
3579        break;
3580    case OPC_LWRE:
3581        mem_idx = MIPS_HFLAG_UM;
3582        /* fall through */
3583    case OPC_LWR:
3584        t1 = tcg_temp_new();
3585        /*
3586         * Do a byte access to possibly trigger a page
3587         * fault with the unaligned address.
3588         */
3589        tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
3590        tcg_gen_andi_tl(t1, t0, 3);
3591#ifdef TARGET_WORDS_BIGENDIAN
3592        tcg_gen_xori_tl(t1, t1, 3);
3593#endif
3594        tcg_gen_shli_tl(t1, t1, 3);
3595        tcg_gen_andi_tl(t0, t0, ~3);
3596        tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
3597        tcg_gen_shr_tl(t0, t0, t1);
3598        tcg_gen_xori_tl(t1, t1, 31);
3599        t2 = tcg_const_tl(0xfffffffeull);
3600        tcg_gen_shl_tl(t2, t2, t1);
3601        gen_load_gpr(t1, rt);
3602        tcg_gen_and_tl(t1, t1, t2);
3603        tcg_temp_free(t2);
3604        tcg_gen_or_tl(t0, t0, t1);
3605        tcg_temp_free(t1);
3606        tcg_gen_ext32s_tl(t0, t0);
3607        gen_store_gpr(t0, rt);
3608        break;
3609    case OPC_LLE:
3610        mem_idx = MIPS_HFLAG_UM;
3611        /* fall through */
3612    case OPC_LL:
3613    case R6_OPC_LL:
3614        op_ld_ll(t0, t0, mem_idx, ctx);
3615        gen_store_gpr(t0, rt);
3616        break;
3617    }
3618    tcg_temp_free(t0);
3619}
3620
3621static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
3622                    uint32_t reg1, uint32_t reg2)
3623{
3624    TCGv taddr = tcg_temp_new();
3625    TCGv_i64 tval = tcg_temp_new_i64();
3626    TCGv tmp1 = tcg_temp_new();
3627    TCGv tmp2 = tcg_temp_new();
3628
3629    gen_base_offset_addr(ctx, taddr, base, offset);
3630    tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
3631#ifdef TARGET_WORDS_BIGENDIAN
3632    tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
3633#else
3634    tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
3635#endif
3636    gen_store_gpr(tmp1, reg1);
3637    tcg_temp_free(tmp1);
3638    gen_store_gpr(tmp2, reg2);
3639    tcg_temp_free(tmp2);
3640    tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
3641    tcg_temp_free_i64(tval);
3642    tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
3643    tcg_temp_free(taddr);
3644}
3645
3646/* Store */
3647static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
3648                   int base, int offset)
3649{
3650    TCGv t0 = tcg_temp_new();
3651    TCGv t1 = tcg_temp_new();
3652    int mem_idx = ctx->mem_idx;
3653
3654    gen_base_offset_addr(ctx, t0, base, offset);
3655    gen_load_gpr(t1, rt);
3656    switch (opc) {
3657#if defined(TARGET_MIPS64)
3658    case OPC_SD:
3659        tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEQ |
3660                           ctx->default_tcg_memop_mask);
3661        break;
3662    case OPC_SDL:
3663        gen_helper_0e2i(sdl, t1, t0, mem_idx);
3664        break;
3665    case OPC_SDR:
3666        gen_helper_0e2i(sdr, t1, t0, mem_idx);
3667        break;
3668#endif
3669    case OPC_SWE:
3670        mem_idx = MIPS_HFLAG_UM;
3671        /* fall through */
3672    case OPC_SW:
3673        tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
3674                           ctx->default_tcg_memop_mask);
3675        break;
3676    case OPC_SHE:
3677        mem_idx = MIPS_HFLAG_UM;
3678        /* fall through */
3679    case OPC_SH:
3680        tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
3681                           ctx->default_tcg_memop_mask);
3682        break;
3683    case OPC_SBE:
3684        mem_idx = MIPS_HFLAG_UM;
3685        /* fall through */
3686    case OPC_SB:
3687        tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);
3688        break;
3689    case OPC_SWLE:
3690        mem_idx = MIPS_HFLAG_UM;
3691        /* fall through */
3692    case OPC_SWL:
3693        gen_helper_0e2i(swl, t1, t0, mem_idx);
3694        break;
3695    case OPC_SWRE:
3696        mem_idx = MIPS_HFLAG_UM;
3697        /* fall through */
3698    case OPC_SWR:
3699        gen_helper_0e2i(swr, t1, t0, mem_idx);
3700        break;
3701    }
3702    tcg_temp_free(t0);
3703    tcg_temp_free(t1);
3704}
3705
3706
3707/* Store conditional */
3708static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
3709                        MemOp tcg_mo, bool eva)
3710{
3711    TCGv addr, t0, val;
3712    TCGLabel *l1 = gen_new_label();
3713    TCGLabel *done = gen_new_label();
3714
3715    t0 = tcg_temp_new();
3716    addr = tcg_temp_new();
3717    /* compare the address against that of the preceeding LL */
3718    gen_base_offset_addr(ctx, addr, base, offset);
3719    tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
3720    tcg_temp_free(addr);
3721    tcg_gen_movi_tl(t0, 0);
3722    gen_store_gpr(t0, rt);
3723    tcg_gen_br(done);
3724
3725    gen_set_label(l1);
3726    /* generate cmpxchg */
3727    val = tcg_temp_new();
3728    gen_load_gpr(val, rt);
3729    tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val,
3730                              eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
3731    tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
3732    gen_store_gpr(t0, rt);
3733    tcg_temp_free(val);
3734
3735    gen_set_label(done);
3736    tcg_temp_free(t0);
3737}
3738
3739
3740static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
3741                    uint32_t reg1, uint32_t reg2, bool eva)
3742{
3743    TCGv taddr = tcg_temp_local_new();
3744    TCGv lladdr = tcg_temp_local_new();
3745    TCGv_i64 tval = tcg_temp_new_i64();
3746    TCGv_i64 llval = tcg_temp_new_i64();
3747    TCGv_i64 val = tcg_temp_new_i64();
3748    TCGv tmp1 = tcg_temp_new();
3749    TCGv tmp2 = tcg_temp_new();
3750    TCGLabel *lab_fail = gen_new_label();
3751    TCGLabel *lab_done = gen_new_label();
3752
3753    gen_base_offset_addr(ctx, taddr, base, offset);
3754
3755    tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
3756    tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
3757
3758    gen_load_gpr(tmp1, reg1);
3759    gen_load_gpr(tmp2, reg2);
3760
3761#ifdef TARGET_WORDS_BIGENDIAN
3762    tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
3763#else
3764    tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
3765#endif
3766
3767    tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
3768    tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
3769                               eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
3770    if (reg1 != 0) {
3771        tcg_gen_movi_tl(cpu_gpr[reg1], 1);
3772    }
3773    tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done);
3774
3775    gen_set_label(lab_fail);
3776
3777    if (reg1 != 0) {
3778        tcg_gen_movi_tl(cpu_gpr[reg1], 0);
3779    }
3780    gen_set_label(lab_done);
3781    tcg_gen_movi_tl(lladdr, -1);
3782    tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
3783}
3784
3785/* Load and store */
3786static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
3787                         TCGv t0)
3788{
3789    /*
3790     * Don't do NOP if destination is zero: we must perform the actual
3791     * memory access.
3792     */
3793    switch (opc) {
3794    case OPC_LWC1:
3795        {
3796            TCGv_i32 fp0 = tcg_temp_new_i32();
3797            tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
3798                                ctx->default_tcg_memop_mask);
3799            gen_store_fpr32(ctx, fp0, ft);
3800            tcg_temp_free_i32(fp0);
3801        }
3802        break;
3803    case OPC_SWC1:
3804        {
3805            TCGv_i32 fp0 = tcg_temp_new_i32();
3806            gen_load_fpr32(ctx, fp0, ft);
3807            tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
3808                                ctx->default_tcg_memop_mask);
3809            tcg_temp_free_i32(fp0);
3810        }
3811        break;
3812    case OPC_LDC1:
3813        {
3814            TCGv_i64 fp0 = tcg_temp_new_i64();
3815            tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
3816                                ctx->default_tcg_memop_mask);
3817            gen_store_fpr64(ctx, fp0, ft);
3818            tcg_temp_free_i64(fp0);
3819        }
3820        break;
3821    case OPC_SDC1:
3822        {
3823            TCGv_i64 fp0 = tcg_temp_new_i64();
3824            gen_load_fpr64(ctx, fp0, ft);
3825            tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
3826                                ctx->default_tcg_memop_mask);
3827            tcg_temp_free_i64(fp0);
3828        }
3829        break;
3830    default:
3831        MIPS_INVAL("flt_ldst");
3832        generate_exception_end(ctx, EXCP_RI);
3833        break;
3834    }
3835}
3836
3837static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
3838                          int rs, int16_t imm)
3839{
3840    TCGv t0 = tcg_temp_new();
3841
3842    if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
3843        check_cp1_enabled(ctx);
3844        switch (op) {
3845        case OPC_LDC1:
3846        case OPC_SDC1:
3847            check_insn(ctx, ISA_MIPS2);
3848            /* Fallthrough */
3849        default:
3850            gen_base_offset_addr(ctx, t0, rs, imm);
3851            gen_flt_ldst(ctx, op, rt, t0);
3852        }
3853    } else {
3854        generate_exception_err(ctx, EXCP_CpU, 1);
3855    }
3856    tcg_temp_free(t0);
3857}
3858
3859/* Arithmetic with immediate operand */
3860static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
3861                          int rt, int rs, int imm)
3862{
3863    target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
3864
3865    if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
3866        /*
3867         * If no destination, treat it as a NOP.
3868         * For addi, we must generate the overflow exception when needed.
3869         */
3870        return;
3871    }
3872    switch (opc) {
3873    case OPC_ADDI:
3874        {
3875            TCGv t0 = tcg_temp_local_new();
3876            TCGv t1 = tcg_temp_new();
3877            TCGv t2 = tcg_temp_new();
3878            TCGLabel *l1 = gen_new_label();
3879
3880            gen_load_gpr(t1, rs);
3881            tcg_gen_addi_tl(t0, t1, uimm);
3882            tcg_gen_ext32s_tl(t0, t0);
3883
3884            tcg_gen_xori_tl(t1, t1, ~uimm);
3885            tcg_gen_xori_tl(t2, t0, uimm);
3886            tcg_gen_and_tl(t1, t1, t2);
3887            tcg_temp_free(t2);
3888            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
3889            tcg_temp_free(t1);
3890            /* operands of same sign, result different sign */
3891            generate_exception(ctx, EXCP_OVERFLOW);
3892            gen_set_label(l1);
3893            tcg_gen_ext32s_tl(t0, t0);
3894            gen_store_gpr(t0, rt);
3895            tcg_temp_free(t0);
3896        }
3897        break;
3898    case OPC_ADDIU:
3899        if (rs != 0) {
3900            tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
3901            tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
3902        } else {
3903            tcg_gen_movi_tl(cpu_gpr[rt], uimm);
3904        }
3905        break;
3906#if defined(TARGET_MIPS64)
3907    case OPC_DADDI:
3908        {
3909            TCGv t0 = tcg_temp_local_new();
3910            TCGv t1 = tcg_temp_new();
3911            TCGv t2 = tcg_temp_new();
3912            TCGLabel *l1 = gen_new_label();
3913
3914            gen_load_gpr(t1, rs);
3915            tcg_gen_addi_tl(t0, t1, uimm);
3916
3917            tcg_gen_xori_tl(t1, t1, ~uimm);
3918            tcg_gen_xori_tl(t2, t0, uimm);
3919            tcg_gen_and_tl(t1, t1, t2);
3920            tcg_temp_free(t2);
3921            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
3922            tcg_temp_free(t1);
3923            /* operands of same sign, result different sign */
3924            generate_exception(ctx, EXCP_OVERFLOW);
3925            gen_set_label(l1);
3926            gen_store_gpr(t0, rt);
3927            tcg_temp_free(t0);
3928        }
3929        break;
3930    case OPC_DADDIU:
3931        if (rs != 0) {
3932            tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
3933        } else {
3934            tcg_gen_movi_tl(cpu_gpr[rt], uimm);
3935        }
3936        break;
3937#endif
3938    }
3939}
3940
3941/* Logic with immediate operand */
3942static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
3943                          int rt, int rs, int16_t imm)
3944{
3945    target_ulong uimm;
3946
3947    if (rt == 0) {
3948        /* If no destination, treat it as a NOP. */
3949        return;
3950    }
3951    uimm = (uint16_t)imm;
3952    switch (opc) {
3953    case OPC_ANDI:
3954        if (likely(rs != 0)) {
3955            tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
3956        } else {
3957            tcg_gen_movi_tl(cpu_gpr[rt], 0);
3958        }
3959        break;
3960    case OPC_ORI:
3961        if (rs != 0) {
3962            tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
3963        } else {
3964            tcg_gen_movi_tl(cpu_gpr[rt], uimm);
3965        }
3966        break;
3967    case OPC_XORI:
3968        if (likely(rs != 0)) {
3969            tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
3970        } else {
3971            tcg_gen_movi_tl(cpu_gpr[rt], uimm);
3972        }
3973        break;
3974    case OPC_LUI:
3975        if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
3976            /* OPC_AUI */
3977            tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
3978            tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
3979        } else {
3980            tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
3981        }
3982        break;
3983
3984    default:
3985        break;
3986    }
3987}
3988
3989/* Set on less than with immediate operand */
3990static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
3991                        int rt, int rs, int16_t imm)
3992{
3993    target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
3994    TCGv t0;
3995
3996    if (rt == 0) {
3997        /* If no destination, treat it as a NOP. */
3998        return;
3999    }
4000    t0 = tcg_temp_new();
4001    gen_load_gpr(t0, rs);
4002    switch (opc) {
4003    case OPC_SLTI:
4004        tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
4005        break;
4006    case OPC_SLTIU:
4007        tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
4008        break;
4009    }
4010    tcg_temp_free(t0);
4011}
4012
4013/* Shifts with immediate operand */
4014static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
4015                          int rt, int rs, int16_t imm)
4016{
4017    target_ulong uimm = ((uint16_t)imm) & 0x1f;
4018    TCGv t0;
4019
4020    if (rt == 0) {
4021        /* If no destination, treat it as a NOP. */
4022        return;
4023    }
4024
4025    t0 = tcg_temp_new();
4026    gen_load_gpr(t0, rs);
4027    switch (opc) {
4028    case OPC_SLL:
4029        tcg_gen_shli_tl(t0, t0, uimm);
4030        tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
4031        break;
4032    case OPC_SRA:
4033        tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
4034        break;
4035    case OPC_SRL:
4036        if (uimm != 0) {
4037            tcg_gen_ext32u_tl(t0, t0);
4038            tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
4039        } else {
4040            tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
4041        }
4042        break;
4043    case OPC_ROTR:
4044        if (uimm != 0) {
4045            TCGv_i32 t1 = tcg_temp_new_i32();
4046
4047            tcg_gen_trunc_tl_i32(t1, t0);
4048            tcg_gen_rotri_i32(t1, t1, uimm);
4049            tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
4050            tcg_temp_free_i32(t1);
4051        } else {
4052            tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
4053        }
4054        break;
4055#if defined(TARGET_MIPS64)
4056    case OPC_DSLL:
4057        tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
4058        break;
4059    case OPC_DSRA:
4060        tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
4061        break;
4062    case OPC_DSRL:
4063        tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
4064        break;
4065    case OPC_DROTR:
4066        if (uimm != 0) {
4067            tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
4068        } else {
4069            tcg_gen_mov_tl(cpu_gpr[rt], t0);
4070        }
4071        break;
4072    case OPC_DSLL32:
4073        tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
4074        break;
4075    case OPC_DSRA32:
4076        tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
4077        break;
4078    case OPC_DSRL32:
4079        tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
4080        break;
4081    case OPC_DROTR32:
4082        tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
4083        break;
4084#endif
4085    }
4086    tcg_temp_free(t0);
4087}
4088
4089/* Arithmetic */
4090static void gen_arith(DisasContext *ctx, uint32_t opc,
4091                      int rd, int rs, int rt)
4092{
4093    if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
4094       && opc != OPC_DADD && opc != OPC_DSUB) {
4095        /*
4096         * If no destination, treat it as a NOP.
4097         * For add & sub, we must generate the overflow exception when needed.
4098         */
4099        return;
4100    }
4101
4102    switch (opc) {
4103    case OPC_ADD:
4104        {
4105            TCGv t0 = tcg_temp_local_new();
4106            TCGv t1 = tcg_temp_new();
4107            TCGv t2 = tcg_temp_new();
4108            TCGLabel *l1 = gen_new_label();
4109
4110            gen_load_gpr(t1, rs);
4111            gen_load_gpr(t2, rt);
4112            tcg_gen_add_tl(t0, t1, t2);
4113            tcg_gen_ext32s_tl(t0, t0);
4114            tcg_gen_xor_tl(t1, t1, t2);
4115            tcg_gen_xor_tl(t2, t0, t2);
4116            tcg_gen_andc_tl(t1, t2, t1);
4117            tcg_temp_free(t2);
4118            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
4119            tcg_temp_free(t1);
4120            /* operands of same sign, result different sign */
4121            generate_exception(ctx, EXCP_OVERFLOW);
4122            gen_set_label(l1);
4123            gen_store_gpr(t0, rd);
4124            tcg_temp_free(t0);
4125        }
4126        break;
4127    case OPC_ADDU:
4128        if (rs != 0 && rt != 0) {
4129            tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4130            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4131        } else if (rs == 0 && rt != 0) {
4132            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
4133        } else if (rs != 0 && rt == 0) {
4134            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4135        } else {
4136            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4137        }
4138        break;
4139    case OPC_SUB:
4140        {
4141            TCGv t0 = tcg_temp_local_new();
4142            TCGv t1 = tcg_temp_new();
4143            TCGv t2 = tcg_temp_new();
4144            TCGLabel *l1 = gen_new_label();
4145
4146            gen_load_gpr(t1, rs);
4147            gen_load_gpr(t2, rt);
4148            tcg_gen_sub_tl(t0, t1, t2);
4149            tcg_gen_ext32s_tl(t0, t0);
4150            tcg_gen_xor_tl(t2, t1, t2);
4151            tcg_gen_xor_tl(t1, t0, t1);
4152            tcg_gen_and_tl(t1, t1, t2);
4153            tcg_temp_free(t2);
4154            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
4155            tcg_temp_free(t1);
4156            /*
4157             * operands of different sign, first operand and the result
4158             * of different sign
4159             */
4160            generate_exception(ctx, EXCP_OVERFLOW);
4161            gen_set_label(l1);
4162            gen_store_gpr(t0, rd);
4163            tcg_temp_free(t0);
4164        }
4165        break;
4166    case OPC_SUBU:
4167        if (rs != 0 && rt != 0) {
4168            tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4169            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4170        } else if (rs == 0 && rt != 0) {
4171            tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
4172            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4173        } else if (rs != 0 && rt == 0) {
4174            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4175        } else {
4176            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4177        }
4178        break;
4179#if defined(TARGET_MIPS64)
4180    case OPC_DADD:
4181        {
4182            TCGv t0 = tcg_temp_local_new();
4183            TCGv t1 = tcg_temp_new();
4184            TCGv t2 = tcg_temp_new();
4185            TCGLabel *l1 = gen_new_label();
4186
4187            gen_load_gpr(t1, rs);
4188            gen_load_gpr(t2, rt);
4189            tcg_gen_add_tl(t0, t1, t2);
4190            tcg_gen_xor_tl(t1, t1, t2);
4191            tcg_gen_xor_tl(t2, t0, t2);
4192            tcg_gen_andc_tl(t1, t2, t1);
4193            tcg_temp_free(t2);
4194            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
4195            tcg_temp_free(t1);
4196            /* operands of same sign, result different sign */
4197            generate_exception(ctx, EXCP_OVERFLOW);
4198            gen_set_label(l1);
4199            gen_store_gpr(t0, rd);
4200            tcg_temp_free(t0);
4201        }
4202        break;
4203    case OPC_DADDU:
4204        if (rs != 0 && rt != 0) {
4205            tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4206        } else if (rs == 0 && rt != 0) {
4207            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
4208        } else if (rs != 0 && rt == 0) {
4209            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4210        } else {
4211            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4212        }
4213        break;
4214    case OPC_DSUB:
4215        {
4216            TCGv t0 = tcg_temp_local_new();
4217            TCGv t1 = tcg_temp_new();
4218            TCGv t2 = tcg_temp_new();
4219            TCGLabel *l1 = gen_new_label();
4220
4221            gen_load_gpr(t1, rs);
4222            gen_load_gpr(t2, rt);
4223            tcg_gen_sub_tl(t0, t1, t2);
4224            tcg_gen_xor_tl(t2, t1, t2);
4225            tcg_gen_xor_tl(t1, t0, t1);
4226            tcg_gen_and_tl(t1, t1, t2);
4227            tcg_temp_free(t2);
4228            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
4229            tcg_temp_free(t1);
4230            /*
4231             * Operands of different sign, first operand and result different
4232             * sign.
4233             */
4234            generate_exception(ctx, EXCP_OVERFLOW);
4235            gen_set_label(l1);
4236            gen_store_gpr(t0, rd);
4237            tcg_temp_free(t0);
4238        }
4239        break;
4240    case OPC_DSUBU:
4241        if (rs != 0 && rt != 0) {
4242            tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4243        } else if (rs == 0 && rt != 0) {
4244            tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
4245        } else if (rs != 0 && rt == 0) {
4246            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4247        } else {
4248            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4249        }
4250        break;
4251#endif
4252    case OPC_MUL:
4253        if (likely(rs != 0 && rt != 0)) {
4254            tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4255            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4256        } else {
4257            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4258        }
4259        break;
4260    }
4261}
4262
4263/* Conditional move */
4264static void gen_cond_move(DisasContext *ctx, uint32_t opc,
4265                          int rd, int rs, int rt)
4266{
4267    TCGv t0, t1, t2;
4268
4269    if (rd == 0) {
4270        /* If no destination, treat it as a NOP. */
4271        return;
4272    }
4273
4274    t0 = tcg_temp_new();
4275    gen_load_gpr(t0, rt);
4276    t1 = tcg_const_tl(0);
4277    t2 = tcg_temp_new();
4278    gen_load_gpr(t2, rs);
4279    switch (opc) {
4280    case OPC_MOVN:
4281        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
4282        break;
4283    case OPC_MOVZ:
4284        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
4285        break;
4286    case OPC_SELNEZ:
4287        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
4288        break;
4289    case OPC_SELEQZ:
4290        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
4291        break;
4292    }
4293    tcg_temp_free(t2);
4294    tcg_temp_free(t1);
4295    tcg_temp_free(t0);
4296}
4297
4298/* Logic */
4299static void gen_logic(DisasContext *ctx, uint32_t opc,
4300                      int rd, int rs, int rt)
4301{
4302    if (rd == 0) {
4303        /* If no destination, treat it as a NOP. */
4304        return;
4305    }
4306
4307    switch (opc) {
4308    case OPC_AND:
4309        if (likely(rs != 0 && rt != 0)) {
4310            tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4311        } else {
4312            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4313        }
4314        break;
4315    case OPC_NOR:
4316        if (rs != 0 && rt != 0) {
4317            tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4318        } else if (rs == 0 && rt != 0) {
4319            tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
4320        } else if (rs != 0 && rt == 0) {
4321            tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
4322        } else {
4323            tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
4324        }
4325        break;
4326    case OPC_OR:
4327        if (likely(rs != 0 && rt != 0)) {
4328            tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4329        } else if (rs == 0 && rt != 0) {
4330            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
4331        } else if (rs != 0 && rt == 0) {
4332            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4333        } else {
4334            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4335        }
4336        break;
4337    case OPC_XOR:
4338        if (likely(rs != 0 && rt != 0)) {
4339            tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
4340        } else if (rs == 0 && rt != 0) {
4341            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
4342        } else if (rs != 0 && rt == 0) {
4343            tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
4344        } else {
4345            tcg_gen_movi_tl(cpu_gpr[rd], 0);
4346        }
4347        break;
4348    }
4349}
4350
4351/* Set on lower than */
4352static void gen_slt(DisasContext *ctx, uint32_t opc,
4353                    int rd, int rs, int rt)
4354{
4355    TCGv t0, t1;
4356
4357    if (rd == 0) {
4358        /* If no destination, treat it as a NOP. */
4359        return;
4360    }
4361
4362    t0 = tcg_temp_new();
4363    t1 = tcg_temp_new();
4364    gen_load_gpr(t0, rs);
4365    gen_load_gpr(t1, rt);
4366    switch (opc) {
4367    case OPC_SLT:
4368        tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
4369        break;
4370    case OPC_SLTU:
4371        tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
4372        break;
4373    }
4374    tcg_temp_free(t0);
4375    tcg_temp_free(t1);
4376}
4377
4378/* Shifts */
4379static void gen_shift(DisasContext *ctx, uint32_t opc,
4380                      int rd, int rs, int rt)
4381{
4382    TCGv t0, t1;
4383
4384    if (rd == 0) {
4385        /*
4386         * If no destination, treat it as a NOP.
4387         * For add & sub, we must generate the overflow exception when needed.
4388         */
4389        return;
4390    }
4391
4392    t0 = tcg_temp_new();
4393    t1 = tcg_temp_new();
4394    gen_load_gpr(t0, rs);
4395    gen_load_gpr(t1, rt);
4396    switch (opc) {
4397    case OPC_SLLV:
4398        tcg_gen_andi_tl(t0, t0, 0x1f);
4399        tcg_gen_shl_tl(t0, t1, t0);
4400        tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4401        break;
4402    case OPC_SRAV:
4403        tcg_gen_andi_tl(t0, t0, 0x1f);
4404        tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
4405        break;
4406    case OPC_SRLV:
4407        tcg_gen_ext32u_tl(t1, t1);
4408        tcg_gen_andi_tl(t0, t0, 0x1f);
4409        tcg_gen_shr_tl(t0, t1, t0);
4410        tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4411        break;
4412    case OPC_ROTRV:
4413        {
4414            TCGv_i32 t2 = tcg_temp_new_i32();
4415            TCGv_i32 t3 = tcg_temp_new_i32();
4416
4417            tcg_gen_trunc_tl_i32(t2, t0);
4418            tcg_gen_trunc_tl_i32(t3, t1);
4419            tcg_gen_andi_i32(t2, t2, 0x1f);
4420            tcg_gen_rotr_i32(t2, t3, t2);
4421            tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
4422            tcg_temp_free_i32(t2);
4423            tcg_temp_free_i32(t3);
4424        }
4425        break;
4426#if defined(TARGET_MIPS64)
4427    case OPC_DSLLV:
4428        tcg_gen_andi_tl(t0, t0, 0x3f);
4429        tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
4430        break;
4431    case OPC_DSRAV:
4432        tcg_gen_andi_tl(t0, t0, 0x3f);
4433        tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
4434        break;
4435    case OPC_DSRLV:
4436        tcg_gen_andi_tl(t0, t0, 0x3f);
4437        tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
4438        break;
4439    case OPC_DROTRV:
4440        tcg_gen_andi_tl(t0, t0, 0x3f);
4441        tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
4442        break;
4443#endif
4444    }
4445    tcg_temp_free(t0);
4446    tcg_temp_free(t1);
4447}
4448
4449#if defined(TARGET_MIPS64)
4450/* Copy GPR to and from TX79 HI1/LO1 register. */
4451static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
4452{
4453    if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
4454        /* Treat as NOP. */
4455        return;
4456    }
4457
4458    switch (opc) {
4459    case MMI_OPC_MFHI1:
4460        tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
4461        break;
4462    case MMI_OPC_MFLO1:
4463        tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
4464        break;
4465    case MMI_OPC_MTHI1:
4466        if (reg != 0) {
4467            tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
4468        } else {
4469            tcg_gen_movi_tl(cpu_HI[1], 0);
4470        }
4471        break;
4472    case MMI_OPC_MTLO1:
4473        if (reg != 0) {
4474            tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
4475        } else {
4476            tcg_gen_movi_tl(cpu_LO[1], 0);
4477        }
4478        break;
4479    default:
4480        MIPS_INVAL("mfthilo1 TX79");
4481        generate_exception_end(ctx, EXCP_RI);
4482        break;
4483    }
4484}
4485#endif
4486
4487/* Arithmetic on HI/LO registers */
4488static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
4489{
4490    if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
4491        /* Treat as NOP. */
4492        return;
4493    }
4494
4495    if (acc != 0) {
4496        check_dsp(ctx);
4497    }
4498
4499    switch (opc) {
4500    case OPC_MFHI:
4501#if defined(TARGET_MIPS64)
4502        if (acc != 0) {
4503            tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
4504        } else
4505#endif
4506        {
4507            tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
4508        }
4509        break;
4510    case OPC_MFLO:
4511#if defined(TARGET_MIPS64)
4512        if (acc != 0) {
4513            tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
4514        } else
4515#endif
4516        {
4517            tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
4518        }
4519        break;
4520    case OPC_MTHI:
4521        if (reg != 0) {
4522#if defined(TARGET_MIPS64)
4523            if (acc != 0) {
4524                tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
4525            } else
4526#endif
4527            {
4528                tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
4529            }
4530        } else {
4531            tcg_gen_movi_tl(cpu_HI[acc], 0);
4532        }
4533        break;
4534    case OPC_MTLO:
4535        if (reg != 0) {
4536#if defined(TARGET_MIPS64)
4537            if (acc != 0) {
4538                tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
4539            } else
4540#endif
4541            {
4542                tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
4543            }
4544        } else {
4545            tcg_gen_movi_tl(cpu_LO[acc], 0);
4546        }
4547        break;
4548    }
4549}
4550
4551static inline void gen_r6_ld(target_long addr, int reg, int memidx,
4552                             MemOp memop)
4553{
4554    TCGv t0 = tcg_const_tl(addr);
4555    tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
4556    gen_store_gpr(t0, reg);
4557    tcg_temp_free(t0);
4558}
4559
4560static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
4561                             int rs)
4562{
4563    target_long offset;
4564    target_long addr;
4565
4566    switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
4567    case OPC_ADDIUPC:
4568        if (rs != 0) {
4569            offset = sextract32(ctx->opcode << 2, 0, 21);
4570            addr = addr_add(ctx, pc, offset);
4571            tcg_gen_movi_tl(cpu_gpr[rs], addr);
4572        }
4573        break;
4574    case R6_OPC_LWPC:
4575        offset = sextract32(ctx->opcode << 2, 0, 21);
4576        addr = addr_add(ctx, pc, offset);
4577        gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
4578        break;
4579#if defined(TARGET_MIPS64)
4580    case OPC_LWUPC:
4581        check_mips_64(ctx);
4582        offset = sextract32(ctx->opcode << 2, 0, 21);
4583        addr = addr_add(ctx, pc, offset);
4584        gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
4585        break;
4586#endif
4587    default:
4588        switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
4589        case OPC_AUIPC:
4590            if (rs != 0) {
4591                offset = sextract32(ctx->opcode, 0, 16) << 16;
4592                addr = addr_add(ctx, pc, offset);
4593                tcg_gen_movi_tl(cpu_gpr[rs], addr);
4594            }
4595            break;
4596        case OPC_ALUIPC:
4597            if (rs != 0) {
4598                offset = sextract32(ctx->opcode, 0, 16) << 16;
4599                addr = ~0xFFFF & addr_add(ctx, pc, offset);
4600                tcg_gen_movi_tl(cpu_gpr[rs], addr);
4601            }
4602            break;
4603#if defined(TARGET_MIPS64)
4604        case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
4605        case R6_OPC_LDPC + (1 << 16):
4606        case R6_OPC_LDPC + (2 << 16):
4607        case R6_OPC_LDPC + (3 << 16):
4608            check_mips_64(ctx);
4609            offset = sextract32(ctx->opcode << 3, 0, 21);
4610            addr = addr_add(ctx, (pc & ~0x7), offset);
4611            gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEQ);
4612            break;
4613#endif
4614        default:
4615            MIPS_INVAL("OPC_PCREL");
4616            generate_exception_end(ctx, EXCP_RI);
4617            break;
4618        }
4619        break;
4620    }
4621}
4622
4623static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
4624{
4625    TCGv t0, t1;
4626
4627    if (rd == 0) {
4628        /* Treat as NOP. */
4629        return;
4630    }
4631
4632    t0 = tcg_temp_new();
4633    t1 = tcg_temp_new();
4634
4635    gen_load_gpr(t0, rs);
4636    gen_load_gpr(t1, rt);
4637
4638    switch (opc) {
4639    case R6_OPC_DIV:
4640        {
4641            TCGv t2 = tcg_temp_new();
4642            TCGv t3 = tcg_temp_new();
4643            tcg_gen_ext32s_tl(t0, t0);
4644            tcg_gen_ext32s_tl(t1, t1);
4645            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
4646            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
4647            tcg_gen_and_tl(t2, t2, t3);
4648            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4649            tcg_gen_or_tl(t2, t2, t3);
4650            tcg_gen_movi_tl(t3, 0);
4651            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4652            tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
4653            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4654            tcg_temp_free(t3);
4655            tcg_temp_free(t2);
4656        }
4657        break;
4658    case R6_OPC_MOD:
4659        {
4660            TCGv t2 = tcg_temp_new();
4661            TCGv t3 = tcg_temp_new();
4662            tcg_gen_ext32s_tl(t0, t0);
4663            tcg_gen_ext32s_tl(t1, t1);
4664            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
4665            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
4666            tcg_gen_and_tl(t2, t2, t3);
4667            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4668            tcg_gen_or_tl(t2, t2, t3);
4669            tcg_gen_movi_tl(t3, 0);
4670            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4671            tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
4672            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4673            tcg_temp_free(t3);
4674            tcg_temp_free(t2);
4675        }
4676        break;
4677    case R6_OPC_DIVU:
4678        {
4679            TCGv t2 = tcg_const_tl(0);
4680            TCGv t3 = tcg_const_tl(1);
4681            tcg_gen_ext32u_tl(t0, t0);
4682            tcg_gen_ext32u_tl(t1, t1);
4683            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4684            tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
4685            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4686            tcg_temp_free(t3);
4687            tcg_temp_free(t2);
4688        }
4689        break;
4690    case R6_OPC_MODU:
4691        {
4692            TCGv t2 = tcg_const_tl(0);
4693            TCGv t3 = tcg_const_tl(1);
4694            tcg_gen_ext32u_tl(t0, t0);
4695            tcg_gen_ext32u_tl(t1, t1);
4696            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4697            tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
4698            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4699            tcg_temp_free(t3);
4700            tcg_temp_free(t2);
4701        }
4702        break;
4703    case R6_OPC_MUL:
4704        {
4705            TCGv_i32 t2 = tcg_temp_new_i32();
4706            TCGv_i32 t3 = tcg_temp_new_i32();
4707            tcg_gen_trunc_tl_i32(t2, t0);
4708            tcg_gen_trunc_tl_i32(t3, t1);
4709            tcg_gen_mul_i32(t2, t2, t3);
4710            tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
4711            tcg_temp_free_i32(t2);
4712            tcg_temp_free_i32(t3);
4713        }
4714        break;
4715    case R6_OPC_MUH:
4716        {
4717            TCGv_i32 t2 = tcg_temp_new_i32();
4718            TCGv_i32 t3 = tcg_temp_new_i32();
4719            tcg_gen_trunc_tl_i32(t2, t0);
4720            tcg_gen_trunc_tl_i32(t3, t1);
4721            tcg_gen_muls2_i32(t2, t3, t2, t3);
4722            tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
4723            tcg_temp_free_i32(t2);
4724            tcg_temp_free_i32(t3);
4725        }
4726        break;
4727    case R6_OPC_MULU:
4728        {
4729            TCGv_i32 t2 = tcg_temp_new_i32();
4730            TCGv_i32 t3 = tcg_temp_new_i32();
4731            tcg_gen_trunc_tl_i32(t2, t0);
4732            tcg_gen_trunc_tl_i32(t3, t1);
4733            tcg_gen_mul_i32(t2, t2, t3);
4734            tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
4735            tcg_temp_free_i32(t2);
4736            tcg_temp_free_i32(t3);
4737        }
4738        break;
4739    case R6_OPC_MUHU:
4740        {
4741            TCGv_i32 t2 = tcg_temp_new_i32();
4742            TCGv_i32 t3 = tcg_temp_new_i32();
4743            tcg_gen_trunc_tl_i32(t2, t0);
4744            tcg_gen_trunc_tl_i32(t3, t1);
4745            tcg_gen_mulu2_i32(t2, t3, t2, t3);
4746            tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
4747            tcg_temp_free_i32(t2);
4748            tcg_temp_free_i32(t3);
4749        }
4750        break;
4751#if defined(TARGET_MIPS64)
4752    case R6_OPC_DDIV:
4753        {
4754            TCGv t2 = tcg_temp_new();
4755            TCGv t3 = tcg_temp_new();
4756            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
4757            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
4758            tcg_gen_and_tl(t2, t2, t3);
4759            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4760            tcg_gen_or_tl(t2, t2, t3);
4761            tcg_gen_movi_tl(t3, 0);
4762            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4763            tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
4764            tcg_temp_free(t3);
4765            tcg_temp_free(t2);
4766        }
4767        break;
4768    case R6_OPC_DMOD:
4769        {
4770            TCGv t2 = tcg_temp_new();
4771            TCGv t3 = tcg_temp_new();
4772            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
4773            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
4774            tcg_gen_and_tl(t2, t2, t3);
4775            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4776            tcg_gen_or_tl(t2, t2, t3);
4777            tcg_gen_movi_tl(t3, 0);
4778            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4779            tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
4780            tcg_temp_free(t3);
4781            tcg_temp_free(t2);
4782        }
4783        break;
4784    case R6_OPC_DDIVU:
4785        {
4786            TCGv t2 = tcg_const_tl(0);
4787            TCGv t3 = tcg_const_tl(1);
4788            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4789            tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
4790            tcg_temp_free(t3);
4791            tcg_temp_free(t2);
4792        }
4793        break;
4794    case R6_OPC_DMODU:
4795        {
4796            TCGv t2 = tcg_const_tl(0);
4797            TCGv t3 = tcg_const_tl(1);
4798            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4799            tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
4800            tcg_temp_free(t3);
4801            tcg_temp_free(t2);
4802        }
4803        break;
4804    case R6_OPC_DMUL:
4805        tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
4806        break;
4807    case R6_OPC_DMUH:
4808        {
4809            TCGv t2 = tcg_temp_new();
4810            tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
4811            tcg_temp_free(t2);
4812        }
4813        break;
4814    case R6_OPC_DMULU:
4815        tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
4816        break;
4817    case R6_OPC_DMUHU:
4818        {
4819            TCGv t2 = tcg_temp_new();
4820            tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
4821            tcg_temp_free(t2);
4822        }
4823        break;
4824#endif
4825    default:
4826        MIPS_INVAL("r6 mul/div");
4827        generate_exception_end(ctx, EXCP_RI);
4828        goto out;
4829    }
4830 out:
4831    tcg_temp_free(t0);
4832    tcg_temp_free(t1);
4833}
4834
4835#if defined(TARGET_MIPS64)
4836static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
4837{
4838    TCGv t0, t1;
4839
4840    t0 = tcg_temp_new();
4841    t1 = tcg_temp_new();
4842
4843    gen_load_gpr(t0, rs);
4844    gen_load_gpr(t1, rt);
4845
4846    switch (opc) {
4847    case MMI_OPC_DIV1:
4848        {
4849            TCGv t2 = tcg_temp_new();
4850            TCGv t3 = tcg_temp_new();
4851            tcg_gen_ext32s_tl(t0, t0);
4852            tcg_gen_ext32s_tl(t1, t1);
4853            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
4854            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
4855            tcg_gen_and_tl(t2, t2, t3);
4856            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4857            tcg_gen_or_tl(t2, t2, t3);
4858            tcg_gen_movi_tl(t3, 0);
4859            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4860            tcg_gen_div_tl(cpu_LO[1], t0, t1);
4861            tcg_gen_rem_tl(cpu_HI[1], t0, t1);
4862            tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
4863            tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
4864            tcg_temp_free(t3);
4865            tcg_temp_free(t2);
4866        }
4867        break;
4868    case MMI_OPC_DIVU1:
4869        {
4870            TCGv t2 = tcg_const_tl(0);
4871            TCGv t3 = tcg_const_tl(1);
4872            tcg_gen_ext32u_tl(t0, t0);
4873            tcg_gen_ext32u_tl(t1, t1);
4874            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4875            tcg_gen_divu_tl(cpu_LO[1], t0, t1);
4876            tcg_gen_remu_tl(cpu_HI[1], t0, t1);
4877            tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
4878            tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
4879            tcg_temp_free(t3);
4880            tcg_temp_free(t2);
4881        }
4882        break;
4883    default:
4884        MIPS_INVAL("div1 TX79");
4885        generate_exception_end(ctx, EXCP_RI);
4886        goto out;
4887    }
4888 out:
4889    tcg_temp_free(t0);
4890    tcg_temp_free(t1);
4891}
4892#endif
4893
4894static void gen_muldiv(DisasContext *ctx, uint32_t opc,
4895                       int acc, int rs, int rt)
4896{
4897    TCGv t0, t1;
4898
4899    t0 = tcg_temp_new();
4900    t1 = tcg_temp_new();
4901
4902    gen_load_gpr(t0, rs);
4903    gen_load_gpr(t1, rt);
4904
4905    if (acc != 0) {
4906        check_dsp(ctx);
4907    }
4908
4909    switch (opc) {
4910    case OPC_DIV:
4911        {
4912            TCGv t2 = tcg_temp_new();
4913            TCGv t3 = tcg_temp_new();
4914            tcg_gen_ext32s_tl(t0, t0);
4915            tcg_gen_ext32s_tl(t1, t1);
4916            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
4917            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
4918            tcg_gen_and_tl(t2, t2, t3);
4919            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4920            tcg_gen_or_tl(t2, t2, t3);
4921            tcg_gen_movi_tl(t3, 0);
4922            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4923            tcg_gen_div_tl(cpu_LO[acc], t0, t1);
4924            tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
4925            tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
4926            tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
4927            tcg_temp_free(t3);
4928            tcg_temp_free(t2);
4929        }
4930        break;
4931    case OPC_DIVU:
4932        {
4933            TCGv t2 = tcg_const_tl(0);
4934            TCGv t3 = tcg_const_tl(1);
4935            tcg_gen_ext32u_tl(t0, t0);
4936            tcg_gen_ext32u_tl(t1, t1);
4937            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4938            tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
4939            tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
4940            tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
4941            tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
4942            tcg_temp_free(t3);
4943            tcg_temp_free(t2);
4944        }
4945        break;
4946    case OPC_MULT:
4947        {
4948            TCGv_i32 t2 = tcg_temp_new_i32();
4949            TCGv_i32 t3 = tcg_temp_new_i32();
4950            tcg_gen_trunc_tl_i32(t2, t0);
4951            tcg_gen_trunc_tl_i32(t3, t1);
4952            tcg_gen_muls2_i32(t2, t3, t2, t3);
4953            tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
4954            tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
4955            tcg_temp_free_i32(t2);
4956            tcg_temp_free_i32(t3);
4957        }
4958        break;
4959    case OPC_MULTU:
4960        {
4961            TCGv_i32 t2 = tcg_temp_new_i32();
4962            TCGv_i32 t3 = tcg_temp_new_i32();
4963            tcg_gen_trunc_tl_i32(t2, t0);
4964            tcg_gen_trunc_tl_i32(t3, t1);
4965            tcg_gen_mulu2_i32(t2, t3, t2, t3);
4966            tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
4967            tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
4968            tcg_temp_free_i32(t2);
4969            tcg_temp_free_i32(t3);
4970        }
4971        break;
4972#if defined(TARGET_MIPS64)
4973    case OPC_DDIV:
4974        {
4975            TCGv t2 = tcg_temp_new();
4976            TCGv t3 = tcg_temp_new();
4977            tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
4978            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
4979            tcg_gen_and_tl(t2, t2, t3);
4980            tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
4981            tcg_gen_or_tl(t2, t2, t3);
4982            tcg_gen_movi_tl(t3, 0);
4983            tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
4984            tcg_gen_div_tl(cpu_LO[acc], t0, t1);
4985            tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
4986            tcg_temp_free(t3);
4987            tcg_temp_free(t2);
4988        }
4989        break;
4990    case OPC_DDIVU:
4991        {
4992            TCGv t2 = tcg_const_tl(0);
4993            TCGv t3 = tcg_const_tl(1);
4994            tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
4995            tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
4996            tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
4997            tcg_temp_free(t3);
4998            tcg_temp_free(t2);
4999        }
5000        break;
5001    case OPC_DMULT:
5002        tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
5003        break;
5004    case OPC_DMULTU:
5005        tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
5006        break;
5007#endif
5008    case OPC_MADD:
5009        {
5010            TCGv_i64 t2 = tcg_temp_new_i64();
5011            TCGv_i64 t3 = tcg_temp_new_i64();
5012
5013            tcg_gen_ext_tl_i64(t2, t0);
5014            tcg_gen_ext_tl_i64(t3, t1);
5015            tcg_gen_mul_i64(t2, t2, t3);
5016            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5017            tcg_gen_add_i64(t2, t2, t3);
5018            tcg_temp_free_i64(t3);
5019            gen_move_low32(cpu_LO[acc], t2);
5020            gen_move_high32(cpu_HI[acc], t2);
5021            tcg_temp_free_i64(t2);
5022        }
5023        break;
5024    case OPC_MADDU:
5025        {
5026            TCGv_i64 t2 = tcg_temp_new_i64();
5027            TCGv_i64 t3 = tcg_temp_new_i64();
5028
5029            tcg_gen_ext32u_tl(t0, t0);
5030            tcg_gen_ext32u_tl(t1, t1);
5031            tcg_gen_extu_tl_i64(t2, t0);
5032            tcg_gen_extu_tl_i64(t3, t1);
5033            tcg_gen_mul_i64(t2, t2, t3);
5034            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5035            tcg_gen_add_i64(t2, t2, t3);
5036            tcg_temp_free_i64(t3);
5037            gen_move_low32(cpu_LO[acc], t2);
5038            gen_move_high32(cpu_HI[acc], t2);
5039            tcg_temp_free_i64(t2);
5040        }
5041        break;
5042    case OPC_MSUB:
5043        {
5044            TCGv_i64 t2 = tcg_temp_new_i64();
5045            TCGv_i64 t3 = tcg_temp_new_i64();
5046
5047            tcg_gen_ext_tl_i64(t2, t0);
5048            tcg_gen_ext_tl_i64(t3, t1);
5049            tcg_gen_mul_i64(t2, t2, t3);
5050            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5051            tcg_gen_sub_i64(t2, t3, t2);
5052            tcg_temp_free_i64(t3);
5053            gen_move_low32(cpu_LO[acc], t2);
5054            gen_move_high32(cpu_HI[acc], t2);
5055            tcg_temp_free_i64(t2);
5056        }
5057        break;
5058    case OPC_MSUBU:
5059        {
5060            TCGv_i64 t2 = tcg_temp_new_i64();
5061            TCGv_i64 t3 = tcg_temp_new_i64();
5062
5063            tcg_gen_ext32u_tl(t0, t0);
5064            tcg_gen_ext32u_tl(t1, t1);
5065            tcg_gen_extu_tl_i64(t2, t0);
5066            tcg_gen_extu_tl_i64(t3, t1);
5067            tcg_gen_mul_i64(t2, t2, t3);
5068            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5069            tcg_gen_sub_i64(t2, t3, t2);
5070            tcg_temp_free_i64(t3);
5071            gen_move_low32(cpu_LO[acc], t2);
5072            gen_move_high32(cpu_HI[acc], t2);
5073            tcg_temp_free_i64(t2);
5074        }
5075        break;
5076    default:
5077        MIPS_INVAL("mul/div");
5078        generate_exception_end(ctx, EXCP_RI);
5079        goto out;
5080    }
5081 out:
5082    tcg_temp_free(t0);
5083    tcg_temp_free(t1);
5084}
5085
5086/*
5087 * These MULT[U] and MADD[U] instructions implemented in for example
5088 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
5089 * architectures are special three-operand variants with the syntax
5090 *
5091 *     MULT[U][1] rd, rs, rt
5092 *
5093 * such that
5094 *
5095 *     (rd, LO, HI) <- rs * rt
5096 *
5097 * and
5098 *
5099 *     MADD[U][1] rd, rs, rt
5100 *
5101 * such that
5102 *
5103 *     (rd, LO, HI) <- (LO, HI) + rs * rt
5104 *
5105 * where the low-order 32-bits of the result is placed into both the
5106 * GPR rd and the special register LO. The high-order 32-bits of the
5107 * result is placed into the special register HI.
5108 *
5109 * If the GPR rd is omitted in assembly language, it is taken to be 0,
5110 * which is the zero register that always reads as 0.
5111 */
5112static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
5113                         int rd, int rs, int rt)
5114{
5115    TCGv t0 = tcg_temp_new();
5116    TCGv t1 = tcg_temp_new();
5117    int acc = 0;
5118
5119    gen_load_gpr(t0, rs);
5120    gen_load_gpr(t1, rt);
5121
5122    switch (opc) {
5123    case MMI_OPC_MULT1:
5124        acc = 1;
5125        /* Fall through */
5126    case OPC_MULT:
5127        {
5128            TCGv_i32 t2 = tcg_temp_new_i32();
5129            TCGv_i32 t3 = tcg_temp_new_i32();
5130            tcg_gen_trunc_tl_i32(t2, t0);
5131            tcg_gen_trunc_tl_i32(t3, t1);
5132            tcg_gen_muls2_i32(t2, t3, t2, t3);
5133            if (rd) {
5134                tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
5135            }
5136            tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
5137            tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
5138            tcg_temp_free_i32(t2);
5139            tcg_temp_free_i32(t3);
5140        }
5141        break;
5142    case MMI_OPC_MULTU1:
5143        acc = 1;
5144        /* Fall through */
5145    case OPC_MULTU:
5146        {
5147            TCGv_i32 t2 = tcg_temp_new_i32();
5148            TCGv_i32 t3 = tcg_temp_new_i32();
5149            tcg_gen_trunc_tl_i32(t2, t0);
5150            tcg_gen_trunc_tl_i32(t3, t1);
5151            tcg_gen_mulu2_i32(t2, t3, t2, t3);
5152            if (rd) {
5153                tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
5154            }
5155            tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
5156            tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
5157            tcg_temp_free_i32(t2);
5158            tcg_temp_free_i32(t3);
5159        }
5160        break;
5161    case MMI_OPC_MADD1:
5162        acc = 1;
5163        /* Fall through */
5164    case MMI_OPC_MADD:
5165        {
5166            TCGv_i64 t2 = tcg_temp_new_i64();
5167            TCGv_i64 t3 = tcg_temp_new_i64();
5168
5169            tcg_gen_ext_tl_i64(t2, t0);
5170            tcg_gen_ext_tl_i64(t3, t1);
5171            tcg_gen_mul_i64(t2, t2, t3);
5172            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5173            tcg_gen_add_i64(t2, t2, t3);
5174            tcg_temp_free_i64(t3);
5175            gen_move_low32(cpu_LO[acc], t2);
5176            gen_move_high32(cpu_HI[acc], t2);
5177            if (rd) {
5178                gen_move_low32(cpu_gpr[rd], t2);
5179            }
5180            tcg_temp_free_i64(t2);
5181        }
5182        break;
5183    case MMI_OPC_MADDU1:
5184        acc = 1;
5185        /* Fall through */
5186    case MMI_OPC_MADDU:
5187        {
5188            TCGv_i64 t2 = tcg_temp_new_i64();
5189            TCGv_i64 t3 = tcg_temp_new_i64();
5190
5191            tcg_gen_ext32u_tl(t0, t0);
5192            tcg_gen_ext32u_tl(t1, t1);
5193            tcg_gen_extu_tl_i64(t2, t0);
5194            tcg_gen_extu_tl_i64(t3, t1);
5195            tcg_gen_mul_i64(t2, t2, t3);
5196            tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
5197            tcg_gen_add_i64(t2, t2, t3);
5198            tcg_temp_free_i64(t3);
5199            gen_move_low32(cpu_LO[acc], t2);
5200            gen_move_high32(cpu_HI[acc], t2);
5201            if (rd) {
5202                gen_move_low32(cpu_gpr[rd], t2);
5203            }
5204            tcg_temp_free_i64(t2);
5205        }
5206        break;
5207    default:
5208        MIPS_INVAL("mul/madd TXx9");
5209        generate_exception_end(ctx, EXCP_RI);
5210        goto out;
5211    }
5212
5213 out:
5214    tcg_temp_free(t0);
5215    tcg_temp_free(t1);
5216}
5217
5218static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
5219                           int rd, int rs, int rt)
5220{
5221    TCGv t0 = tcg_temp_new();
5222    TCGv t1 = tcg_temp_new();
5223
5224    gen_load_gpr(t0, rs);
5225    gen_load_gpr(t1, rt);
5226
5227    switch (opc) {
5228    case OPC_VR54XX_MULS:
5229        gen_helper_muls(t0, cpu_env, t0, t1);
5230        break;
5231    case OPC_VR54XX_MULSU:
5232        gen_helper_mulsu(t0, cpu_env, t0, t1);
5233        break;
5234    case OPC_VR54XX_MACC:
5235        gen_helper_macc(t0, cpu_env, t0, t1);
5236        break;
5237    case OPC_VR54XX_MACCU:
5238        gen_helper_maccu(t0, cpu_env, t0, t1);
5239        break;
5240    case OPC_VR54XX_MSAC:
5241        gen_helper_msac(t0, cpu_env, t0, t1);
5242        break;
5243    case OPC_VR54XX_MSACU:
5244        gen_helper_msacu(t0, cpu_env, t0, t1);
5245        break;
5246    case OPC_VR54XX_MULHI:
5247        gen_helper_mulhi(t0, cpu_env, t0, t1);
5248        break;
5249    case OPC_VR54XX_MULHIU:
5250        gen_helper_mulhiu(t0, cpu_env, t0, t1);
5251        break;
5252    case OPC_VR54XX_MULSHI:
5253        gen_helper_mulshi(t0, cpu_env, t0, t1);
5254        break;
5255    case OPC_VR54XX_MULSHIU:
5256        gen_helper_mulshiu(t0, cpu_env, t0, t1);
5257        break;
5258    case OPC_VR54XX_MACCHI:
5259        gen_helper_macchi(t0, cpu_env, t0, t1);
5260        break;
5261    case OPC_VR54XX_MACCHIU:
5262        gen_helper_macchiu(t0, cpu_env, t0, t1);
5263        break;
5264    case OPC_VR54XX_MSACHI:
5265        gen_helper_msachi(t0, cpu_env, t0, t1);
5266        break;
5267    case OPC_VR54XX_MSACHIU:
5268        gen_helper_msachiu(t0, cpu_env, t0, t1);
5269        break;
5270    default:
5271        MIPS_INVAL("mul vr54xx");
5272        generate_exception_end(ctx, EXCP_RI);
5273        goto out;
5274    }
5275    gen_store_gpr(t0, rd);
5276
5277 out:
5278    tcg_temp_free(t0);
5279    tcg_temp_free(t1);
5280}
5281
5282static void gen_cl(DisasContext *ctx, uint32_t opc,
5283                   int rd, int rs)
5284{
5285    TCGv t0;
5286
5287    if (rd == 0) {
5288        /* Treat as NOP. */
5289        return;
5290    }
5291    t0 = cpu_gpr[rd];
5292    gen_load_gpr(t0, rs);
5293
5294    switch (opc) {
5295    case OPC_CLO:
5296    case R6_OPC_CLO:
5297#if defined(TARGET_MIPS64)
5298    case OPC_DCLO:
5299    case R6_OPC_DCLO:
5300#endif
5301        tcg_gen_not_tl(t0, t0);
5302        break;
5303    }
5304
5305    switch (opc) {
5306    case OPC_CLO:
5307    case R6_OPC_CLO:
5308    case OPC_CLZ:
5309    case R6_OPC_CLZ:
5310        tcg_gen_ext32u_tl(t0, t0);
5311        tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
5312        tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
5313        break;
5314#if defined(TARGET_MIPS64)
5315    case OPC_DCLO:
5316    case R6_OPC_DCLO:
5317    case OPC_DCLZ:
5318    case R6_OPC_DCLZ:
5319        tcg_gen_clzi_i64(t0, t0, 64);
5320        break;
5321#endif
5322    }
5323}
5324
5325/* Godson integer instructions */
5326static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
5327                                 int rd, int rs, int rt)
5328{
5329    TCGv t0, t1;
5330
5331    if (rd == 0) {
5332        /* Treat as NOP. */
5333        return;
5334    }
5335
5336    switch (opc) {
5337    case OPC_MULT_G_2E:
5338    case OPC_MULT_G_2F:
5339    case OPC_MULTU_G_2E:
5340    case OPC_MULTU_G_2F:
5341#if defined(TARGET_MIPS64)
5342    case OPC_DMULT_G_2E:
5343    case OPC_DMULT_G_2F:
5344    case OPC_DMULTU_G_2E:
5345    case OPC_DMULTU_G_2F:
5346#endif
5347        t0 = tcg_temp_new();
5348        t1 = tcg_temp_new();
5349        break;
5350    default:
5351        t0 = tcg_temp_local_new();
5352        t1 = tcg_temp_local_new();
5353        break;
5354    }
5355
5356    gen_load_gpr(t0, rs);
5357    gen_load_gpr(t1, rt);
5358
5359    switch (opc) {
5360    case OPC_MULT_G_2E:
5361    case OPC_MULT_G_2F:
5362        tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
5363        tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
5364        break;
5365    case OPC_MULTU_G_2E:
5366    case OPC_MULTU_G_2F:
5367        tcg_gen_ext32u_tl(t0, t0);
5368        tcg_gen_ext32u_tl(t1, t1);
5369        tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
5370        tcg_gen_ext32s_tl(cpu_