LXR qemu/target/nios2/cpu.h

   1/*
   2 * Altera Nios II virtual CPU header
   3 *
   4 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#ifndef NIOS2_CPU_H
  22#define NIOS2_CPU_H
  23
  24#include "exec/cpu-defs.h"
  25#include "hw/core/cpu.h"
  26#include "qom/object.h"
  27
  28typedef struct CPUNios2State CPUNios2State;
  29#if !defined(CONFIG_USER_ONLY)
  30#include "mmu.h"
  31#endif
  32
  33#define TYPE_NIOS2_CPU "nios2-cpu"
  34
  35OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
  36                    NIOS2_CPU)
  37
  38/**
  39 * Nios2CPUClass:
  40 * @parent_reset: The parent class' reset handler.
  41 *
  42 * A Nios2 CPU model.
  43 */
  44struct Nios2CPUClass {
  45    /*< private >*/
  46    CPUClass parent_class;
  47    /*< public >*/
  48
  49    DeviceRealize parent_realize;
  50    DeviceReset parent_reset;
  51};
  52
  53#define TARGET_HAS_ICE 1
  54
  55/* Configuration options for Nios II */
  56#define RESET_ADDRESS         0x00000000
  57#define EXCEPTION_ADDRESS     0x00000004
  58#define FAST_TLB_MISS_ADDRESS 0x00000008
  59
  60
  61/* GP regs + CR regs + PC */
  62#define NUM_CORE_REGS (32 + 32 + 1)
  63
  64/* General purpose register aliases */
  65#define R_ZERO   0
  66#define R_AT     1
  67#define R_RET0   2
  68#define R_RET1   3
  69#define R_ARG0   4
  70#define R_ARG1   5
  71#define R_ARG2   6
  72#define R_ARG3   7
  73#define R_ET     24
  74#define R_BT     25
  75#define R_GP     26
  76#define R_SP     27
  77#define R_FP     28
  78#define R_EA     29
  79#define R_BA     30
  80#define R_RA     31
  81
  82/* Control register aliases */
  83#define CR_BASE  32
  84#define CR_STATUS    (CR_BASE + 0)
  85#define   CR_STATUS_PIE  (1 << 0)
  86#define   CR_STATUS_U    (1 << 1)
  87#define   CR_STATUS_EH   (1 << 2)
  88#define   CR_STATUS_IH   (1 << 3)
  89#define   CR_STATUS_IL   (63 << 4)
  90#define   CR_STATUS_CRS  (63 << 10)
  91#define   CR_STATUS_PRS  (63 << 16)
  92#define   CR_STATUS_NMI  (1 << 22)
  93#define   CR_STATUS_RSIE (1 << 23)
  94#define CR_ESTATUS   (CR_BASE + 1)
  95#define CR_BSTATUS   (CR_BASE + 2)
  96#define CR_IENABLE   (CR_BASE + 3)
  97#define CR_IPENDING  (CR_BASE + 4)
  98#define CR_CPUID     (CR_BASE + 5)
  99#define CR_CTL6      (CR_BASE + 6)
 100#define CR_EXCEPTION (CR_BASE + 7)
 101#define CR_PTEADDR   (CR_BASE + 8)
 102#define   CR_PTEADDR_PTBASE_SHIFT 22
 103#define   CR_PTEADDR_PTBASE_MASK  (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
 104#define   CR_PTEADDR_VPN_SHIFT    2
 105#define   CR_PTEADDR_VPN_MASK     (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
 106#define CR_TLBACC    (CR_BASE + 9)
 107#define   CR_TLBACC_IGN_SHIFT 25
 108#define   CR_TLBACC_IGN_MASK  (0x7F << CR_TLBACC_IGN_SHIFT)
 109#define   CR_TLBACC_C         (1 << 24)
 110#define   CR_TLBACC_R         (1 << 23)
 111#define   CR_TLBACC_W         (1 << 22)
 112#define   CR_TLBACC_X         (1 << 21)
 113#define   CR_TLBACC_G         (1 << 20)
 114#define   CR_TLBACC_PFN_MASK  0x000FFFFF
 115#define CR_TLBMISC   (CR_BASE + 10)
 116#define   CR_TLBMISC_WAY_SHIFT 20
 117#define   CR_TLBMISC_WAY_MASK  (0xF << CR_TLBMISC_WAY_SHIFT)
 118#define   CR_TLBMISC_RD        (1 << 19)
 119#define   CR_TLBMISC_WR        (1 << 18)
 120#define   CR_TLBMISC_PID_SHIFT 4
 121#define   CR_TLBMISC_PID_MASK  (0x3FFF << CR_TLBMISC_PID_SHIFT)
 122#define   CR_TLBMISC_DBL       (1 << 3)
 123#define   CR_TLBMISC_BAD       (1 << 2)
 124#define   CR_TLBMISC_PERM      (1 << 1)
 125#define   CR_TLBMISC_D         (1 << 0)
 126#define CR_ENCINJ    (CR_BASE + 11)
 127#define CR_BADADDR   (CR_BASE + 12)
 128#define CR_CONFIG    (CR_BASE + 13)
 129#define CR_MPUBASE   (CR_BASE + 14)
 130#define CR_MPUACC    (CR_BASE + 15)
 131
 132/* Other registers */
 133#define R_PC         64
 134
 135/* Exceptions */
 136#define EXCP_BREAK    0x1000
 137#define EXCP_RESET    0
 138#define EXCP_PRESET   1
 139#define EXCP_IRQ      2
 140#define EXCP_TRAP     3
 141#define EXCP_UNIMPL   4
 142#define EXCP_ILLEGAL  5
 143#define EXCP_UNALIGN  6
 144#define EXCP_UNALIGND 7
 145#define EXCP_DIV      8
 146#define EXCP_SUPERA   9
 147#define EXCP_SUPERI   10
 148#define EXCP_SUPERD   11
 149#define EXCP_TLBD     12
 150#define EXCP_TLBX     13
 151#define EXCP_TLBR     14
 152#define EXCP_TLBW     15
 153#define EXCP_MPUI     16
 154#define EXCP_MPUD     17
 155
 156#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 157
 158struct CPUNios2State {
 159    uint32_t regs[NUM_CORE_REGS];
 160
 161#if !defined(CONFIG_USER_ONLY)
 162    Nios2MMU mmu;
 163
 164    uint32_t irq_pending;
 165#endif
 166};
 167
 168/**
 169 * Nios2CPU:
 170 * @env: #CPUNios2State
 171 *
 172 * A Nios2 CPU.
 173 */
 174struct Nios2CPU {
 175    /*< private >*/
 176    CPUState parent_obj;
 177    /*< public >*/
 178
 179    CPUNegativeOffsetState neg;
 180    CPUNios2State env;
 181
 182    bool mmu_present;
 183    uint32_t pid_num_bits;
 184    uint32_t tlb_num_ways;
 185    uint32_t tlb_num_entries;
 186
 187    /* Addresses that are hard-coded in the FPGA build settings */
 188    uint32_t reset_addr;
 189    uint32_t exception_addr;
 190    uint32_t fast_tlb_miss_addr;
 191};
 192
 193
 194void nios2_tcg_init(void);
 195void nios2_cpu_do_interrupt(CPUState *cs);
 196void dump_mmu(CPUNios2State *env);
 197void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 198hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 199void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 200                                   MMUAccessType access_type, int mmu_idx,
 201                                   uintptr_t retaddr) QEMU_NORETURN;
 202
 203void do_nios2_semihosting(CPUNios2State *env);
 204
 205#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
 206
 207#define cpu_gen_code cpu_nios2_gen_code
 208
 209#define CPU_SAVE_VERSION 1
 210
 211/* MMU modes definitions */
 212#define MMU_SUPERVISOR_IDX  0
 213#define MMU_USER_IDX        1
 214
 215static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
 216{
 217    return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
 218                                                  MMU_SUPERVISOR_IDX;
 219}
 220
 221#ifdef CONFIG_USER_ONLY
 222void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
 223                              MMUAccessType access_type,
 224                              bool maperr, uintptr_t ra);
 225#else
 226bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 227                        MMUAccessType access_type, int mmu_idx,
 228                        bool probe, uintptr_t retaddr);
 229#endif
 230
 231static inline int cpu_interrupts_enabled(CPUNios2State *env)
 232{
 233    return env->regs[CR_STATUS] & CR_STATUS_PIE;
 234}
 235
 236typedef CPUNios2State CPUArchState;
 237typedef Nios2CPU ArchCPU;
 238
 239#include "exec/cpu-all.h"
 240
 241static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
 242                                        target_ulong *cs_base, uint32_t *flags)
 243{
 244    *pc = env->regs[R_PC];
 245    *cs_base = 0;
 246    *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
 247}
 248
 249#endif /* NIOS2_CPU_H */
 250