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20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/exec-all.h"
23#include "exec/gdbstub.h"
24#include "qemu/host-utils.h"
25#ifndef CONFIG_USER_ONLY
26#include "hw/loader.h"
27#endif
28
29void openrisc_cpu_do_interrupt(CPUState *cs)
30{
31 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
32 CPUOpenRISCState *env = &cpu->env;
33 int exception = cs->exception_index;
34
35 env->epcr = env->pc;
36 if (exception == EXCP_SYSCALL) {
37 env->epcr += 4;
38 }
39
40
41 if (exception == EXCP_ILLEGAL) {
42 env->eear = env->pc;
43 }
44
45
46 env->esr = cpu_get_sr(env);
47
48
49 env->sr &= ~SR_DME;
50 env->sr &= ~SR_IME;
51 env->sr |= SR_SM;
52 env->sr &= ~SR_IEE;
53 env->sr &= ~SR_TEE;
54 env->pmr &= ~PMR_DME;
55 env->pmr &= ~PMR_SME;
56 env->lock_addr = -1;
57
58
59 if (env->dflag) {
60 env->dflag = 0;
61 env->sr |= SR_DSX;
62 env->epcr -= 4;
63 } else {
64 env->sr &= ~SR_DSX;
65 }
66
67 if (exception > 0 && exception < EXCP_NR) {
68 static const char * const int_name[EXCP_NR] = {
69 [EXCP_RESET] = "RESET",
70 [EXCP_BUSERR] = "BUSERR (bus error)",
71 [EXCP_DPF] = "DFP (data protection fault)",
72 [EXCP_IPF] = "IPF (code protection fault)",
73 [EXCP_TICK] = "TICK (timer interrupt)",
74 [EXCP_ALIGN] = "ALIGN",
75 [EXCP_ILLEGAL] = "ILLEGAL",
76 [EXCP_INT] = "INT (device interrupt)",
77 [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)",
78 [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)",
79 [EXCP_RANGE] = "RANGE",
80 [EXCP_SYSCALL] = "SYSCALL",
81 [EXCP_FPE] = "FPE",
82 [EXCP_TRAP] = "TRAP",
83 };
84
85 qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
86
87 hwaddr vect_pc = exception << 8;
88 if (env->cpucfgr & CPUCFGR_EVBARP) {
89 vect_pc |= env->evbar;
90 }
91 if (env->sr & SR_EPH) {
92 vect_pc |= 0xf0000000;
93 }
94 env->pc = vect_pc;
95 } else {
96 cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
97 }
98
99 cs->exception_index = -1;
100}
101
102bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
103{
104 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
105 CPUOpenRISCState *env = &cpu->env;
106 int idx = -1;
107
108 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
109 idx = EXCP_INT;
110 }
111 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) {
112 idx = EXCP_TICK;
113 }
114 if (idx >= 0) {
115 cs->exception_index = idx;
116 openrisc_cpu_do_interrupt(cs);
117 return true;
118 }
119 return false;
120}
121