1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
22
23#include "qemu/int128.h"
24#include "exec/cpu-defs.h"
25#include "cpu-qom.h"
26#include "qom/object.h"
27
28#define TCG_GUEST_DEFAULT_MO 0
29
30#define TARGET_PAGE_BITS_64K 16
31#define TARGET_PAGE_BITS_16M 24
32
33#if defined(TARGET_PPC64)
34#define PPC_ELF_MACHINE EM_PPC64
35#else
36#define PPC_ELF_MACHINE EM_PPC
37#endif
38
39#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
40#define PPC_BIT32(bit) (0x80000000 >> (bit))
41#define PPC_BIT8(bit) (0x80 >> (bit))
42#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
43#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
44 PPC_BIT32(bs))
45#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
46
47
48
49enum {
50 POWERPC_EXCP_NONE = -1,
51
52 POWERPC_EXCP_CRITICAL = 0,
53 POWERPC_EXCP_MCHECK = 1,
54 POWERPC_EXCP_DSI = 2,
55 POWERPC_EXCP_ISI = 3,
56 POWERPC_EXCP_EXTERNAL = 4,
57 POWERPC_EXCP_ALIGN = 5,
58 POWERPC_EXCP_PROGRAM = 6,
59 POWERPC_EXCP_FPU = 7,
60 POWERPC_EXCP_SYSCALL = 8,
61 POWERPC_EXCP_APU = 9,
62 POWERPC_EXCP_DECR = 10,
63 POWERPC_EXCP_FIT = 11,
64 POWERPC_EXCP_WDT = 12,
65 POWERPC_EXCP_DTLB = 13,
66 POWERPC_EXCP_ITLB = 14,
67 POWERPC_EXCP_DEBUG = 15,
68
69 POWERPC_EXCP_SPEU = 32,
70 POWERPC_EXCP_EFPDI = 33,
71 POWERPC_EXCP_EFPRI = 34,
72 POWERPC_EXCP_EPERFM = 35,
73 POWERPC_EXCP_DOORI = 36,
74 POWERPC_EXCP_DOORCI = 37,
75 POWERPC_EXCP_GDOORI = 38,
76 POWERPC_EXCP_GDOORCI = 39,
77 POWERPC_EXCP_HYPPRIV = 41,
78
79
80 POWERPC_EXCP_RESET = 64,
81 POWERPC_EXCP_DSEG = 65,
82 POWERPC_EXCP_ISEG = 66,
83 POWERPC_EXCP_HDECR = 67,
84 POWERPC_EXCP_TRACE = 68,
85 POWERPC_EXCP_HDSI = 69,
86 POWERPC_EXCP_HISI = 70,
87 POWERPC_EXCP_HDSEG = 71,
88 POWERPC_EXCP_HISEG = 72,
89 POWERPC_EXCP_VPU = 73,
90
91 POWERPC_EXCP_PIT = 74,
92
93 POWERPC_EXCP_IO = 75,
94 POWERPC_EXCP_RUNM = 76,
95
96 POWERPC_EXCP_EMUL = 77,
97
98 POWERPC_EXCP_IFTLB = 78,
99 POWERPC_EXCP_DLTLB = 79,
100 POWERPC_EXCP_DSTLB = 80,
101
102 POWERPC_EXCP_FPA = 81,
103 POWERPC_EXCP_DABR = 82,
104 POWERPC_EXCP_IABR = 83,
105 POWERPC_EXCP_SMI = 84,
106 POWERPC_EXCP_PERFM = 85,
107
108 POWERPC_EXCP_THERM = 86,
109
110 POWERPC_EXCP_VPUA = 87,
111
112 POWERPC_EXCP_SOFTP = 88,
113 POWERPC_EXCP_MAINT = 89,
114
115 POWERPC_EXCP_MEXTBR = 90,
116 POWERPC_EXCP_NMEXTBR = 91,
117 POWERPC_EXCP_ITLBE = 92,
118 POWERPC_EXCP_DTLBE = 93,
119
120 POWERPC_EXCP_VSXU = 94,
121 POWERPC_EXCP_FU = 95,
122
123 POWERPC_EXCP_HV_EMU = 96,
124 POWERPC_EXCP_HV_MAINT = 97,
125 POWERPC_EXCP_HV_FU = 98,
126
127 POWERPC_EXCP_SDOOR = 99,
128 POWERPC_EXCP_SDOOR_HV = 100,
129
130 POWERPC_EXCP_HVIRT = 101,
131 POWERPC_EXCP_SYSCALL_VECTORED = 102,
132
133 POWERPC_EXCP_NB = 103,
134
135 POWERPC_EXCP_SYSCALL_USER = 0x203,
136};
137
138
139enum {
140
141 POWERPC_EXCP_ALIGN_FP = 0x01,
142 POWERPC_EXCP_ALIGN_LST = 0x02,
143 POWERPC_EXCP_ALIGN_LE = 0x03,
144 POWERPC_EXCP_ALIGN_PROT = 0x04,
145 POWERPC_EXCP_ALIGN_BAT = 0x05,
146 POWERPC_EXCP_ALIGN_CACHE = 0x06,
147 POWERPC_EXCP_ALIGN_INSN = 0x07,
148
149
150 POWERPC_EXCP_FP = 0x10,
151 POWERPC_EXCP_FP_OX = 0x01,
152 POWERPC_EXCP_FP_UX = 0x02,
153 POWERPC_EXCP_FP_ZX = 0x03,
154 POWERPC_EXCP_FP_XX = 0x04,
155 POWERPC_EXCP_FP_VXSNAN = 0x05,
156 POWERPC_EXCP_FP_VXISI = 0x06,
157 POWERPC_EXCP_FP_VXIDI = 0x07,
158 POWERPC_EXCP_FP_VXZDZ = 0x08,
159 POWERPC_EXCP_FP_VXIMZ = 0x09,
160 POWERPC_EXCP_FP_VXVC = 0x0A,
161 POWERPC_EXCP_FP_VXSOFT = 0x0B,
162 POWERPC_EXCP_FP_VXSQRT = 0x0C,
163 POWERPC_EXCP_FP_VXCVI = 0x0D,
164
165 POWERPC_EXCP_INVAL = 0x20,
166 POWERPC_EXCP_INVAL_INVAL = 0x01,
167 POWERPC_EXCP_INVAL_LSWX = 0x02,
168 POWERPC_EXCP_INVAL_SPR = 0x03,
169 POWERPC_EXCP_INVAL_FP = 0x04,
170
171 POWERPC_EXCP_PRIV = 0x30,
172 POWERPC_EXCP_PRIV_OPC = 0x01,
173 POWERPC_EXCP_PRIV_REG = 0x02,
174
175 POWERPC_EXCP_TRAP = 0x40,
176};
177
178#define PPC_INPUT(env) ((env)->bus_model)
179
180
181typedef struct opc_handler_t opc_handler_t;
182
183
184
185typedef struct DisasContext DisasContext;
186typedef struct ppc_spr_t ppc_spr_t;
187typedef union ppc_tlb_t ppc_tlb_t;
188typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
189
190
191struct ppc_spr_t {
192 const char *name;
193 target_ulong default_value;
194#ifndef CONFIG_USER_ONLY
195 unsigned int gdb_id;
196#endif
197#ifdef CONFIG_TCG
198 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
199 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
200# ifndef CONFIG_USER_ONLY
201 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
202 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
203 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
204 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
205# endif
206#endif
207#ifdef CONFIG_KVM
208
209
210
211
212
213 uint64_t one_reg_id;
214#endif
215};
216
217
218typedef union _ppc_vsr_t {
219 uint8_t u8[16];
220 uint16_t u16[8];
221 uint32_t u32[4];
222 uint64_t u64[2];
223 int8_t s8[16];
224 int16_t s16[8];
225 int32_t s32[4];
226 int64_t s64[2];
227 float32 f32[4];
228 float64 f64[2];
229 float128 f128;
230#ifdef CONFIG_INT128
231 __uint128_t u128;
232#endif
233 Int128 s128;
234} ppc_vsr_t;
235
236typedef ppc_vsr_t ppc_avr_t;
237typedef ppc_vsr_t ppc_fprp_t;
238
239#if !defined(CONFIG_USER_ONLY)
240
241typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
242struct ppc6xx_tlb_t {
243 target_ulong pte0;
244 target_ulong pte1;
245 target_ulong EPN;
246};
247
248typedef struct ppcemb_tlb_t ppcemb_tlb_t;
249struct ppcemb_tlb_t {
250 uint64_t RPN;
251 target_ulong EPN;
252 target_ulong PID;
253 target_ulong size;
254 uint32_t prot;
255 uint32_t attr;
256};
257
258typedef struct ppcmas_tlb_t {
259 uint32_t mas8;
260 uint32_t mas1;
261 uint64_t mas2;
262 uint64_t mas7_3;
263} ppcmas_tlb_t;
264
265union ppc_tlb_t {
266 ppc6xx_tlb_t *tlb6;
267 ppcemb_tlb_t *tlbe;
268 ppcmas_tlb_t *tlbm;
269};
270
271
272#define TLB_NONE 0
273#define TLB_6XX 1
274#define TLB_EMB 2
275#define TLB_MAS 3
276#endif
277
278typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
279
280typedef struct ppc_slb_t ppc_slb_t;
281struct ppc_slb_t {
282 uint64_t esid;
283 uint64_t vsid;
284 const PPCHash64SegmentPageSizes *sps;
285};
286
287#define MAX_SLB_ENTRIES 64
288#define SEGMENT_SHIFT_256M 28
289#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
290
291#define SEGMENT_SHIFT_1T 40
292#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
293
294typedef struct ppc_v3_pate_t {
295 uint64_t dw0;
296 uint64_t dw1;
297} ppc_v3_pate_t;
298
299
300
301#define MSR_SF 63
302#define MSR_TAG 62
303#define MSR_ISF 61
304#define MSR_HV 60
305#define MSR_TS0 34
306#define MSR_TS1 33
307#define MSR_TM 32
308#define MSR_CM 31
309#define MSR_ICM 30
310#define MSR_GS 28
311#define MSR_UCLE 26
312#define MSR_VR 25
313#define MSR_SPE 25
314#define MSR_AP 23
315#define MSR_VSX 23
316#define MSR_SA 22
317#define MSR_S 22
318#define MSR_KEY 19
319#define MSR_POW 18
320#define MSR_TGPR 17
321#define MSR_CE 17
322#define MSR_ILE 16
323#define MSR_EE 15
324#define MSR_PR 14
325#define MSR_FP 13
326#define MSR_ME 12
327#define MSR_FE0 11
328#define MSR_SE 10
329#define MSR_DWE 10
330#define MSR_UBLE 10
331#define MSR_BE 9
332#define MSR_DE 9
333#define MSR_FE1 8
334#define MSR_AL 7
335#define MSR_EP 6
336#define MSR_IR 5
337#define MSR_DR 4
338#define MSR_IS 5
339#define MSR_DS 4
340#define MSR_PE 3
341#define MSR_PX 2
342#define MSR_PMM 2
343#define MSR_RI 1
344#define MSR_LE 0
345
346
347#define MMCR0_FC PPC_BIT(32)
348#define MMCR0_PMAO PPC_BIT(56)
349#define MMCR0_PMAE PPC_BIT(37)
350#define MMCR0_EBE PPC_BIT(43)
351#define MMCR0_FCECE PPC_BIT(38)
352#define MMCR0_PMCC0 PPC_BIT(44)
353#define MMCR0_PMCC1 PPC_BIT(45)
354
355#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
356
357#define MMCR2_FC1P0 PPC_BIT(1)
358#define MMCR2_FC2P0 PPC_BIT(10)
359#define MMCR2_FC3P0 PPC_BIT(19)
360#define MMCR2_FC4P0 PPC_BIT(28)
361#define MMCR2_FC5P0 PPC_BIT(37)
362#define MMCR2_FC6P0 PPC_BIT(46)
363#define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
364 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
365
366
367#define LPCR_VPM0 PPC_BIT(0)
368#define LPCR_VPM1 PPC_BIT(1)
369#define LPCR_ISL PPC_BIT(2)
370#define LPCR_KBV PPC_BIT(3)
371#define LPCR_DPFD_SHIFT (63 - 11)
372#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
373#define LPCR_VRMASD_SHIFT (63 - 16)
374#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
375
376#define LPCR_PECE_U_SHIFT (63 - 19)
377#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
378#define LPCR_HVEE PPC_BIT(17)
379#define LPCR_RMLS_SHIFT (63 - 37)
380#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
381#define LPCR_HAIL PPC_BIT(37)
382#define LPCR_ILE PPC_BIT(38)
383#define LPCR_AIL_SHIFT (63 - 40)
384#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
385#define LPCR_UPRT PPC_BIT(41)
386#define LPCR_EVIRT PPC_BIT(42)
387#define LPCR_HR PPC_BIT(43)
388#define LPCR_ONL PPC_BIT(45)
389#define LPCR_LD PPC_BIT(46)
390#define LPCR_P7_PECE0 PPC_BIT(49)
391#define LPCR_P7_PECE1 PPC_BIT(50)
392#define LPCR_P7_PECE2 PPC_BIT(51)
393#define LPCR_P8_PECE0 PPC_BIT(47)
394#define LPCR_P8_PECE1 PPC_BIT(48)
395#define LPCR_P8_PECE2 PPC_BIT(49)
396#define LPCR_P8_PECE3 PPC_BIT(50)
397#define LPCR_P8_PECE4 PPC_BIT(51)
398
399#define LPCR_PECE_L_SHIFT (63 - 51)
400#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
401#define LPCR_PDEE PPC_BIT(47)
402#define LPCR_HDEE PPC_BIT(48)
403#define LPCR_EEE PPC_BIT(49)
404#define LPCR_DEE PPC_BIT(50)
405#define LPCR_OEE PPC_BIT(51)
406#define LPCR_MER PPC_BIT(52)
407#define LPCR_GTSE PPC_BIT(53)
408#define LPCR_TC PPC_BIT(54)
409#define LPCR_HEIC PPC_BIT(59)
410#define LPCR_LPES0 PPC_BIT(60)
411#define LPCR_LPES1 PPC_BIT(61)
412#define LPCR_RMI PPC_BIT(62)
413#define LPCR_HVICE PPC_BIT(62)
414#define LPCR_HDICE PPC_BIT(63)
415
416
417#define PSSCR_ESL PPC_BIT(42)
418#define PSSCR_EC PPC_BIT(43)
419
420
421#define HFSCR_MSGP PPC_BIT(53)
422#define HFSCR_IC_MSGP 0xA
423
424#define msr_sf ((env->msr >> MSR_SF) & 1)
425#define msr_isf ((env->msr >> MSR_ISF) & 1)
426#if defined(TARGET_PPC64)
427#define msr_hv ((env->msr >> MSR_HV) & 1)
428#else
429#define msr_hv (0)
430#endif
431#define msr_cm ((env->msr >> MSR_CM) & 1)
432#define msr_icm ((env->msr >> MSR_ICM) & 1)
433#define msr_gs ((env->msr >> MSR_GS) & 1)
434#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
435#define msr_vr ((env->msr >> MSR_VR) & 1)
436#define msr_spe ((env->msr >> MSR_SPE) & 1)
437#define msr_ap ((env->msr >> MSR_AP) & 1)
438#define msr_vsx ((env->msr >> MSR_VSX) & 1)
439#define msr_sa ((env->msr >> MSR_SA) & 1)
440#define msr_key ((env->msr >> MSR_KEY) & 1)
441#define msr_pow ((env->msr >> MSR_POW) & 1)
442#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
443#define msr_ce ((env->msr >> MSR_CE) & 1)
444#define msr_ile ((env->msr >> MSR_ILE) & 1)
445#define msr_ee ((env->msr >> MSR_EE) & 1)
446#define msr_pr ((env->msr >> MSR_PR) & 1)
447#define msr_fp ((env->msr >> MSR_FP) & 1)
448#define msr_me ((env->msr >> MSR_ME) & 1)
449#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
450#define msr_se ((env->msr >> MSR_SE) & 1)
451#define msr_dwe ((env->msr >> MSR_DWE) & 1)
452#define msr_uble ((env->msr >> MSR_UBLE) & 1)
453#define msr_be ((env->msr >> MSR_BE) & 1)
454#define msr_de ((env->msr >> MSR_DE) & 1)
455#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
456#define msr_al ((env->msr >> MSR_AL) & 1)
457#define msr_ep ((env->msr >> MSR_EP) & 1)
458#define msr_ir ((env->msr >> MSR_IR) & 1)
459#define msr_dr ((env->msr >> MSR_DR) & 1)
460#define msr_is ((env->msr >> MSR_IS) & 1)
461#define msr_ds ((env->msr >> MSR_DS) & 1)
462#define msr_pe ((env->msr >> MSR_PE) & 1)
463#define msr_px ((env->msr >> MSR_PX) & 1)
464#define msr_pmm ((env->msr >> MSR_PMM) & 1)
465#define msr_ri ((env->msr >> MSR_RI) & 1)
466#define msr_le ((env->msr >> MSR_LE) & 1)
467#define msr_ts ((env->msr >> MSR_TS1) & 3)
468#define msr_tm ((env->msr >> MSR_TM) & 1)
469
470#define DBCR0_ICMP (1 << 27)
471#define DBCR0_BRT (1 << 26)
472#define DBSR_ICMP (1 << 27)
473#define DBSR_BRT (1 << 26)
474
475
476#if defined(TARGET_PPC64)
477#define MSR_HVB (1ULL << MSR_HV)
478#else
479#define MSR_HVB (0ULL)
480#endif
481
482
483#define DSISR_NOPTE 0x40000000
484
485#define DSISR_PROTFAULT 0x08000000
486#define DSISR_ISSTORE 0x02000000
487
488#define DSISR_AMR 0x00200000
489
490#define DSISR_R_BADCONFIG 0x00080000
491#define DSISR_ATOMIC_RC 0x00040000
492
493#define DSISR_PRTABLE_FAULT 0x00020000
494
495
496
497#define SRR1_NOPTE DSISR_NOPTE
498
499#define SRR1_NOEXEC_GUARD 0x10000000
500#define SRR1_PROTFAULT DSISR_PROTFAULT
501#define SRR1_IAMR DSISR_AMR
502
503
504
505#define SRR1_WAKEMASK 0x003c0000
506
507#define SRR1_WAKEHMI 0x00280000
508#define SRR1_WAKEHVI 0x00240000
509#define SRR1_WAKEEE 0x00200000
510#define SRR1_WAKEDEC 0x00180000
511#define SRR1_WAKEDBELL 0x00140000
512#define SRR1_WAKERESET 0x00100000
513#define SRR1_WAKEHDBELL 0x000c0000
514#define SRR1_WAKESCOM 0x00080000
515
516
517
518#define SRR1_WAKESTATE 0x00030000
519
520#define SRR1_WS_HVLOSS 0x00030000
521#define SRR1_WS_GPRLOSS 0x00020000
522#define SRR1_WS_NOLOSS 0x00010000
523
524
525#define FSCR_EBB (63 - 56)
526#define FSCR_TAR (63 - 55)
527#define FSCR_SCV (63 - 51)
528
529#define FSCR_IC_MASK (0xFFULL)
530#define FSCR_IC_POS (63 - 7)
531#define FSCR_IC_DSCR_SPR3 2
532#define FSCR_IC_PMU 3
533#define FSCR_IC_BHRB 4
534#define FSCR_IC_TM 5
535#define FSCR_IC_EBB 7
536#define FSCR_IC_TAR 8
537#define FSCR_IC_SCV 12
538
539
540#define ESR_PIL PPC_BIT(36)
541#define ESR_PPR PPC_BIT(37)
542#define ESR_PTR PPC_BIT(38)
543#define ESR_FP PPC_BIT(39)
544#define ESR_ST PPC_BIT(40)
545#define ESR_AP PPC_BIT(44)
546#define ESR_PUO PPC_BIT(45)
547#define ESR_BO PPC_BIT(46)
548#define ESR_PIE PPC_BIT(47)
549#define ESR_DATA PPC_BIT(53)
550#define ESR_TLBI PPC_BIT(54)
551#define ESR_PT PPC_BIT(55)
552#define ESR_SPV PPC_BIT(56)
553#define ESR_EPID PPC_BIT(57)
554#define ESR_VLEMI PPC_BIT(58)
555#define ESR_MIF PPC_BIT(62)
556
557
558#define TEXASR_FAILURE_PERSISTENT (63 - 7)
559#define TEXASR_DISALLOWED (63 - 8)
560#define TEXASR_NESTING_OVERFLOW (63 - 9)
561#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
562#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
563#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
564#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
565#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
566#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
567#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
568#define TEXASR_ABORT (63 - 31)
569#define TEXASR_SUSPENDED (63 - 32)
570#define TEXASR_PRIVILEGE_HV (63 - 34)
571#define TEXASR_PRIVILEGE_PR (63 - 35)
572#define TEXASR_FAILURE_SUMMARY (63 - 36)
573#define TEXASR_TFIAR_EXACT (63 - 37)
574#define TEXASR_ROT (63 - 38)
575#define TEXASR_TRANSACTION_LEVEL (63 - 52)
576
577enum {
578 POWERPC_FLAG_NONE = 0x00000000,
579
580 POWERPC_FLAG_SPE = 0x00000001,
581 POWERPC_FLAG_VRE = 0x00000002,
582
583 POWERPC_FLAG_TGPR = 0x00000004,
584 POWERPC_FLAG_CE = 0x00000008,
585
586 POWERPC_FLAG_SE = 0x00000010,
587 POWERPC_FLAG_DWE = 0x00000020,
588 POWERPC_FLAG_UBLE = 0x00000040,
589
590 POWERPC_FLAG_BE = 0x00000080,
591 POWERPC_FLAG_DE = 0x00000100,
592
593 POWERPC_FLAG_PX = 0x00000200,
594 POWERPC_FLAG_PMM = 0x00000400,
595
596
597 POWERPC_FLAG_RTC_CLK = 0x00010000,
598 POWERPC_FLAG_BUS_CLK = 0x00020000,
599
600 POWERPC_FLAG_CFAR = 0x00040000,
601
602 POWERPC_FLAG_VSX = 0x00080000,
603
604 POWERPC_FLAG_TM = 0x00100000,
605
606 POWERPC_FLAG_SCV = 0x00200000,
607
608 POWERPC_FLAG_HID0_LE = 0x00400000,
609};
610
611
612
613
614
615
616
617
618enum {
619 HFLAGS_LE = 0,
620 HFLAGS_HV = 1,
621 HFLAGS_64 = 2,
622 HFLAGS_GTSE = 3,
623 HFLAGS_DR = 4,
624 HFLAGS_HR = 5,
625 HFLAGS_SPE = 6,
626 HFLAGS_TM = 8,
627 HFLAGS_BE = 9,
628 HFLAGS_SE = 10,
629 HFLAGS_FP = 13,
630 HFLAGS_PR = 14,
631 HFLAGS_PMCC0 = 15,
632 HFLAGS_PMCC1 = 16,
633 HFLAGS_VSX = 23,
634 HFLAGS_VR = 25,
635
636 HFLAGS_IMMU_IDX = 26,
637 HFLAGS_DMMU_IDX = 29,
638};
639
640
641
642#define FPSCR_DRN2 34
643#define FPSCR_DRN1 33
644#define FPSCR_DRN0 32
645#define FPSCR_FX 31
646#define FPSCR_FEX 30
647#define FPSCR_VX 29
648#define FPSCR_OX 28
649#define FPSCR_UX 27
650#define FPSCR_ZX 26
651#define FPSCR_XX 25
652#define FPSCR_VXSNAN 24
653#define FPSCR_VXISI 23
654#define FPSCR_VXIDI 22
655#define FPSCR_VXZDZ 21
656#define FPSCR_VXIMZ 20
657#define FPSCR_VXVC 19
658#define FPSCR_FR 18
659#define FPSCR_FI 17
660#define FPSCR_C 16
661#define FPSCR_FL 15
662#define FPSCR_FG 14
663#define FPSCR_FE 13
664#define FPSCR_FU 12
665#define FPSCR_FPCC 12
666#define FPSCR_FPRF 12
667#define FPSCR_VXSOFT 10
668#define FPSCR_VXSQRT 9
669#define FPSCR_VXCVI 8
670#define FPSCR_VE 7
671#define FPSCR_OE 6
672#define FPSCR_UE 5
673#define FPSCR_ZE 4
674#define FPSCR_XE 3
675#define FPSCR_NI 2
676#define FPSCR_RN1 1
677#define FPSCR_RN0 0
678#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
679#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
680#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
681#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
682#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
683#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
684#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
685#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
686#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
687#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
688#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
689#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
690#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
691#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
692#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
693#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
694#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
695#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
696#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
697#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
698#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
699#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
700#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
701#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
702
703#define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
704 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
705 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
706 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
707 (1 << FPSCR_VXCVI))
708
709#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
710
711#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
712 0x1F)
713
714#define FP_DRN2 (1ull << FPSCR_DRN2)
715#define FP_DRN1 (1ull << FPSCR_DRN1)
716#define FP_DRN0 (1ull << FPSCR_DRN0)
717#define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
718#define FP_FX (1ull << FPSCR_FX)
719#define FP_FEX (1ull << FPSCR_FEX)
720#define FP_VX (1ull << FPSCR_VX)
721#define FP_OX (1ull << FPSCR_OX)
722#define FP_UX (1ull << FPSCR_UX)
723#define FP_ZX (1ull << FPSCR_ZX)
724#define FP_XX (1ull << FPSCR_XX)
725#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
726#define FP_VXISI (1ull << FPSCR_VXISI)
727#define FP_VXIDI (1ull << FPSCR_VXIDI)
728#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
729#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
730#define FP_VXVC (1ull << FPSCR_VXVC)
731#define FP_FR (1ull << FPSCR_FR)
732#define FP_FI (1ull << FPSCR_FI)
733#define FP_C (1ull << FPSCR_C)
734#define FP_FL (1ull << FPSCR_FL)
735#define FP_FG (1ull << FPSCR_FG)
736#define FP_FE (1ull << FPSCR_FE)
737#define FP_FU (1ull << FPSCR_FU)
738#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
739#define FP_FPRF (FP_C | FP_FPCC)
740#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
741#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
742#define FP_VXCVI (1ull << FPSCR_VXCVI)
743#define FP_VE (1ull << FPSCR_VE)
744#define FP_OE (1ull << FPSCR_OE)
745#define FP_UE (1ull << FPSCR_UE)
746#define FP_ZE (1ull << FPSCR_ZE)
747#define FP_XE (1ull << FPSCR_XE)
748#define FP_NI (1ull << FPSCR_NI)
749#define FP_RN1 (1ull << FPSCR_RN1)
750#define FP_RN0 (1ull << FPSCR_RN0)
751#define FP_RN (FP_RN1 | FP_RN0)
752
753#define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
754#define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
755
756
757#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
758 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
759 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
760 FP_VXSQRT | FP_VXCVI)
761
762
763
764#define VSCR_NJ 16
765#define VSCR_SAT 0
766
767
768
769
770#define MAS0_NV_SHIFT 0
771#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
772
773#define MAS0_WQ_SHIFT 12
774#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
775
776#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
777
778#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
779
780#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
781
782#define MAS0_HES_SHIFT 14
783#define MAS0_HES (1 << MAS0_HES_SHIFT)
784
785#define MAS0_ESEL_SHIFT 16
786#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
787
788#define MAS0_TLBSEL_SHIFT 28
789#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
790#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
791#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
792#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
793#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
794
795#define MAS0_ATSEL_SHIFT 31
796#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
797#define MAS0_ATSEL_TLB 0
798#define MAS0_ATSEL_LRAT MAS0_ATSEL
799
800#define MAS1_TSIZE_SHIFT 7
801#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
802
803#define MAS1_TS_SHIFT 12
804#define MAS1_TS (1 << MAS1_TS_SHIFT)
805
806#define MAS1_IND_SHIFT 13
807#define MAS1_IND (1 << MAS1_IND_SHIFT)
808
809#define MAS1_TID_SHIFT 16
810#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
811
812#define MAS1_IPROT_SHIFT 30
813#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
814
815#define MAS1_VALID_SHIFT 31
816#define MAS1_VALID 0x80000000
817
818#define MAS2_EPN_SHIFT 12
819#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
820
821#define MAS2_ACM_SHIFT 6
822#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
823
824#define MAS2_VLE_SHIFT 5
825#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
826
827#define MAS2_W_SHIFT 4
828#define MAS2_W (1 << MAS2_W_SHIFT)
829
830#define MAS2_I_SHIFT 3
831#define MAS2_I (1 << MAS2_I_SHIFT)
832
833#define MAS2_M_SHIFT 2
834#define MAS2_M (1 << MAS2_M_SHIFT)
835
836#define MAS2_G_SHIFT 1
837#define MAS2_G (1 << MAS2_G_SHIFT)
838
839#define MAS2_E_SHIFT 0
840#define MAS2_E (1 << MAS2_E_SHIFT)
841
842#define MAS3_RPN_SHIFT 12
843#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
844
845#define MAS3_U0 0x00000200
846#define MAS3_U1 0x00000100
847#define MAS3_U2 0x00000080
848#define MAS3_U3 0x00000040
849#define MAS3_UX 0x00000020
850#define MAS3_SX 0x00000010
851#define MAS3_UW 0x00000008
852#define MAS3_SW 0x00000004
853#define MAS3_UR 0x00000002
854#define MAS3_SR 0x00000001
855#define MAS3_SPSIZE_SHIFT 1
856#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
857
858#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
859#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
860#define MAS4_TIDSELD_MASK 0x00030000
861#define MAS4_TIDSELD_PID0 0x00000000
862#define MAS4_TIDSELD_PID1 0x00010000
863#define MAS4_TIDSELD_PID2 0x00020000
864#define MAS4_TIDSELD_PIDZ 0x00030000
865#define MAS4_INDD 0x00008000
866#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
867#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
868#define MAS4_ACMD 0x00000040
869#define MAS4_VLED 0x00000020
870#define MAS4_WD 0x00000010
871#define MAS4_ID 0x00000008
872#define MAS4_MD 0x00000004
873#define MAS4_GD 0x00000002
874#define MAS4_ED 0x00000001
875#define MAS4_WIMGED_MASK 0x0000001f
876#define MAS4_WIMGED_SHIFT 0
877
878#define MAS5_SGS 0x80000000
879#define MAS5_SLPID_MASK 0x00000fff
880
881#define MAS6_SPID0 0x3fff0000
882#define MAS6_SPID1 0x00007ffe
883#define MAS6_ISIZE(x) MAS1_TSIZE(x)
884#define MAS6_SAS 0x00000001
885#define MAS6_SPID MAS6_SPID0
886#define MAS6_SIND 0x00000002
887#define MAS6_SIND_SHIFT 1
888#define MAS6_SPID_MASK 0x3fff0000
889#define MAS6_SPID_SHIFT 16
890#define MAS6_ISIZE_MASK 0x00000f80
891#define MAS6_ISIZE_SHIFT 7
892
893#define MAS7_RPN 0xffffffff
894
895#define MAS8_TGS 0x80000000
896#define MAS8_VF 0x40000000
897#define MAS8_TLBPID 0x00000fff
898
899
900#define MMUCFG_MAVN 0x00000003
901#define MMUCFG_MAVN_V1 0x00000000
902#define MMUCFG_MAVN_V2 0x00000001
903#define MMUCFG_NTLBS 0x0000000c
904#define MMUCFG_PIDSIZE 0x000007c0
905#define MMUCFG_TWC 0x00008000
906#define MMUCFG_LRAT 0x00010000
907#define MMUCFG_RASIZE 0x00fe0000
908#define MMUCFG_LPIDSIZE 0x0f000000
909
910
911#define MMUCSR0_TLB1FI 0x00000002
912#define MMUCSR0_TLB0FI 0x00000004
913#define MMUCSR0_TLB2FI 0x00000040
914#define MMUCSR0_TLB3FI 0x00000020
915#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
916 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
917#define MMUCSR0_TLB0PS 0x00000780
918#define MMUCSR0_TLB1PS 0x00007800
919#define MMUCSR0_TLB2PS 0x00078000
920#define MMUCSR0_TLB3PS 0x00780000
921
922
923#define TLBnCFG_N_ENTRY 0x00000fff
924#define TLBnCFG_HES 0x00002000
925#define TLBnCFG_AVAIL 0x00004000
926#define TLBnCFG_IPROT 0x00008000
927#define TLBnCFG_GTWE 0x00010000
928#define TLBnCFG_IND 0x00020000
929#define TLBnCFG_PT 0x00040000
930#define TLBnCFG_MINSIZE 0x00f00000
931#define TLBnCFG_MINSIZE_SHIFT 20
932#define TLBnCFG_MAXSIZE 0x000f0000
933#define TLBnCFG_MAXSIZE_SHIFT 16
934#define TLBnCFG_ASSOC 0xff000000
935#define TLBnCFG_ASSOC_SHIFT 24
936
937
938#define TLBnPS_4K 0x00000004
939#define TLBnPS_8K 0x00000008
940#define TLBnPS_16K 0x00000010
941#define TLBnPS_32K 0x00000020
942#define TLBnPS_64K 0x00000040
943#define TLBnPS_128K 0x00000080
944#define TLBnPS_256K 0x00000100
945#define TLBnPS_512K 0x00000200
946#define TLBnPS_1M 0x00000400
947#define TLBnPS_2M 0x00000800
948#define TLBnPS_4M 0x00001000
949#define TLBnPS_8M 0x00002000
950#define TLBnPS_16M 0x00004000
951#define TLBnPS_32M 0x00008000
952#define TLBnPS_64M 0x00010000
953#define TLBnPS_128M 0x00020000
954#define TLBnPS_256M 0x00040000
955#define TLBnPS_512M 0x00080000
956#define TLBnPS_1G 0x00100000
957#define TLBnPS_2G 0x00200000
958#define TLBnPS_4G 0x00400000
959#define TLBnPS_8G 0x00800000
960#define TLBnPS_16G 0x01000000
961#define TLBnPS_32G 0x02000000
962#define TLBnPS_64G 0x04000000
963#define TLBnPS_128G 0x08000000
964#define TLBnPS_256G 0x10000000
965
966
967#define TLBILX_T_ALL 0
968#define TLBILX_T_TID 1
969#define TLBILX_T_FULLMATCH 3
970#define TLBILX_T_CLASS0 4
971#define TLBILX_T_CLASS1 5
972#define TLBILX_T_CLASS2 6
973#define TLBILX_T_CLASS3 7
974
975
976
977#define BOOKE206_FLUSH_TLB0 (1 << 0)
978#define BOOKE206_FLUSH_TLB1 (1 << 1)
979#define BOOKE206_FLUSH_TLB2 (1 << 2)
980#define BOOKE206_FLUSH_TLB3 (1 << 3)
981
982
983#define BOOKE206_MAX_TLBN 4
984
985#define EPID_EPID_SHIFT 0x0
986#define EPID_EPID 0xFF
987#define EPID_ELPID_SHIFT 0x10
988#define EPID_ELPID 0x3F0000
989#define EPID_EGS 0x20000000
990#define EPID_EGS_SHIFT 29
991#define EPID_EAS 0x40000000
992#define EPID_EAS_SHIFT 30
993#define EPID_EPR 0x80000000
994#define EPID_EPR_SHIFT 31
995
996#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
997
998
999
1000
1001#define DBELL_TYPE_SHIFT 27
1002#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1003#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1004#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1005#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1006#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1007#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1008
1009#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1010
1011#define DBELL_BRDCAST PPC_BIT(37)
1012#define DBELL_LPIDTAG_SHIFT 14
1013#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1014#define DBELL_PIRTAG_MASK 0x3fff
1015
1016#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1017
1018#define PPC_PAGE_SIZES_MAX_SZ 8
1019
1020struct ppc_radix_page_info {
1021 uint32_t count;
1022 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1023};
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033#define PPC_TLB_EPID_LOAD 8
1034#define PPC_TLB_EPID_STORE 9
1035
1036#define PPC_CPU_OPCODES_LEN 0x40
1037#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1038
1039struct CPUPPCState {
1040
1041 target_ulong gpr[32];
1042 target_ulong gprh[32];
1043 target_ulong lr;
1044 target_ulong ctr;
1045 uint32_t crf[8];
1046#if defined(TARGET_PPC64)
1047 target_ulong cfar;
1048#endif
1049 target_ulong xer;
1050 target_ulong so;
1051 target_ulong ov;
1052 target_ulong ca;
1053 target_ulong ov32;
1054 target_ulong ca32;
1055
1056 target_ulong reserve_addr;
1057 target_ulong reserve_val;
1058 target_ulong reserve_val2;
1059
1060
1061 target_ulong msr;
1062 target_ulong tgpr[4];
1063
1064
1065 target_ulong nip;
1066 uint64_t retxh;
1067
1068
1069 int access_type;
1070
1071#if !defined(CONFIG_USER_ONLY)
1072
1073#if defined(TARGET_PPC64)
1074 ppc_slb_t slb[MAX_SLB_ENTRIES];
1075#endif
1076 target_ulong sr[32];
1077 uint32_t nb_BATs;
1078 target_ulong DBAT[2][8];
1079 target_ulong IBAT[2][8];
1080
1081 int32_t nb_tlb;
1082 int tlb_per_way;
1083 int nb_ways;
1084 int last_way;
1085 int id_tlbs;
1086 int nb_pids;
1087 int tlb_type;
1088 ppc_tlb_t tlb;
1089 target_ulong pb[4];
1090 bool tlb_dirty;
1091 bool kvm_sw_tlb;
1092 uint32_t tlb_need_flush;
1093#define TLB_NEED_LOCAL_FLUSH 0x1
1094#define TLB_NEED_GLOBAL_FLUSH 0x2
1095#endif
1096
1097
1098 target_ulong spr[1024];
1099 ppc_spr_t spr_cb[1024];
1100
1101 uint32_t vscr;
1102
1103 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1104
1105 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1106
1107 uint64_t spe_acc;
1108 uint32_t spe_fscr;
1109
1110 float_status vec_status;
1111 float_status fp_status;
1112 target_ulong fpscr;
1113
1114
1115 ppc_tb_t *tb_env;
1116 ppc_dcr_t *dcr_env;
1117
1118 int dcache_line_size;
1119 int icache_line_size;
1120
1121
1122
1123 target_ulong msr_mask;
1124 powerpc_mmu_t mmu_model;
1125 powerpc_excp_t excp_model;
1126 powerpc_input_t bus_model;
1127 int bfd_mach;
1128 uint32_t flags;
1129 uint64_t insns_flags;
1130 uint64_t insns_flags2;
1131
1132 int error_code;
1133 uint32_t pending_interrupts;
1134#if !defined(CONFIG_USER_ONLY)
1135
1136
1137
1138
1139
1140 uint32_t irq_input_state;
1141 void **irq_inputs;
1142
1143 target_ulong excp_vectors[POWERPC_EXCP_NB];
1144 target_ulong excp_prefix;
1145 target_ulong ivor_mask;
1146 target_ulong ivpr_mask;
1147 target_ulong hreset_vector;
1148 hwaddr mpic_iack;
1149 bool mpic_proxy;
1150 bool has_hv_mode;
1151
1152
1153
1154
1155
1156 bool resume_as_sreset;
1157#endif
1158
1159
1160 uint32_t hflags;
1161 target_ulong hflags_compat_nmsr;
1162
1163
1164 int (*check_pow)(CPUPPCState *env);
1165
1166#if !defined(CONFIG_USER_ONLY)
1167 void *load_info;
1168#endif
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178 uint8_t fit_period[4];
1179 uint8_t wdt_period[4];
1180
1181
1182 target_ulong tm_gpr[32];
1183 ppc_avr_t tm_vsr[64];
1184 uint64_t tm_cr;
1185 uint64_t tm_lr;
1186 uint64_t tm_ctr;
1187 uint64_t tm_fpscr;
1188 uint64_t tm_amr;
1189 uint64_t tm_ppr;
1190 uint64_t tm_vrsave;
1191 uint32_t tm_vscr;
1192 uint64_t tm_dscr;
1193 uint64_t tm_tar;
1194};
1195
1196#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1197do { \
1198 env->fit_period[0] = (a_); \
1199 env->fit_period[1] = (b_); \
1200 env->fit_period[2] = (c_); \
1201 env->fit_period[3] = (d_); \
1202 } while (0)
1203
1204#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1205do { \
1206 env->wdt_period[0] = (a_); \
1207 env->wdt_period[1] = (b_); \
1208 env->wdt_period[2] = (c_); \
1209 env->wdt_period[3] = (d_); \
1210 } while (0)
1211
1212typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1213typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223struct PowerPCCPU {
1224
1225 CPUState parent_obj;
1226
1227
1228 CPUNegativeOffsetState neg;
1229 CPUPPCState env;
1230
1231 int vcpu_id;
1232 uint32_t compat_pvr;
1233 PPCVirtualHypervisor *vhyp;
1234 void *machine_data;
1235 int32_t node_id;
1236 PPCHash64Options *hash64_opts;
1237
1238
1239
1240 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1241
1242
1243 bool pre_2_8_migration;
1244 target_ulong mig_msr_mask;
1245 uint64_t mig_insns_flags;
1246 uint64_t mig_insns_flags2;
1247 uint32_t mig_nb_BATs;
1248 bool pre_2_10_migration;
1249 bool pre_3_0_migration;
1250 int32_t mig_slb_nr;
1251};
1252
1253
1254PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1255PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1256PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1257
1258#ifndef CONFIG_USER_ONLY
1259struct PPCVirtualHypervisorClass {
1260 InterfaceClass parent;
1261 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1262 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1263 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1264 hwaddr ptex, int n);
1265 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1266 const ppc_hash_pte64_t *hptes,
1267 hwaddr ptex, int n);
1268 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1269 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1270 void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1271 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1272 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1273 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1274};
1275
1276#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1277DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1278 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1279#endif
1280
1281void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1282hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1283int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1284int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1285int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1286int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1287#ifndef CONFIG_USER_ONLY
1288void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1289const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1290#endif
1291int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1292 int cpuid, void *opaque);
1293int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1294 int cpuid, void *opaque);
1295#ifndef CONFIG_USER_ONLY
1296void ppc_cpu_do_interrupt(CPUState *cpu);
1297bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1298void ppc_cpu_do_system_reset(CPUState *cs);
1299void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1300extern const VMStateDescription vmstate_ppc_cpu;
1301#endif
1302
1303
1304void ppc_translate_init(void);
1305
1306#if !defined(CONFIG_USER_ONLY)
1307void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1308#endif
1309void ppc_store_msr(CPUPPCState *env, target_ulong value);
1310void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1311
1312void ppc_cpu_list(void);
1313
1314
1315#ifndef NO_CPU_IO_DEFS
1316uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1317uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1318void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1319void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1320uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1321uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1322void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1323void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1324uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1325void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1326bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1327target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1328void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1329target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1330void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1331void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1332uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1333void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1334uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1335uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1336#if !defined(CONFIG_USER_ONLY)
1337void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1338void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1339target_ulong load_40x_pit(CPUPPCState *env);
1340void store_40x_pit(CPUPPCState *env, target_ulong val);
1341void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1342void store_40x_sler(CPUPPCState *env, uint32_t val);
1343void store_booke_tcr(CPUPPCState *env, target_ulong val);
1344void store_booke_tsr(CPUPPCState *env, target_ulong val);
1345void ppc_tlb_invalidate_all(CPUPPCState *env);
1346void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1347void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1348int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1349 hwaddr *raddrp, target_ulong address,
1350 uint32_t pid);
1351int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
1352 hwaddr *raddrp,
1353 target_ulong address, uint32_t pid, int ext,
1354 int i);
1355hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
1356 ppcmas_tlb_t *tlb);
1357#endif
1358#endif
1359
1360void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1361void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1362 const char *caller, uint32_t cause);
1363
1364static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1365{
1366 uint64_t gprv;
1367
1368 gprv = env->gpr[gprn];
1369 if (env->flags & POWERPC_FLAG_SPE) {
1370
1371
1372
1373
1374 gprv &= 0xFFFFFFFFULL;
1375 gprv |= (uint64_t)env->gprh[gprn] << 32;
1376 }
1377
1378 return gprv;
1379}
1380
1381
1382int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1383int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1384
1385#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1386#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1387#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1388
1389#define cpu_list ppc_cpu_list
1390
1391
1392#define MMU_USER_IDX 0
1393static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1394{
1395#ifdef CONFIG_USER_ONLY
1396 return MMU_USER_IDX;
1397#else
1398 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1399#endif
1400}
1401
1402
1403#if defined(TARGET_PPC64)
1404bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1405 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1406bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1407 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1408
1409int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1410
1411#if !defined(CONFIG_USER_ONLY)
1412int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1413#endif
1414int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1415void ppc_compat_add_property(Object *obj, const char *name,
1416 uint32_t *compat_pvr, const char *basedesc);
1417#endif
1418
1419typedef CPUPPCState CPUArchState;
1420typedef PowerPCCPU ArchCPU;
1421
1422#include "exec/cpu-all.h"
1423
1424
1425
1426#define CRF_LT_BIT 3
1427#define CRF_GT_BIT 2
1428#define CRF_EQ_BIT 1
1429#define CRF_SO_BIT 0
1430#define CRF_LT (1 << CRF_LT_BIT)
1431#define CRF_GT (1 << CRF_GT_BIT)
1432#define CRF_EQ (1 << CRF_EQ_BIT)
1433#define CRF_SO (1 << CRF_SO_BIT)
1434
1435#define CRF_CH (1 << CRF_LT_BIT)
1436#define CRF_CL (1 << CRF_GT_BIT)
1437#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1438#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1439
1440
1441#define XER_SO 31
1442#define XER_OV 30
1443#define XER_CA 29
1444#define XER_OV32 19
1445#define XER_CA32 18
1446#define XER_CMP 8
1447#define XER_BC 0
1448#define xer_so (env->so)
1449#define xer_ov (env->ov)
1450#define xer_ca (env->ca)
1451#define xer_ov32 (env->ov)
1452#define xer_ca32 (env->ca)
1453#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1454#define xer_bc ((env->xer >> XER_BC) & 0x7F)
1455
1456
1457#define SPR_MQ (0x000)
1458#define SPR_XER (0x001)
1459#define SPR_601_VRTCU (0x004)
1460#define SPR_601_VRTCL (0x005)
1461#define SPR_601_UDECR (0x006)
1462#define SPR_LR (0x008)
1463#define SPR_CTR (0x009)
1464#define SPR_UAMR (0x00D)
1465#define SPR_DSCR (0x011)
1466#define SPR_DSISR (0x012)
1467#define SPR_DAR (0x013)
1468#define SPR_601_RTCU (0x014)
1469#define SPR_601_RTCL (0x015)
1470#define SPR_DECR (0x016)
1471#define SPR_SDR1 (0x019)
1472#define SPR_SRR0 (0x01A)
1473#define SPR_SRR1 (0x01B)
1474#define SPR_CFAR (0x01C)
1475#define SPR_AMR (0x01D)
1476#define SPR_ACOP (0x01F)
1477#define SPR_BOOKE_PID (0x030)
1478#define SPR_BOOKS_PID (0x030)
1479#define SPR_BOOKE_DECAR (0x036)
1480#define SPR_BOOKE_CSRR0 (0x03A)
1481#define SPR_BOOKE_CSRR1 (0x03B)
1482#define SPR_BOOKE_DEAR (0x03D)
1483#define SPR_IAMR (0x03D)
1484#define SPR_BOOKE_ESR (0x03E)
1485#define SPR_BOOKE_IVPR (0x03F)
1486#define SPR_MPC_EIE (0x050)
1487#define SPR_MPC_EID (0x051)
1488#define SPR_MPC_NRI (0x052)
1489#define SPR_TFHAR (0x080)
1490#define SPR_TFIAR (0x081)
1491#define SPR_TEXASR (0x082)
1492#define SPR_TEXASRU (0x083)
1493#define SPR_UCTRL (0x088)
1494#define SPR_TIDR (0x090)
1495#define SPR_MPC_CMPA (0x090)
1496#define SPR_MPC_CMPB (0x091)
1497#define SPR_MPC_CMPC (0x092)
1498#define SPR_MPC_CMPD (0x093)
1499#define SPR_MPC_ECR (0x094)
1500#define SPR_MPC_DER (0x095)
1501#define SPR_MPC_COUNTA (0x096)
1502#define SPR_MPC_COUNTB (0x097)
1503#define SPR_CTRL (0x098)
1504#define SPR_MPC_CMPE (0x098)
1505#define SPR_MPC_CMPF (0x099)
1506#define SPR_FSCR (0x099)
1507#define SPR_MPC_CMPG (0x09A)
1508#define SPR_MPC_CMPH (0x09B)
1509#define SPR_MPC_LCTRL1 (0x09C)
1510#define SPR_MPC_LCTRL2 (0x09D)
1511#define SPR_UAMOR (0x09D)
1512#define SPR_MPC_ICTRL (0x09E)
1513#define SPR_MPC_BAR (0x09F)
1514#define SPR_PSPB (0x09F)
1515#define SPR_DPDES (0x0B0)
1516#define SPR_DAWR0 (0x0B4)
1517#define SPR_RPR (0x0BA)
1518#define SPR_CIABR (0x0BB)
1519#define SPR_DAWRX0 (0x0BC)
1520#define SPR_HFSCR (0x0BE)
1521#define SPR_VRSAVE (0x100)
1522#define SPR_USPRG0 (0x100)
1523#define SPR_USPRG1 (0x101)
1524#define SPR_USPRG2 (0x102)
1525#define SPR_USPRG3 (0x103)
1526#define SPR_USPRG4 (0x104)
1527#define SPR_USPRG5 (0x105)
1528#define SPR_USPRG6 (0x106)
1529#define SPR_USPRG7 (0x107)
1530#define SPR_VTBL (0x10C)
1531#define SPR_VTBU (0x10D)
1532#define SPR_SPRG0 (0x110)
1533#define SPR_SPRG1 (0x111)
1534#define SPR_SPRG2 (0x112)
1535#define SPR_SPRG3 (0x113)
1536#define SPR_SPRG4 (0x114)
1537#define SPR_SCOMC (0x114)
1538#define SPR_SPRG5 (0x115)
1539#define SPR_SCOMD (0x115)
1540#define SPR_SPRG6 (0x116)
1541#define SPR_SPRG7 (0x117)
1542#define SPR_ASR (0x118)
1543#define SPR_EAR (0x11A)
1544#define SPR_TBL (0x11C)
1545#define SPR_TBU (0x11D)
1546#define SPR_TBU40 (0x11E)
1547#define SPR_SVR (0x11E)
1548#define SPR_BOOKE_PIR (0x11E)
1549#define SPR_PVR (0x11F)
1550#define SPR_HSPRG0 (0x130)
1551#define SPR_BOOKE_DBSR (0x130)
1552#define SPR_HSPRG1 (0x131)
1553#define SPR_HDSISR (0x132)
1554#define SPR_HDAR (0x133)
1555#define SPR_BOOKE_EPCR (0x133)
1556#define SPR_SPURR (0x134)
1557#define SPR_BOOKE_DBCR0 (0x134)
1558#define SPR_IBCR (0x135)
1559#define SPR_PURR (0x135)
1560#define SPR_BOOKE_DBCR1 (0x135)
1561#define SPR_DBCR (0x136)
1562#define SPR_HDEC (0x136)
1563#define SPR_BOOKE_DBCR2 (0x136)
1564#define SPR_HIOR (0x137)
1565#define SPR_MBAR (0x137)
1566#define SPR_RMOR (0x138)
1567#define SPR_BOOKE_IAC1 (0x138)
1568#define SPR_HRMOR (0x139)
1569#define SPR_BOOKE_IAC2 (0x139)
1570#define SPR_HSRR0 (0x13A)
1571#define SPR_BOOKE_IAC3 (0x13A)
1572#define SPR_HSRR1 (0x13B)
1573#define SPR_BOOKE_IAC4 (0x13B)
1574#define SPR_BOOKE_DAC1 (0x13C)
1575#define SPR_MMCRH (0x13C)
1576#define SPR_DABR2 (0x13D)
1577#define SPR_BOOKE_DAC2 (0x13D)
1578#define SPR_TFMR (0x13D)
1579#define SPR_BOOKE_DVC1 (0x13E)
1580#define SPR_LPCR (0x13E)
1581#define SPR_BOOKE_DVC2 (0x13F)
1582#define SPR_LPIDR (0x13F)
1583#define SPR_BOOKE_TSR (0x150)
1584#define SPR_HMER (0x150)
1585#define SPR_HMEER (0x151)
1586#define SPR_PCR (0x152)
1587#define SPR_BOOKE_LPIDR (0x152)
1588#define SPR_BOOKE_TCR (0x154)
1589#define SPR_BOOKE_TLB0PS (0x158)
1590#define SPR_BOOKE_TLB1PS (0x159)
1591#define SPR_BOOKE_TLB2PS (0x15A)
1592#define SPR_BOOKE_TLB3PS (0x15B)
1593#define SPR_AMOR (0x15D)
1594#define SPR_BOOKE_MAS7_MAS3 (0x174)
1595#define SPR_BOOKE_IVOR0 (0x190)
1596#define SPR_BOOKE_IVOR1 (0x191)
1597#define SPR_BOOKE_IVOR2 (0x192)
1598#define SPR_BOOKE_IVOR3 (0x193)
1599#define SPR_BOOKE_IVOR4 (0x194)
1600#define SPR_BOOKE_IVOR5 (0x195)
1601#define SPR_BOOKE_IVOR6 (0x196)
1602#define SPR_BOOKE_IVOR7 (0x197)
1603#define SPR_BOOKE_IVOR8 (0x198)
1604#define SPR_BOOKE_IVOR9 (0x199)
1605#define SPR_BOOKE_IVOR10 (0x19A)
1606#define SPR_BOOKE_IVOR11 (0x19B)
1607#define SPR_BOOKE_IVOR12 (0x19C)
1608#define SPR_BOOKE_IVOR13 (0x19D)
1609#define SPR_BOOKE_IVOR14 (0x19E)
1610#define SPR_BOOKE_IVOR15 (0x19F)
1611#define SPR_BOOKE_IVOR38 (0x1B0)
1612#define SPR_BOOKE_IVOR39 (0x1B1)
1613#define SPR_BOOKE_IVOR40 (0x1B2)
1614#define SPR_BOOKE_IVOR41 (0x1B3)
1615#define SPR_BOOKE_IVOR42 (0x1B4)
1616#define SPR_BOOKE_GIVOR2 (0x1B8)
1617#define SPR_BOOKE_GIVOR3 (0x1B9)
1618#define SPR_BOOKE_GIVOR4 (0x1BA)
1619#define SPR_BOOKE_GIVOR8 (0x1BB)
1620#define SPR_BOOKE_GIVOR13 (0x1BC)
1621#define SPR_BOOKE_GIVOR14 (0x1BD)
1622#define SPR_TIR (0x1BE)
1623#define SPR_PTCR (0x1D0)
1624#define SPR_BOOKE_SPEFSCR (0x200)
1625#define SPR_Exxx_BBEAR (0x201)
1626#define SPR_Exxx_BBTAR (0x202)
1627#define SPR_Exxx_L1CFG0 (0x203)
1628#define SPR_Exxx_L1CFG1 (0x204)
1629#define SPR_Exxx_NPIDR (0x205)
1630#define SPR_ATBL (0x20E)
1631#define SPR_ATBU (0x20F)
1632#define SPR_IBAT0U (0x210)
1633#define SPR_BOOKE_IVOR32 (0x210)
1634#define SPR_RCPU_MI_GRA (0x210)
1635#define SPR_IBAT0L (0x211)
1636#define SPR_BOOKE_IVOR33 (0x211)
1637#define SPR_IBAT1U (0x212)
1638#define SPR_BOOKE_IVOR34 (0x212)
1639#define SPR_IBAT1L (0x213)
1640#define SPR_BOOKE_IVOR35 (0x213)
1641#define SPR_IBAT2U (0x214)
1642#define SPR_BOOKE_IVOR36 (0x214)
1643#define SPR_IBAT2L (0x215)
1644#define SPR_BOOKE_IVOR37 (0x215)
1645#define SPR_IBAT3U (0x216)
1646#define SPR_IBAT3L (0x217)
1647#define SPR_DBAT0U (0x218)
1648#define SPR_RCPU_L2U_GRA (0x218)
1649#define SPR_DBAT0L (0x219)
1650#define SPR_DBAT1U (0x21A)
1651#define SPR_DBAT1L (0x21B)
1652#define SPR_DBAT2U (0x21C)
1653#define SPR_DBAT2L (0x21D)
1654#define SPR_DBAT3U (0x21E)
1655#define SPR_DBAT3L (0x21F)
1656#define SPR_IBAT4U (0x230)
1657#define SPR_RPCU_BBCMCR (0x230)
1658#define SPR_MPC_IC_CST (0x230)
1659#define SPR_Exxx_CTXCR (0x230)
1660#define SPR_IBAT4L (0x231)
1661#define SPR_MPC_IC_ADR (0x231)
1662#define SPR_Exxx_DBCR3 (0x231)
1663#define SPR_IBAT5U (0x232)
1664#define SPR_MPC_IC_DAT (0x232)
1665#define SPR_Exxx_DBCNT (0x232)
1666#define SPR_IBAT5L (0x233)
1667#define SPR_IBAT6U (0x234)
1668#define SPR_IBAT6L (0x235)
1669#define SPR_IBAT7U (0x236)
1670#define SPR_IBAT7L (0x237)
1671#define SPR_DBAT4U (0x238)
1672#define SPR_RCPU_L2U_MCR (0x238)
1673#define SPR_MPC_DC_CST (0x238)
1674#define SPR_Exxx_ALTCTXCR (0x238)
1675#define SPR_DBAT4L (0x239)
1676#define SPR_MPC_DC_ADR (0x239)
1677#define SPR_DBAT5U (0x23A)
1678#define SPR_BOOKE_MCSRR0 (0x23A)
1679#define SPR_MPC_DC_DAT (0x23A)
1680#define SPR_DBAT5L (0x23B)
1681#define SPR_BOOKE_MCSRR1 (0x23B)
1682#define SPR_DBAT6U (0x23C)
1683#define SPR_BOOKE_MCSR (0x23C)
1684#define SPR_DBAT6L (0x23D)
1685#define SPR_Exxx_MCAR (0x23D)
1686#define SPR_DBAT7U (0x23E)
1687#define SPR_BOOKE_DSRR0 (0x23E)
1688#define SPR_DBAT7L (0x23F)
1689#define SPR_BOOKE_DSRR1 (0x23F)
1690#define SPR_BOOKE_SPRG8 (0x25C)
1691#define SPR_BOOKE_SPRG9 (0x25D)
1692#define SPR_BOOKE_MAS0 (0x270)
1693#define SPR_BOOKE_MAS1 (0x271)
1694#define SPR_BOOKE_MAS2 (0x272)
1695#define SPR_BOOKE_MAS3 (0x273)
1696#define SPR_BOOKE_MAS4 (0x274)
1697#define SPR_BOOKE_MAS5 (0x275)
1698#define SPR_BOOKE_MAS6 (0x276)
1699#define SPR_BOOKE_PID1 (0x279)
1700#define SPR_BOOKE_PID2 (0x27A)
1701#define SPR_MPC_DPDR (0x280)
1702#define SPR_MPC_IMMR (0x288)
1703#define SPR_BOOKE_TLB0CFG (0x2B0)
1704#define SPR_BOOKE_TLB1CFG (0x2B1)
1705#define SPR_BOOKE_TLB2CFG (0x2B2)
1706#define SPR_BOOKE_TLB3CFG (0x2B3)
1707#define SPR_BOOKE_EPR (0x2BE)
1708#define SPR_PERF0 (0x300)
1709#define SPR_RCPU_MI_RBA0 (0x300)
1710#define SPR_MPC_MI_CTR (0x300)
1711#define SPR_POWER_USIER (0x300)
1712#define SPR_PERF1 (0x301)
1713#define SPR_RCPU_MI_RBA1 (0x301)
1714#define SPR_POWER_UMMCR2 (0x301)
1715#define SPR_PERF2 (0x302)
1716#define SPR_RCPU_MI_RBA2 (0x302)
1717#define SPR_MPC_MI_AP (0x302)
1718#define SPR_POWER_UMMCRA (0x302)
1719#define SPR_PERF3 (0x303)
1720#define SPR_RCPU_MI_RBA3 (0x303)
1721#define SPR_MPC_MI_EPN (0x303)
1722#define SPR_POWER_UPMC1 (0x303)
1723#define SPR_PERF4 (0x304)
1724#define SPR_POWER_UPMC2 (0x304)
1725#define SPR_PERF5 (0x305)
1726#define SPR_MPC_MI_TWC (0x305)
1727#define SPR_POWER_UPMC3 (0x305)
1728#define SPR_PERF6 (0x306)
1729#define SPR_MPC_MI_RPN (0x306)
1730#define SPR_POWER_UPMC4 (0x306)
1731#define SPR_PERF7 (0x307)
1732#define SPR_POWER_UPMC5 (0x307)
1733#define SPR_PERF8 (0x308)
1734#define SPR_RCPU_L2U_RBA0 (0x308)
1735#define SPR_MPC_MD_CTR (0x308)
1736#define SPR_POWER_UPMC6 (0x308)
1737#define SPR_PERF9 (0x309)
1738#define SPR_RCPU_L2U_RBA1 (0x309)
1739#define SPR_MPC_MD_CASID (0x309)
1740#define SPR_970_UPMC7 (0X309)
1741#define SPR_PERFA (0x30A)
1742#define SPR_RCPU_L2U_RBA2 (0x30A)
1743#define SPR_MPC_MD_AP (0x30A)
1744#define SPR_970_UPMC8 (0X30A)
1745#define SPR_PERFB (0x30B)
1746#define SPR_RCPU_L2U_RBA3 (0x30B)
1747#define SPR_MPC_MD_EPN (0x30B)
1748#define SPR_POWER_UMMCR0 (0X30B)
1749#define SPR_PERFC (0x30C)
1750#define SPR_MPC_MD_TWB (0x30C)
1751#define SPR_POWER_USIAR (0X30C)
1752#define SPR_PERFD (0x30D)
1753#define SPR_MPC_MD_TWC (0x30D)
1754#define SPR_POWER_USDAR (0X30D)
1755#define SPR_PERFE (0x30E)
1756#define SPR_MPC_MD_RPN (0x30E)
1757#define SPR_POWER_UMMCR1 (0X30E)
1758#define SPR_PERFF (0x30F)
1759#define SPR_MPC_MD_TW (0x30F)
1760#define SPR_UPERF0 (0x310)
1761#define SPR_POWER_SIER (0x310)
1762#define SPR_UPERF1 (0x311)
1763#define SPR_POWER_MMCR2 (0x311)
1764#define SPR_UPERF2 (0x312)
1765#define SPR_POWER_MMCRA (0X312)
1766#define SPR_UPERF3 (0x313)
1767#define SPR_POWER_PMC1 (0X313)
1768#define SPR_UPERF4 (0x314)
1769#define SPR_POWER_PMC2 (0X314)
1770#define SPR_UPERF5 (0x315)
1771#define SPR_POWER_PMC3 (0X315)
1772#define SPR_UPERF6 (0x316)
1773#define SPR_POWER_PMC4 (0X316)
1774#define SPR_UPERF7 (0x317)
1775#define SPR_POWER_PMC5 (0X317)
1776#define SPR_UPERF8 (0x318)
1777#define SPR_POWER_PMC6 (0X318)
1778#define SPR_UPERF9 (0x319)
1779#define SPR_970_PMC7 (0X319)
1780#define SPR_UPERFA (0x31A)
1781#define SPR_970_PMC8 (0X31A)
1782#define SPR_UPERFB (0x31B)
1783#define SPR_POWER_MMCR0 (0X31B)
1784#define SPR_UPERFC (0x31C)
1785#define SPR_POWER_SIAR (0X31C)
1786#define SPR_UPERFD (0x31D)
1787#define SPR_POWER_SDAR (0X31D)
1788#define SPR_UPERFE (0x31E)
1789#define SPR_POWER_MMCR1 (0X31E)
1790#define SPR_UPERFF (0x31F)
1791#define SPR_RCPU_MI_RA0 (0x320)
1792#define SPR_MPC_MI_DBCAM (0x320)
1793#define SPR_BESCRS (0x320)
1794#define SPR_RCPU_MI_RA1 (0x321)
1795#define SPR_MPC_MI_DBRAM0 (0x321)
1796#define SPR_BESCRSU (0x321)
1797#define SPR_RCPU_MI_RA2 (0x322)
1798#define SPR_MPC_MI_DBRAM1 (0x322)
1799#define SPR_BESCRR (0x322)
1800#define SPR_RCPU_MI_RA3 (0x323)
1801#define SPR_BESCRRU (0x323)
1802#define SPR_EBBHR (0x324)
1803#define SPR_EBBRR (0x325)
1804#define SPR_BESCR (0x326)
1805#define SPR_RCPU_L2U_RA0 (0x328)
1806#define SPR_MPC_MD_DBCAM (0x328)
1807#define SPR_RCPU_L2U_RA1 (0x329)
1808#define SPR_MPC_MD_DBRAM0 (0x329)
1809#define SPR_RCPU_L2U_RA2 (0x32A)
1810#define SPR_MPC_MD_DBRAM1 (0x32A)
1811#define SPR_RCPU_L2U_RA3 (0x32B)
1812#define SPR_TAR (0x32F)
1813#define SPR_ASDR (0x330)
1814#define SPR_IC (0x350)
1815#define SPR_VTB (0x351)
1816#define SPR_MMCRC (0x353)
1817#define SPR_PSSCR (0x357)
1818#define SPR_440_INV0 (0x370)
1819#define SPR_440_INV1 (0x371)
1820#define SPR_440_INV2 (0x372)
1821#define SPR_440_INV3 (0x373)
1822#define SPR_440_ITV0 (0x374)
1823#define SPR_440_ITV1 (0x375)
1824#define SPR_440_ITV2 (0x376)
1825#define SPR_440_ITV3 (0x377)
1826#define SPR_440_CCR1 (0x378)
1827#define SPR_TACR (0x378)
1828#define SPR_TCSCR (0x379)
1829#define SPR_CSIGR (0x37a)
1830#define SPR_DCRIPR (0x37B)
1831#define SPR_POWER_SPMC1 (0x37C)
1832#define SPR_POWER_SPMC2 (0x37D)
1833#define SPR_POWER_MMCRS (0x37E)
1834#define SPR_WORT (0x37F)
1835#define SPR_PPR (0x380)
1836#define SPR_750_GQR0 (0x390)
1837#define SPR_440_DNV0 (0x390)
1838#define SPR_750_GQR1 (0x391)
1839#define SPR_440_DNV1 (0x391)
1840#define SPR_750_GQR2 (0x392)
1841#define SPR_440_DNV2 (0x392)
1842#define SPR_750_GQR3 (0x393)
1843#define SPR_440_DNV3 (0x393)
1844#define SPR_750_GQR4 (0x394)
1845#define SPR_440_DTV0 (0x394)
1846#define SPR_750_GQR5 (0x395)
1847#define SPR_440_DTV1 (0x395)
1848#define SPR_750_GQR6 (0x396)
1849#define SPR_440_DTV2 (0x396)
1850#define SPR_750_GQR7 (0x397)
1851#define SPR_440_DTV3 (0x397)
1852#define SPR_750_THRM4 (0x398)
1853#define SPR_750CL_HID2 (0x398)
1854#define SPR_440_DVLIM (0x398)
1855#define SPR_750_WPAR (0x399)
1856#define SPR_440_IVLIM (0x399)
1857#define SPR_TSCR (0x399)
1858#define SPR_750_DMAU (0x39A)
1859#define SPR_750_DMAL (0x39B)
1860#define SPR_440_RSTCFG (0x39B)
1861#define SPR_BOOKE_DCDBTRL (0x39C)
1862#define SPR_BOOKE_DCDBTRH (0x39D)
1863#define SPR_BOOKE_ICDBTRL (0x39E)
1864#define SPR_BOOKE_ICDBTRH (0x39F)
1865#define SPR_74XX_UMMCR2 (0x3A0)
1866#define SPR_7XX_UPMC5 (0x3A1)
1867#define SPR_7XX_UPMC6 (0x3A2)
1868#define SPR_UBAMR (0x3A7)
1869#define SPR_7XX_UMMCR0 (0x3A8)
1870#define SPR_7XX_UPMC1 (0x3A9)
1871#define SPR_7XX_UPMC2 (0x3AA)
1872#define SPR_7XX_USIAR (0x3AB)
1873#define SPR_7XX_UMMCR1 (0x3AC)
1874#define SPR_7XX_UPMC3 (0x3AD)
1875#define SPR_7XX_UPMC4 (0x3AE)
1876#define SPR_USDA (0x3AF)
1877#define SPR_40x_ZPR (0x3B0)
1878#define SPR_BOOKE_MAS7 (0x3B0)
1879#define SPR_74XX_MMCR2 (0x3B0)
1880#define SPR_7XX_PMC5 (0x3B1)
1881#define SPR_40x_PID (0x3B1)
1882#define SPR_7XX_PMC6 (0x3B2)
1883#define SPR_440_MMUCR (0x3B2)
1884#define SPR_4xx_CCR0 (0x3B3)
1885#define SPR_BOOKE_EPLC (0x3B3)
1886#define SPR_405_IAC3 (0x3B4)
1887#define SPR_BOOKE_EPSC (0x3B4)
1888#define SPR_405_IAC4 (0x3B5)
1889#define SPR_405_DVC1 (0x3B6)
1890#define SPR_405_DVC2 (0x3B7)
1891#define SPR_BAMR (0x3B7)
1892#define SPR_7XX_MMCR0 (0x3B8)
1893#define SPR_7XX_PMC1 (0x3B9)
1894#define SPR_40x_SGR (0x3B9)
1895#define SPR_7XX_PMC2 (0x3BA)
1896#define SPR_40x_DCWR (0x3BA)
1897#define SPR_7XX_SIAR (0x3BB)
1898#define SPR_405_SLER (0x3BB)
1899#define SPR_7XX_MMCR1 (0x3BC)
1900#define SPR_405_SU0R (0x3BC)
1901#define SPR_401_SKR (0x3BC)
1902#define SPR_7XX_PMC3 (0x3BD)
1903#define SPR_405_DBCR1 (0x3BD)
1904#define SPR_7XX_PMC4 (0x3BE)
1905#define SPR_SDA (0x3BF)
1906#define SPR_403_VTBL (0x3CC)
1907#define SPR_403_VTBU (0x3CD)
1908#define SPR_DMISS (0x3D0)
1909#define SPR_DCMP (0x3D1)
1910#define SPR_HASH1 (0x3D2)
1911#define SPR_HASH2 (0x3D3)
1912#define SPR_BOOKE_ICDBDR (0x3D3)
1913#define SPR_TLBMISS (0x3D4)
1914#define SPR_IMISS (0x3D4)
1915#define SPR_40x_ESR (0x3D4)
1916#define SPR_PTEHI (0x3D5)
1917#define SPR_ICMP (0x3D5)
1918#define SPR_40x_DEAR (0x3D5)
1919#define SPR_PTELO (0x3D6)
1920#define SPR_RPA (0x3D6)
1921#define SPR_40x_EVPR (0x3D6)
1922#define SPR_L3PM (0x3D7)
1923#define SPR_403_CDBCR (0x3D7)
1924#define SPR_L3ITCR0 (0x3D8)
1925#define SPR_TCR (0x3D8)
1926#define SPR_40x_TSR (0x3D8)
1927#define SPR_IBR (0x3DA)
1928#define SPR_40x_TCR (0x3DA)
1929#define SPR_ESASRR (0x3DB)
1930#define SPR_40x_PIT (0x3DB)
1931#define SPR_403_TBL (0x3DC)
1932#define SPR_403_TBU (0x3DD)
1933#define SPR_SEBR (0x3DE)
1934#define SPR_40x_SRR2 (0x3DE)
1935#define SPR_SER (0x3DF)
1936#define SPR_40x_SRR3 (0x3DF)
1937#define SPR_L3OHCR (0x3E8)
1938#define SPR_L3ITCR1 (0x3E9)
1939#define SPR_L3ITCR2 (0x3EA)
1940#define SPR_L3ITCR3 (0x3EB)
1941#define SPR_HID0 (0x3F0)
1942#define SPR_40x_DBSR (0x3F0)
1943#define SPR_HID1 (0x3F1)
1944#define SPR_IABR (0x3F2)
1945#define SPR_40x_DBCR0 (0x3F2)
1946#define SPR_601_HID2 (0x3F2)
1947#define SPR_Exxx_L1CSR0 (0x3F2)
1948#define SPR_ICTRL (0x3F3)
1949#define SPR_HID2 (0x3F3)
1950#define SPR_750CL_HID4 (0x3F3)
1951#define SPR_Exxx_L1CSR1 (0x3F3)
1952#define SPR_440_DBDR (0x3F3)
1953#define SPR_LDSTDB (0x3F4)
1954#define SPR_750_TDCL (0x3F4)
1955#define SPR_40x_IAC1 (0x3F4)
1956#define SPR_MMUCSR0 (0x3F4)
1957#define SPR_970_HID4 (0x3F4)
1958#define SPR_DABR (0x3F5)
1959#define DABR_MASK (~(target_ulong)0x7)
1960#define SPR_Exxx_BUCSR (0x3F5)
1961#define SPR_40x_IAC2 (0x3F5)
1962#define SPR_601_HID5 (0x3F5)
1963#define SPR_40x_DAC1 (0x3F6)
1964#define SPR_MSSCR0 (0x3F6)
1965#define SPR_970_HID5 (0x3F6)
1966#define SPR_MSSSR0 (0x3F7)
1967#define SPR_MSSCR1 (0x3F7)
1968#define SPR_DABRX (0x3F7)
1969#define SPR_40x_DAC2 (0x3F7)
1970#define SPR_MMUCFG (0x3F7)
1971#define SPR_LDSTCR (0x3F8)
1972#define SPR_L2PMCR (0x3F8)
1973#define SPR_750FX_HID2 (0x3F8)
1974#define SPR_Exxx_L1FINV0 (0x3F8)
1975#define SPR_L2CR (0x3F9)
1976#define SPR_Exxx_L2CSR0 (0x3F9)
1977#define SPR_L3CR (0x3FA)
1978#define SPR_750_TDCH (0x3FA)
1979#define SPR_IABR2 (0x3FA)
1980#define SPR_40x_DCCR (0x3FA)
1981#define SPR_ICTC (0x3FB)
1982#define SPR_40x_ICCR (0x3FB)
1983#define SPR_THRM1 (0x3FC)
1984#define SPR_403_PBL1 (0x3FC)
1985#define SPR_SP (0x3FD)
1986#define SPR_THRM2 (0x3FD)
1987#define SPR_403_PBU1 (0x3FD)
1988#define SPR_604_HID13 (0x3FD)
1989#define SPR_LT (0x3FE)
1990#define SPR_THRM3 (0x3FE)
1991#define SPR_RCPU_FPECR (0x3FE)
1992#define SPR_403_PBL2 (0x3FE)
1993#define SPR_PIR (0x3FF)
1994#define SPR_403_PBU2 (0x3FF)
1995#define SPR_601_HID15 (0x3FF)
1996#define SPR_604_HID15 (0x3FF)
1997#define SPR_E500_SVR (0x3FF)
1998
1999
2000#define EPCR_DMIUH (1 << 22)
2001
2002#define EPCR_DGTMI (1 << 23)
2003
2004#define EPCR_GICM (1 << 24)
2005
2006#define EPCR_ICM (1 << 25)
2007
2008#define EPCR_DUVD (1 << 26)
2009
2010#define EPCR_ISIGS (1 << 27)
2011
2012#define EPCR_DSIGS (1 << 28)
2013
2014#define EPCR_ITLBGS (1 << 29)
2015
2016#define EPCR_DTLBGS (1 << 30)
2017
2018#define EPCR_EXTGS (1 << 31)
2019
2020#define L1CSR0_CPE 0x00010000
2021#define L1CSR0_CUL 0x00000400
2022#define L1CSR0_DCLFR 0x00000100
2023#define L1CSR0_DCFI 0x00000002
2024#define L1CSR0_DCE 0x00000001
2025
2026#define L1CSR1_CPE 0x00010000
2027#define L1CSR1_ICUL 0x00000400
2028#define L1CSR1_ICLFR 0x00000100
2029#define L1CSR1_ICFI 0x00000002
2030#define L1CSR1_ICE 0x00000001
2031
2032
2033#define E500_L2CSR0_L2FI (1 << 21)
2034#define E500_L2CSR0_L2FL (1 << 11)
2035#define E500_L2CSR0_L2LFC (1 << 10)
2036
2037
2038#define HID0_DEEPNAP (1 << 24)
2039#define HID0_DOZE (1 << 23)
2040#define HID0_NAP (1 << 22)
2041#define HID0_HILE PPC_BIT(19)
2042#define HID0_POWER9_HILE PPC_BIT(4)
2043
2044
2045
2046enum {
2047 PPC_NONE = 0x0000000000000000ULL,
2048
2049 PPC_INSNS_BASE = 0x0000000000000001ULL,
2050
2051#define PPC_INTEGER PPC_INSNS_BASE
2052
2053#define PPC_FLOW PPC_INSNS_BASE
2054
2055#define PPC_MEM PPC_INSNS_BASE
2056
2057#define PPC_RES PPC_INSNS_BASE
2058
2059#define PPC_MISC PPC_INSNS_BASE
2060
2061
2062 PPC_POWER = 0x0000000000000002ULL,
2063
2064 PPC_POWER2 = 0x0000000000000004ULL,
2065
2066 PPC_POWER_RTC = 0x0000000000000008ULL,
2067
2068 PPC_POWER_BR = 0x0000000000000010ULL,
2069
2070 PPC_64B = 0x0000000000000020ULL,
2071
2072 PPC_64BX = 0x0000000000000040ULL,
2073
2074 PPC_64H = 0x0000000000000080ULL,
2075
2076 PPC_WAIT = 0x0000000000000100ULL,
2077
2078 PPC_MFTB = 0x0000000000000200ULL,
2079
2080
2081
2082 PPC_602_SPEC = 0x0000000000000400ULL,
2083
2084 PPC_ISEL = 0x0000000000000800ULL,
2085
2086 PPC_POPCNTB = 0x0000000000001000ULL,
2087
2088 PPC_STRING = 0x0000000000002000ULL,
2089
2090 PPC_CILDST = 0x0000000000004000ULL,
2091
2092
2093
2094 PPC_FLOAT = 0x0000000000010000ULL,
2095
2096 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2097 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2098 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2099 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2100 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2101 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2102 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2103
2104
2105
2106 PPC_ALTIVEC = 0x0000000001000000ULL,
2107
2108 PPC_SPE = 0x0000000002000000ULL,
2109
2110 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2111
2112 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2113
2114
2115 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2116 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2117 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2118
2119 PPC_MEM_SYNC = 0x0000000080000000ULL,
2120
2121 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2122
2123
2124 PPC_CACHE = 0x0000000200000000ULL,
2125
2126 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2127
2128 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2129
2130 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2131
2132 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2133
2134
2135
2136 PPC_EXTERN = 0x0000010000000000ULL,
2137
2138 PPC_SEGMENT = 0x0000020000000000ULL,
2139
2140 PPC_6xx_TLB = 0x0000040000000000ULL,
2141
2142 PPC_74xx_TLB = 0x0000080000000000ULL,
2143
2144 PPC_40x_TLB = 0x0000100000000000ULL,
2145
2146 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2147
2148 PPC_SLBI = 0x0000400000000000ULL,
2149
2150
2151 PPC_WRTEE = 0x0001000000000000ULL,
2152
2153 PPC_40x_EXCP = 0x0002000000000000ULL,
2154
2155 PPC_405_MAC = 0x0004000000000000ULL,
2156
2157 PPC_440_SPEC = 0x0008000000000000ULL,
2158
2159 PPC_BOOKE = 0x0010000000000000ULL,
2160
2161 PPC_MFAPIDI = 0x0020000000000000ULL,
2162
2163 PPC_TLBIVA = 0x0040000000000000ULL,
2164
2165 PPC_TLBIVAX = 0x0080000000000000ULL,
2166
2167 PPC_4xx_COMMON = 0x0100000000000000ULL,
2168
2169 PPC_40x_ICBT = 0x0200000000000000ULL,
2170
2171 PPC_RFMCI = 0x0400000000000000ULL,
2172
2173 PPC_RFDI = 0x0800000000000000ULL,
2174
2175 PPC_DCR = 0x1000000000000000ULL,
2176
2177 PPC_DCRX = 0x2000000000000000ULL,
2178
2179 PPC_DCRUX = 0x4000000000000000ULL,
2180
2181 PPC_POPCNTWD = 0x8000000000000000ULL,
2182
2183#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2184 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2185 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2186 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2187 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2188 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2189 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2190 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2191 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2192 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2193 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2194 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2195 | PPC_CACHE | PPC_CACHE_ICBI \
2196 | PPC_CACHE_DCBZ \
2197 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2198 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2199 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2200 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2201 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2202 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2203 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2204 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2205 | PPC_POPCNTWD | PPC_CILDST)
2206
2207
2208
2209
2210 PPC2_BOOKE206 = 0x0000000000000001ULL,
2211
2212 PPC2_VSX = 0x0000000000000002ULL,
2213
2214 PPC2_DFP = 0x0000000000000004ULL,
2215
2216 PPC2_PRCNTL = 0x0000000000000008ULL,
2217
2218 PPC2_DBRX = 0x0000000000000010ULL,
2219
2220 PPC2_ISA205 = 0x0000000000000020ULL,
2221
2222 PPC2_VSX207 = 0x0000000000000040ULL,
2223
2224 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2225
2226 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2227
2228 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2229
2230 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2231
2232 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2233
2234 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2235
2236 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2237
2238 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2239
2240 PPC2_ISA207S = 0x0000000000008000ULL,
2241
2242 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2243
2244 PPC2_TM = 0x0000000000020000ULL,
2245
2246 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2247
2248 PPC2_ISA300 = 0x0000000000080000ULL,
2249
2250 PPC2_ISA310 = 0x0000000000100000ULL,
2251
2252#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2253 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2254 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2255 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2256 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2257 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2258 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2259 PPC2_ISA300 | PPC2_ISA310)
2260};
2261
2262
2263
2264
2265
2266
2267enum {
2268
2269 ACCESS_CODE = 0x10,
2270 ACCESS_INT = 0x20,
2271 ACCESS_FLOAT = 0x30,
2272 ACCESS_RES = 0x40,
2273 ACCESS_EXT = 0x50,
2274 ACCESS_CACHE = 0x60,
2275};
2276
2277
2278
2279
2280
2281
2282enum {
2283
2284 PPC6xx_INPUT_HRESET = 0,
2285 PPC6xx_INPUT_SRESET = 1,
2286 PPC6xx_INPUT_CKSTP_IN = 2,
2287 PPC6xx_INPUT_MCP = 3,
2288 PPC6xx_INPUT_SMI = 4,
2289 PPC6xx_INPUT_INT = 5,
2290 PPC6xx_INPUT_TBEN = 6,
2291 PPC6xx_INPUT_WAKEUP = 7,
2292 PPC6xx_INPUT_NB,
2293};
2294
2295enum {
2296
2297 PPCBookE_INPUT_HRESET = 0,
2298 PPCBookE_INPUT_SRESET = 1,
2299 PPCBookE_INPUT_CKSTP_IN = 2,
2300 PPCBookE_INPUT_MCP = 3,
2301 PPCBookE_INPUT_SMI = 4,
2302 PPCBookE_INPUT_INT = 5,
2303 PPCBookE_INPUT_CINT = 6,
2304 PPCBookE_INPUT_NB,
2305};
2306
2307enum {
2308
2309 PPCE500_INPUT_RESET_CORE = 0,
2310 PPCE500_INPUT_MCK = 1,
2311 PPCE500_INPUT_CINT = 3,
2312 PPCE500_INPUT_INT = 4,
2313 PPCE500_INPUT_DEBUG = 6,
2314 PPCE500_INPUT_NB,
2315};
2316
2317enum {
2318
2319 PPC40x_INPUT_RESET_CORE = 0,
2320 PPC40x_INPUT_RESET_CHIP = 1,
2321 PPC40x_INPUT_RESET_SYS = 2,
2322 PPC40x_INPUT_CINT = 3,
2323 PPC40x_INPUT_INT = 4,
2324 PPC40x_INPUT_HALT = 5,
2325 PPC40x_INPUT_DEBUG = 6,
2326 PPC40x_INPUT_NB,
2327};
2328
2329enum {
2330
2331 PPCRCPU_INPUT_PORESET = 0,
2332 PPCRCPU_INPUT_HRESET = 1,
2333 PPCRCPU_INPUT_SRESET = 2,
2334 PPCRCPU_INPUT_IRQ0 = 3,
2335 PPCRCPU_INPUT_IRQ1 = 4,
2336 PPCRCPU_INPUT_IRQ2 = 5,
2337 PPCRCPU_INPUT_IRQ3 = 6,
2338 PPCRCPU_INPUT_IRQ4 = 7,
2339 PPCRCPU_INPUT_IRQ5 = 8,
2340 PPCRCPU_INPUT_IRQ6 = 9,
2341 PPCRCPU_INPUT_IRQ7 = 10,
2342 PPCRCPU_INPUT_NB,
2343};
2344
2345#if defined(TARGET_PPC64)
2346enum {
2347
2348 PPC970_INPUT_HRESET = 0,
2349 PPC970_INPUT_SRESET = 1,
2350 PPC970_INPUT_CKSTP = 2,
2351 PPC970_INPUT_TBEN = 3,
2352 PPC970_INPUT_MCP = 4,
2353 PPC970_INPUT_INT = 5,
2354 PPC970_INPUT_THINT = 6,
2355 PPC970_INPUT_NB,
2356};
2357
2358enum {
2359
2360 POWER7_INPUT_INT = 0,
2361
2362
2363
2364
2365
2366 POWER7_INPUT_NB,
2367};
2368
2369enum {
2370
2371 POWER9_INPUT_INT = 0,
2372 POWER9_INPUT_HINT = 1,
2373 POWER9_INPUT_NB,
2374};
2375#endif
2376
2377
2378enum {
2379
2380 PPC_INTERRUPT_RESET = 0,
2381 PPC_INTERRUPT_WAKEUP,
2382 PPC_INTERRUPT_MCK,
2383 PPC_INTERRUPT_EXT,
2384 PPC_INTERRUPT_SMI,
2385 PPC_INTERRUPT_CEXT,
2386 PPC_INTERRUPT_DEBUG,
2387 PPC_INTERRUPT_THERM,
2388
2389 PPC_INTERRUPT_DECR,
2390 PPC_INTERRUPT_HDECR,
2391 PPC_INTERRUPT_PIT,
2392 PPC_INTERRUPT_FIT,
2393 PPC_INTERRUPT_WDT,
2394 PPC_INTERRUPT_CDOORBELL,
2395 PPC_INTERRUPT_DOORBELL,
2396 PPC_INTERRUPT_PERFM,
2397 PPC_INTERRUPT_HMI,
2398 PPC_INTERRUPT_HDOORBELL,
2399 PPC_INTERRUPT_HVIRT,
2400};
2401
2402
2403enum {
2404 PCR_COMPAT_2_05 = PPC_BIT(62),
2405 PCR_COMPAT_2_06 = PPC_BIT(61),
2406 PCR_COMPAT_2_07 = PPC_BIT(60),
2407 PCR_COMPAT_3_00 = PPC_BIT(59),
2408 PCR_COMPAT_3_10 = PPC_BIT(58),
2409 PCR_VEC_DIS = PPC_BIT(0),
2410 PCR_VSX_DIS = PPC_BIT(1),
2411 PCR_TM_DIS = PPC_BIT(2),
2412};
2413
2414
2415enum {
2416 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2417 HMER_PROC_RECV_DONE = PPC_BIT(2),
2418 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2419 HMER_TFAC_ERROR = PPC_BIT(4),
2420 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2421 HMER_XSCOM_FAIL = PPC_BIT(8),
2422 HMER_XSCOM_DONE = PPC_BIT(9),
2423 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2424 HMER_WARN_RISE = PPC_BIT(14),
2425 HMER_WARN_FALL = PPC_BIT(15),
2426 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2427 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2428 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2429 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2430};
2431
2432
2433
2434#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2435target_ulong cpu_read_xer(const CPUPPCState *env);
2436void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2437
2438
2439
2440
2441
2442#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2443
2444#ifdef CONFIG_DEBUG_TCG
2445void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2446 target_ulong *cs_base, uint32_t *flags);
2447#else
2448static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2449 target_ulong *cs_base, uint32_t *flags)
2450{
2451 *pc = env->nip;
2452 *cs_base = 0;
2453 *flags = env->hflags;
2454}
2455#endif
2456
2457void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2458void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2459 uintptr_t raddr);
2460void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2461 uint32_t error_code);
2462void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2463 uint32_t error_code, uintptr_t raddr);
2464
2465#if !defined(CONFIG_USER_ONLY)
2466static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2467{
2468 uintptr_t tlbml = (uintptr_t)tlbm;
2469 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2470
2471 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2472}
2473
2474static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2475{
2476 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2477 int r = tlbncfg & TLBnCFG_N_ENTRY;
2478 return r;
2479}
2480
2481static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2482{
2483 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2484 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2485 return r;
2486}
2487
2488static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2489{
2490 int id = booke206_tlbm_id(env, tlbm);
2491 int end = 0;
2492 int i;
2493
2494 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2495 end += booke206_tlb_size(env, i);
2496 if (id < end) {
2497 return i;
2498 }
2499 }
2500
2501 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2502 return 0;
2503}
2504
2505static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2506{
2507 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2508 int tlbid = booke206_tlbm_id(env, tlb);
2509 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2510}
2511
2512static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2513 target_ulong ea, int way)
2514{
2515 int r;
2516 uint32_t ways = booke206_tlb_ways(env, tlbn);
2517 int ways_bits = ctz32(ways);
2518 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2519 int i;
2520
2521 way &= ways - 1;
2522 ea >>= MAS2_EPN_SHIFT;
2523 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2524 r = (ea << ways_bits) | way;
2525
2526 if (r >= booke206_tlb_size(env, tlbn)) {
2527 return NULL;
2528 }
2529
2530
2531 for (i = 0; i < tlbn; i++) {
2532 r += booke206_tlb_size(env, i);
2533 }
2534
2535 return &env->tlb.tlbm[r];
2536}
2537
2538
2539static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2540{
2541 uint32_t ret = 0;
2542
2543 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2544
2545 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2546 } else {
2547 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2548 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2549 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2550 int i;
2551 for (i = min; i <= max; i++) {
2552 ret |= (1 << (i << 1));
2553 }
2554 }
2555
2556 return ret;
2557}
2558
2559static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2560 ppcmas_tlb_t *tlb)
2561{
2562 uint8_t i;
2563 int32_t tsize = -1;
2564
2565 for (i = 0; i < 32; i++) {
2566 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2567 if (tsize == -1) {
2568 tsize = i;
2569 } else {
2570 return;
2571 }
2572 }
2573 }
2574
2575
2576 assert(tsize != -1);
2577 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2578 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2579}
2580
2581#endif
2582
2583static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2584{
2585 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2586 return msr & (1ULL << MSR_CM);
2587 }
2588
2589 return msr & (1ULL << MSR_SF);
2590}
2591
2592
2593
2594
2595
2596static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2597{
2598 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2599 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2600}
2601
2602
2603#if defined(HOST_WORDS_BIGENDIAN)
2604#define VsrB(i) u8[i]
2605#define VsrSB(i) s8[i]
2606#define VsrH(i) u16[i]
2607#define VsrSH(i) s16[i]
2608#define VsrW(i) u32[i]
2609#define VsrSW(i) s32[i]
2610#define VsrD(i) u64[i]
2611#define VsrSD(i) s64[i]
2612#else
2613#define VsrB(i) u8[15 - (i)]
2614#define VsrSB(i) s8[15 - (i)]
2615#define VsrH(i) u16[7 - (i)]
2616#define VsrSH(i) s16[7 - (i)]
2617#define VsrW(i) u32[3 - (i)]
2618#define VsrSW(i) s32[3 - (i)]
2619#define VsrD(i) u64[1 - (i)]
2620#define VsrSD(i) s64[1 - (i)]
2621#endif
2622
2623static inline int vsr64_offset(int i, bool high)
2624{
2625 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2626}
2627
2628static inline int vsr_full_offset(int i)
2629{
2630 return offsetof(CPUPPCState, vsr[i].u64[0]);
2631}
2632
2633static inline int fpr_offset(int i)
2634{
2635 return vsr64_offset(i, true);
2636}
2637
2638static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2639{
2640 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2641}
2642
2643static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2644{
2645 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2646}
2647
2648static inline long avr64_offset(int i, bool high)
2649{
2650 return vsr64_offset(i + 32, high);
2651}
2652
2653static inline int avr_full_offset(int i)
2654{
2655 return vsr_full_offset(i + 32);
2656}
2657
2658static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2659{
2660 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2661}
2662
2663static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2664{
2665
2666 return cpu->env.spr_cb[spr].name != NULL;
2667}
2668
2669static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu)
2670{
2671 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2672
2673
2674
2675
2676
2677 if (pcc->lpcr_mask & LPCR_ILE) {
2678 return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
2679 }
2680
2681 return false;
2682}
2683
2684void dump_mmu(CPUPPCState *env);
2685
2686void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2687void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2688uint32_t ppc_get_vscr(CPUPPCState *env);
2689#endif
2690