qemu/target/ppc/translate_init.inc.c
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   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "disas/dis-asm.h"
  22#include "exec/gdbstub.h"
  23#include "kvm_ppc.h"
  24#include "sysemu/arch_init.h"
  25#include "sysemu/cpus.h"
  26#include "sysemu/hw_accel.h"
  27#include "sysemu/tcg.h"
  28#include "cpu-models.h"
  29#include "mmu-hash32.h"
  30#include "mmu-hash64.h"
  31#include "qemu/error-report.h"
  32#include "qemu/module.h"
  33#include "qemu/qemu-print.h"
  34#include "qapi/error.h"
  35#include "qapi/qmp/qnull.h"
  36#include "qapi/visitor.h"
  37#include "hw/qdev-properties.h"
  38#include "hw/ppc/ppc.h"
  39#include "mmu-book3s-v3.h"
  40#include "sysemu/qtest.h"
  41#include "qemu/cutils.h"
  42#include "disas/capstone.h"
  43#include "fpu/softfloat.h"
  44#include "qapi/qapi-commands-machine-target.h"
  45
  46/* #define PPC_DUMP_CPU */
  47/* #define PPC_DEBUG_SPR */
  48/* #define PPC_DUMP_SPR_ACCESSES */
  49/* #define USE_APPLE_GDB */
  50
  51/*
  52 * Generic callbacks:
  53 * do nothing but store/retrieve spr value
  54 */
  55static void spr_load_dump_spr(int sprn)
  56{
  57#ifdef PPC_DUMP_SPR_ACCESSES
  58    TCGv_i32 t0 = tcg_const_i32(sprn);
  59    gen_helper_load_dump_spr(cpu_env, t0);
  60    tcg_temp_free_i32(t0);
  61#endif
  62}
  63
  64static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
  65{
  66    gen_load_spr(cpu_gpr[gprn], sprn);
  67    spr_load_dump_spr(sprn);
  68}
  69
  70static void spr_store_dump_spr(int sprn)
  71{
  72#ifdef PPC_DUMP_SPR_ACCESSES
  73    TCGv_i32 t0 = tcg_const_i32(sprn);
  74    gen_helper_store_dump_spr(cpu_env, t0);
  75    tcg_temp_free_i32(t0);
  76#endif
  77}
  78
  79static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
  80{
  81    gen_store_spr(sprn, cpu_gpr[gprn]);
  82    spr_store_dump_spr(sprn);
  83}
  84
  85#if !defined(CONFIG_USER_ONLY)
  86static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
  87{
  88#ifdef TARGET_PPC64
  89    TCGv t0 = tcg_temp_new();
  90    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
  91    gen_store_spr(sprn, t0);
  92    tcg_temp_free(t0);
  93    spr_store_dump_spr(sprn);
  94#else
  95    spr_write_generic(ctx, sprn, gprn);
  96#endif
  97}
  98
  99static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
 100{
 101    TCGv t0 = tcg_temp_new();
 102    TCGv t1 = tcg_temp_new();
 103    gen_load_spr(t0, sprn);
 104    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 105    tcg_gen_and_tl(t0, t0, t1);
 106    gen_store_spr(sprn, t0);
 107    tcg_temp_free(t0);
 108    tcg_temp_free(t1);
 109}
 110
 111static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
 112{
 113}
 114
 115#endif
 116
 117/* SPR common to all PowerPC */
 118/* XER */
 119static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
 120{
 121    gen_read_xer(ctx, cpu_gpr[gprn]);
 122}
 123
 124static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
 125{
 126    gen_write_xer(cpu_gpr[gprn]);
 127}
 128
 129/* LR */
 130static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
 131{
 132    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 133}
 134
 135static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 136{
 137    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 138}
 139
 140/* CFAR */
 141#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 142static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 143{
 144    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
 145}
 146
 147static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 148{
 149    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
 150}
 151#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
 152
 153/* CTR */
 154static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
 155{
 156    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 157}
 158
 159static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
 160{
 161    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 162}
 163
 164/* User read access to SPR */
 165/* USPRx */
 166/* UMMCRx */
 167/* UPMCx */
 168/* USIA */
 169/* UDECR */
 170static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
 171{
 172    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 173}
 174
 175#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 176static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 177{
 178    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
 179}
 180#endif
 181
 182/* SPR common to all non-embedded PowerPC */
 183/* DECR */
 184#if !defined(CONFIG_USER_ONLY)
 185static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
 186{
 187    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 188        gen_io_start();
 189    }
 190    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 191    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 192        gen_io_end();
 193        gen_stop_exception(ctx);
 194    }
 195}
 196
 197static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 198{
 199    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 200        gen_io_start();
 201    }
 202    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 203    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 204        gen_io_end();
 205        gen_stop_exception(ctx);
 206    }
 207}
 208#endif
 209
 210/* SPR common to all non-embedded PowerPC, except 601 */
 211/* Time base */
 212static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
 213{
 214    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 215        gen_io_start();
 216    }
 217    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 218    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 219        gen_io_end();
 220        gen_stop_exception(ctx);
 221    }
 222}
 223
 224static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
 225{
 226    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 227        gen_io_start();
 228    }
 229    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 230    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 231        gen_io_end();
 232        gen_stop_exception(ctx);
 233    }
 234}
 235
 236ATTRIBUTE_UNUSED
 237static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
 238{
 239    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
 240}
 241
 242ATTRIBUTE_UNUSED
 243static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
 244{
 245    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
 246}
 247
 248#if !defined(CONFIG_USER_ONLY)
 249static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
 250{
 251    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 252        gen_io_start();
 253    }
 254    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 255    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 256        gen_io_end();
 257        gen_stop_exception(ctx);
 258    }
 259}
 260
 261static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
 262{
 263    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 264        gen_io_start();
 265    }
 266    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 267    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 268        gen_io_end();
 269        gen_stop_exception(ctx);
 270    }
 271}
 272
 273ATTRIBUTE_UNUSED
 274static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
 275{
 276    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
 277}
 278
 279ATTRIBUTE_UNUSED
 280static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
 281{
 282    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
 283}
 284
 285#if defined(TARGET_PPC64)
 286ATTRIBUTE_UNUSED
 287static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
 288{
 289    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 290}
 291
 292/* HDECR */
 293static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
 294{
 295    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 296        gen_io_start();
 297    }
 298    gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
 299    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 300        gen_io_end();
 301        gen_stop_exception(ctx);
 302    }
 303}
 304
 305static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
 306{
 307    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 308        gen_io_start();
 309    }
 310    gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
 311    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 312        gen_io_end();
 313        gen_stop_exception(ctx);
 314    }
 315}
 316
 317#endif
 318#endif
 319
 320#if !defined(CONFIG_USER_ONLY)
 321/* IBAT0U...IBAT0U */
 322/* IBAT0L...IBAT7L */
 323static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
 324{
 325    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 326                  offsetof(CPUPPCState,
 327                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 328}
 329
 330static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
 331{
 332    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 333                  offsetof(CPUPPCState,
 334                           IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
 335}
 336
 337static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
 338{
 339    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 340    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 341    tcg_temp_free_i32(t0);
 342}
 343
 344static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
 345{
 346    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 347    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 348    tcg_temp_free_i32(t0);
 349}
 350
 351static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
 352{
 353    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 354    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 355    tcg_temp_free_i32(t0);
 356}
 357
 358static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
 359{
 360    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 361    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 362    tcg_temp_free_i32(t0);
 363}
 364
 365/* DBAT0U...DBAT7U */
 366/* DBAT0L...DBAT7L */
 367static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
 368{
 369    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 370                  offsetof(CPUPPCState,
 371                           DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 372}
 373
 374static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
 375{
 376    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 377                  offsetof(CPUPPCState,
 378                           DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 379}
 380
 381static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
 382{
 383    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 384    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 385    tcg_temp_free_i32(t0);
 386}
 387
 388static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
 389{
 390    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 391    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 392    tcg_temp_free_i32(t0);
 393}
 394
 395static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
 396{
 397    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 398    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 399    tcg_temp_free_i32(t0);
 400}
 401
 402static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
 403{
 404    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 405    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 406    tcg_temp_free_i32(t0);
 407}
 408
 409/* SDR1 */
 410static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
 411{
 412    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
 413}
 414
 415#if defined(TARGET_PPC64)
 416/* 64 bits PowerPC specific SPRs */
 417/* PIDR */
 418static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
 419{
 420    gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
 421}
 422
 423static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
 424{
 425    gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
 426}
 427
 428static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
 429{
 430    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
 431}
 432
 433static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
 434{
 435    TCGv t0 = tcg_temp_new();
 436    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 437    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 438    tcg_temp_free(t0);
 439}
 440static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
 441{
 442    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
 443}
 444
 445static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
 446{
 447    gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
 448}
 449#endif
 450#endif
 451
 452/* PowerPC 601 specific registers */
 453/* RTC */
 454static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
 455{
 456    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
 457}
 458
 459static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
 460{
 461    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
 462}
 463
 464#if !defined(CONFIG_USER_ONLY)
 465static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
 466{
 467    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
 468}
 469
 470static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
 471{
 472    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
 473}
 474
 475static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
 476{
 477    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
 478    /* Must stop the translation as endianness may have changed */
 479    gen_stop_exception(ctx);
 480}
 481#endif
 482
 483/* Unified bats */
 484#if !defined(CONFIG_USER_ONLY)
 485static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
 486{
 487    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 488                  offsetof(CPUPPCState,
 489                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 490}
 491
 492static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
 493{
 494    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 495    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
 496    tcg_temp_free_i32(t0);
 497}
 498
 499static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
 500{
 501    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 502    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
 503    tcg_temp_free_i32(t0);
 504}
 505#endif
 506
 507/* PowerPC 40x specific registers */
 508#if !defined(CONFIG_USER_ONLY)
 509static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
 510{
 511    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 512}
 513
 514static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
 515{
 516    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 517}
 518
 519static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 520{
 521    gen_store_spr(sprn, cpu_gpr[gprn]);
 522    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
 523    /* We must stop translation as we may have rebooted */
 524    gen_stop_exception(ctx);
 525}
 526
 527static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
 528{
 529    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 530}
 531
 532static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
 533{
 534    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 535}
 536
 537static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
 538{
 539    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 540}
 541#endif
 542
 543/* PowerPC 403 specific registers */
 544/* PBL1 / PBU1 / PBL2 / PBU2 */
 545#if !defined(CONFIG_USER_ONLY)
 546static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
 547{
 548    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 549                  offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
 550}
 551
 552static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
 553{
 554    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 555    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
 556    tcg_temp_free_i32(t0);
 557}
 558
 559static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
 560{
 561    TCGv t0 = tcg_temp_new();
 562    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 563    gen_store_spr(SPR_PIR, t0);
 564    tcg_temp_free(t0);
 565}
 566#endif
 567
 568/* SPE specific registers */
 569static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
 570{
 571    TCGv_i32 t0 = tcg_temp_new_i32();
 572    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 573    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 574    tcg_temp_free_i32(t0);
 575}
 576
 577static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
 578{
 579    TCGv_i32 t0 = tcg_temp_new_i32();
 580    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 581    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 582    tcg_temp_free_i32(t0);
 583}
 584
 585#if !defined(CONFIG_USER_ONLY)
 586/* Callback used to write the exception vector base */
 587static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
 588{
 589    TCGv t0 = tcg_temp_new();
 590    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
 591    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 592    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 593    gen_store_spr(sprn, t0);
 594    tcg_temp_free(t0);
 595}
 596
 597static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
 598{
 599    int sprn_offs;
 600
 601    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 602        sprn_offs = sprn - SPR_BOOKE_IVOR0;
 603    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 604        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
 605    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
 606        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
 607    } else {
 608        printf("Trying to write an unknown exception vector %d %03x\n",
 609               sprn, sprn);
 610        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 611        return;
 612    }
 613
 614    TCGv t0 = tcg_temp_new();
 615    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
 616    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 617    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
 618    gen_store_spr(sprn, t0);
 619    tcg_temp_free(t0);
 620}
 621#endif
 622
 623static inline void vscr_init(CPUPPCState *env, uint32_t val)
 624{
 625    /* Altivec always uses round-to-nearest */
 626    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 627    helper_mtvscr(env, val);
 628}
 629
 630#ifdef CONFIG_USER_ONLY
 631#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 632                         oea_read, oea_write, one_reg_id, initial_value)       \
 633    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 634#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 635                            oea_read, oea_write, hea_read, hea_write,          \
 636                            one_reg_id, initial_value)                         \
 637    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 638#else
 639#if !defined(CONFIG_KVM)
 640#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 641                         oea_read, oea_write, one_reg_id, initial_value)       \
 642    _spr_register(env, num, name, uea_read, uea_write,                         \
 643                  oea_read, oea_write, oea_read, oea_write, initial_value)
 644#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 645                            oea_read, oea_write, hea_read, hea_write,          \
 646                            one_reg_id, initial_value)                         \
 647    _spr_register(env, num, name, uea_read, uea_write,                         \
 648                  oea_read, oea_write, hea_read, hea_write, initial_value)
 649#else
 650#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 651                         oea_read, oea_write, one_reg_id, initial_value)       \
 652    _spr_register(env, num, name, uea_read, uea_write,                         \
 653                  oea_read, oea_write, oea_read, oea_write,                    \
 654                  one_reg_id, initial_value)
 655#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 656                            oea_read, oea_write, hea_read, hea_write,          \
 657                            one_reg_id, initial_value)                         \
 658    _spr_register(env, num, name, uea_read, uea_write,                         \
 659                  oea_read, oea_write, hea_read, hea_write,                    \
 660                  one_reg_id, initial_value)
 661#endif
 662#endif
 663
 664#define spr_register(env, num, name, uea_read, uea_write,                      \
 665                     oea_read, oea_write, initial_value)                       \
 666    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
 667                     oea_read, oea_write, 0, initial_value)
 668
 669#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
 670                        oea_read, oea_write, hea_read, hea_write,              \
 671                        initial_value)                                         \
 672    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
 673                        oea_read, oea_write, hea_read, hea_write,              \
 674                        0, initial_value)
 675
 676static inline void _spr_register(CPUPPCState *env, int num,
 677                                 const char *name,
 678                                 void (*uea_read)(DisasContext *ctx,
 679                                                  int gprn, int sprn),
 680                                 void (*uea_write)(DisasContext *ctx,
 681                                                   int sprn, int gprn),
 682#if !defined(CONFIG_USER_ONLY)
 683
 684                                 void (*oea_read)(DisasContext *ctx,
 685                                                  int gprn, int sprn),
 686                                 void (*oea_write)(DisasContext *ctx,
 687                                                   int sprn, int gprn),
 688                                 void (*hea_read)(DisasContext *opaque,
 689                                                  int gprn, int sprn),
 690                                 void (*hea_write)(DisasContext *opaque,
 691                                                   int sprn, int gprn),
 692#endif
 693#if defined(CONFIG_KVM)
 694                                 uint64_t one_reg_id,
 695#endif
 696                                 target_ulong initial_value)
 697{
 698    ppc_spr_t *spr;
 699
 700    spr = &env->spr_cb[num];
 701    if (spr->name != NULL || env->spr[num] != 0x00000000 ||
 702#if !defined(CONFIG_USER_ONLY)
 703        spr->oea_read != NULL || spr->oea_write != NULL ||
 704#endif
 705        spr->uea_read != NULL || spr->uea_write != NULL) {
 706        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 707        exit(1);
 708    }
 709#if defined(PPC_DEBUG_SPR)
 710    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 711           name, initial_value);
 712#endif
 713    spr->name = name;
 714    spr->uea_read = uea_read;
 715    spr->uea_write = uea_write;
 716#if !defined(CONFIG_USER_ONLY)
 717    spr->oea_read = oea_read;
 718    spr->oea_write = oea_write;
 719    spr->hea_read = hea_read;
 720    spr->hea_write = hea_write;
 721#endif
 722#if defined(CONFIG_KVM)
 723    spr->one_reg_id = one_reg_id,
 724#endif
 725    env->spr[num] = spr->default_value = initial_value;
 726}
 727
 728/* Generic PowerPC SPRs */
 729static void gen_spr_generic(CPUPPCState *env)
 730{
 731    /* Integer processing */
 732    spr_register(env, SPR_XER, "XER",
 733                 &spr_read_xer, &spr_write_xer,
 734                 &spr_read_xer, &spr_write_xer,
 735                 0x00000000);
 736    /* Branch contol */
 737    spr_register(env, SPR_LR, "LR",
 738                 &spr_read_lr, &spr_write_lr,
 739                 &spr_read_lr, &spr_write_lr,
 740                 0x00000000);
 741    spr_register(env, SPR_CTR, "CTR",
 742                 &spr_read_ctr, &spr_write_ctr,
 743                 &spr_read_ctr, &spr_write_ctr,
 744                 0x00000000);
 745    /* Interrupt processing */
 746    spr_register(env, SPR_SRR0, "SRR0",
 747                 SPR_NOACCESS, SPR_NOACCESS,
 748                 &spr_read_generic, &spr_write_generic,
 749                 0x00000000);
 750    spr_register(env, SPR_SRR1, "SRR1",
 751                 SPR_NOACCESS, SPR_NOACCESS,
 752                 &spr_read_generic, &spr_write_generic,
 753                 0x00000000);
 754    /* Processor control */
 755    spr_register(env, SPR_SPRG0, "SPRG0",
 756                 SPR_NOACCESS, SPR_NOACCESS,
 757                 &spr_read_generic, &spr_write_generic,
 758                 0x00000000);
 759    spr_register(env, SPR_SPRG1, "SPRG1",
 760                 SPR_NOACCESS, SPR_NOACCESS,
 761                 &spr_read_generic, &spr_write_generic,
 762                 0x00000000);
 763    spr_register(env, SPR_SPRG2, "SPRG2",
 764                 SPR_NOACCESS, SPR_NOACCESS,
 765                 &spr_read_generic, &spr_write_generic,
 766                 0x00000000);
 767    spr_register(env, SPR_SPRG3, "SPRG3",
 768                 SPR_NOACCESS, SPR_NOACCESS,
 769                 &spr_read_generic, &spr_write_generic,
 770                 0x00000000);
 771}
 772
 773/* SPR common to all non-embedded PowerPC, including 601 */
 774static void gen_spr_ne_601(CPUPPCState *env)
 775{
 776    /* Exception processing */
 777    spr_register_kvm(env, SPR_DSISR, "DSISR",
 778                     SPR_NOACCESS, SPR_NOACCESS,
 779                     &spr_read_generic, &spr_write_generic,
 780                     KVM_REG_PPC_DSISR, 0x00000000);
 781    spr_register_kvm(env, SPR_DAR, "DAR",
 782                     SPR_NOACCESS, SPR_NOACCESS,
 783                     &spr_read_generic, &spr_write_generic,
 784                     KVM_REG_PPC_DAR, 0x00000000);
 785    /* Timer */
 786    spr_register(env, SPR_DECR, "DECR",
 787                 SPR_NOACCESS, SPR_NOACCESS,
 788                 &spr_read_decr, &spr_write_decr,
 789                 0x00000000);
 790}
 791
 792/* Storage Description Register 1 */
 793static void gen_spr_sdr1(CPUPPCState *env)
 794{
 795#ifndef CONFIG_USER_ONLY
 796    if (env->has_hv_mode) {
 797        /*
 798         * SDR1 is a hypervisor resource on CPUs which have a
 799         * hypervisor mode
 800         */
 801        spr_register_hv(env, SPR_SDR1, "SDR1",
 802                        SPR_NOACCESS, SPR_NOACCESS,
 803                        SPR_NOACCESS, SPR_NOACCESS,
 804                        &spr_read_generic, &spr_write_sdr1,
 805                        0x00000000);
 806    } else {
 807        spr_register(env, SPR_SDR1, "SDR1",
 808                     SPR_NOACCESS, SPR_NOACCESS,
 809                     &spr_read_generic, &spr_write_sdr1,
 810                     0x00000000);
 811    }
 812#endif
 813}
 814
 815/* BATs 0-3 */
 816static void gen_low_BATs(CPUPPCState *env)
 817{
 818#if !defined(CONFIG_USER_ONLY)
 819    spr_register(env, SPR_IBAT0U, "IBAT0U",
 820                 SPR_NOACCESS, SPR_NOACCESS,
 821                 &spr_read_ibat, &spr_write_ibatu,
 822                 0x00000000);
 823    spr_register(env, SPR_IBAT0L, "IBAT0L",
 824                 SPR_NOACCESS, SPR_NOACCESS,
 825                 &spr_read_ibat, &spr_write_ibatl,
 826                 0x00000000);
 827    spr_register(env, SPR_IBAT1U, "IBAT1U",
 828                 SPR_NOACCESS, SPR_NOACCESS,
 829                 &spr_read_ibat, &spr_write_ibatu,
 830                 0x00000000);
 831    spr_register(env, SPR_IBAT1L, "IBAT1L",
 832                 SPR_NOACCESS, SPR_NOACCESS,
 833                 &spr_read_ibat, &spr_write_ibatl,
 834                 0x00000000);
 835    spr_register(env, SPR_IBAT2U, "IBAT2U",
 836                 SPR_NOACCESS, SPR_NOACCESS,
 837                 &spr_read_ibat, &spr_write_ibatu,
 838                 0x00000000);
 839    spr_register(env, SPR_IBAT2L, "IBAT2L",
 840                 SPR_NOACCESS, SPR_NOACCESS,
 841                 &spr_read_ibat, &spr_write_ibatl,
 842                 0x00000000);
 843    spr_register(env, SPR_IBAT3U, "IBAT3U",
 844                 SPR_NOACCESS, SPR_NOACCESS,
 845                 &spr_read_ibat, &spr_write_ibatu,
 846                 0x00000000);
 847    spr_register(env, SPR_IBAT3L, "IBAT3L",
 848                 SPR_NOACCESS, SPR_NOACCESS,
 849                 &spr_read_ibat, &spr_write_ibatl,
 850                 0x00000000);
 851    spr_register(env, SPR_DBAT0U, "DBAT0U",
 852                 SPR_NOACCESS, SPR_NOACCESS,
 853                 &spr_read_dbat, &spr_write_dbatu,
 854                 0x00000000);
 855    spr_register(env, SPR_DBAT0L, "DBAT0L",
 856                 SPR_NOACCESS, SPR_NOACCESS,
 857                 &spr_read_dbat, &spr_write_dbatl,
 858                 0x00000000);
 859    spr_register(env, SPR_DBAT1U, "DBAT1U",
 860                 SPR_NOACCESS, SPR_NOACCESS,
 861                 &spr_read_dbat, &spr_write_dbatu,
 862                 0x00000000);
 863    spr_register(env, SPR_DBAT1L, "DBAT1L",
 864                 SPR_NOACCESS, SPR_NOACCESS,
 865                 &spr_read_dbat, &spr_write_dbatl,
 866                 0x00000000);
 867    spr_register(env, SPR_DBAT2U, "DBAT2U",
 868                 SPR_NOACCESS, SPR_NOACCESS,
 869                 &spr_read_dbat, &spr_write_dbatu,
 870                 0x00000000);
 871    spr_register(env, SPR_DBAT2L, "DBAT2L",
 872                 SPR_NOACCESS, SPR_NOACCESS,
 873                 &spr_read_dbat, &spr_write_dbatl,
 874                 0x00000000);
 875    spr_register(env, SPR_DBAT3U, "DBAT3U",
 876                 SPR_NOACCESS, SPR_NOACCESS,
 877                 &spr_read_dbat, &spr_write_dbatu,
 878                 0x00000000);
 879    spr_register(env, SPR_DBAT3L, "DBAT3L",
 880                 SPR_NOACCESS, SPR_NOACCESS,
 881                 &spr_read_dbat, &spr_write_dbatl,
 882                 0x00000000);
 883    env->nb_BATs += 4;
 884#endif
 885}
 886
 887/* BATs 4-7 */
 888static void gen_high_BATs(CPUPPCState *env)
 889{
 890#if !defined(CONFIG_USER_ONLY)
 891    spr_register(env, SPR_IBAT4U, "IBAT4U",
 892                 SPR_NOACCESS, SPR_NOACCESS,
 893                 &spr_read_ibat_h, &spr_write_ibatu_h,
 894                 0x00000000);
 895    spr_register(env, SPR_IBAT4L, "IBAT4L",
 896                 SPR_NOACCESS, SPR_NOACCESS,
 897                 &spr_read_ibat_h, &spr_write_ibatl_h,
 898                 0x00000000);
 899    spr_register(env, SPR_IBAT5U, "IBAT5U",
 900                 SPR_NOACCESS, SPR_NOACCESS,
 901                 &spr_read_ibat_h, &spr_write_ibatu_h,
 902                 0x00000000);
 903    spr_register(env, SPR_IBAT5L, "IBAT5L",
 904                 SPR_NOACCESS, SPR_NOACCESS,
 905                 &spr_read_ibat_h, &spr_write_ibatl_h,
 906                 0x00000000);
 907    spr_register(env, SPR_IBAT6U, "IBAT6U",
 908                 SPR_NOACCESS, SPR_NOACCESS,
 909                 &spr_read_ibat_h, &spr_write_ibatu_h,
 910                 0x00000000);
 911    spr_register(env, SPR_IBAT6L, "IBAT6L",
 912                 SPR_NOACCESS, SPR_NOACCESS,
 913                 &spr_read_ibat_h, &spr_write_ibatl_h,
 914                 0x00000000);
 915    spr_register(env, SPR_IBAT7U, "IBAT7U",
 916                 SPR_NOACCESS, SPR_NOACCESS,
 917                 &spr_read_ibat_h, &spr_write_ibatu_h,
 918                 0x00000000);
 919    spr_register(env, SPR_IBAT7L, "IBAT7L",
 920                 SPR_NOACCESS, SPR_NOACCESS,
 921                 &spr_read_ibat_h, &spr_write_ibatl_h,
 922                 0x00000000);
 923    spr_register(env, SPR_DBAT4U, "DBAT4U",
 924                 SPR_NOACCESS, SPR_NOACCESS,
 925                 &spr_read_dbat_h, &spr_write_dbatu_h,
 926                 0x00000000);
 927    spr_register(env, SPR_DBAT4L, "DBAT4L",
 928                 SPR_NOACCESS, SPR_NOACCESS,
 929                 &spr_read_dbat_h, &spr_write_dbatl_h,
 930                 0x00000000);
 931    spr_register(env, SPR_DBAT5U, "DBAT5U",
 932                 SPR_NOACCESS, SPR_NOACCESS,
 933                 &spr_read_dbat_h, &spr_write_dbatu_h,
 934                 0x00000000);
 935    spr_register(env, SPR_DBAT5L, "DBAT5L",
 936                 SPR_NOACCESS, SPR_NOACCESS,
 937                 &spr_read_dbat_h, &spr_write_dbatl_h,
 938                 0x00000000);
 939    spr_register(env, SPR_DBAT6U, "DBAT6U",
 940                 SPR_NOACCESS, SPR_NOACCESS,
 941                 &spr_read_dbat_h, &spr_write_dbatu_h,
 942                 0x00000000);
 943    spr_register(env, SPR_DBAT6L, "DBAT6L",
 944                 SPR_NOACCESS, SPR_NOACCESS,
 945                 &spr_read_dbat_h, &spr_write_dbatl_h,
 946                 0x00000000);
 947    spr_register(env, SPR_DBAT7U, "DBAT7U",
 948                 SPR_NOACCESS, SPR_NOACCESS,
 949                 &spr_read_dbat_h, &spr_write_dbatu_h,
 950                 0x00000000);
 951    spr_register(env, SPR_DBAT7L, "DBAT7L",
 952                 SPR_NOACCESS, SPR_NOACCESS,
 953                 &spr_read_dbat_h, &spr_write_dbatl_h,
 954                 0x00000000);
 955    env->nb_BATs += 4;
 956#endif
 957}
 958
 959/* Generic PowerPC time base */
 960static void gen_tbl(CPUPPCState *env)
 961{
 962    spr_register(env, SPR_VTBL,  "TBL",
 963                 &spr_read_tbl, SPR_NOACCESS,
 964                 &spr_read_tbl, SPR_NOACCESS,
 965                 0x00000000);
 966    spr_register(env, SPR_TBL,   "TBL",
 967                 &spr_read_tbl, SPR_NOACCESS,
 968                 &spr_read_tbl, &spr_write_tbl,
 969                 0x00000000);
 970    spr_register(env, SPR_VTBU,  "TBU",
 971                 &spr_read_tbu, SPR_NOACCESS,
 972                 &spr_read_tbu, SPR_NOACCESS,
 973                 0x00000000);
 974    spr_register(env, SPR_TBU,   "TBU",
 975                 &spr_read_tbu, SPR_NOACCESS,
 976                 &spr_read_tbu, &spr_write_tbu,
 977                 0x00000000);
 978}
 979
 980/* Softare table search registers */
 981static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 982{
 983#if !defined(CONFIG_USER_ONLY)
 984    env->nb_tlb = nb_tlbs;
 985    env->nb_ways = nb_ways;
 986    env->id_tlbs = 1;
 987    env->tlb_type = TLB_6XX;
 988    spr_register(env, SPR_DMISS, "DMISS",
 989                 SPR_NOACCESS, SPR_NOACCESS,
 990                 &spr_read_generic, SPR_NOACCESS,
 991                 0x00000000);
 992    spr_register(env, SPR_DCMP, "DCMP",
 993                 SPR_NOACCESS, SPR_NOACCESS,
 994                 &spr_read_generic, SPR_NOACCESS,
 995                 0x00000000);
 996    spr_register(env, SPR_HASH1, "HASH1",
 997                 SPR_NOACCESS, SPR_NOACCESS,
 998                 &spr_read_generic, SPR_NOACCESS,
 999                 0x00000000);
1000    spr_register(env, SPR_HASH2, "HASH2",
1001                 SPR_NOACCESS, SPR_NOACCESS,
1002                 &spr_read_generic, SPR_NOACCESS,
1003                 0x00000000);
1004    spr_register(env, SPR_IMISS, "IMISS",
1005                 SPR_NOACCESS, SPR_NOACCESS,
1006                 &spr_read_generic, SPR_NOACCESS,
1007                 0x00000000);
1008    spr_register(env, SPR_ICMP, "ICMP",
1009                 SPR_NOACCESS, SPR_NOACCESS,
1010                 &spr_read_generic, SPR_NOACCESS,
1011                 0x00000000);
1012    spr_register(env, SPR_RPA, "RPA",
1013                 SPR_NOACCESS, SPR_NOACCESS,
1014                 &spr_read_generic, &spr_write_generic,
1015                 0x00000000);
1016#endif
1017}
1018
1019/* SPR common to MPC755 and G2 */
1020static void gen_spr_G2_755(CPUPPCState *env)
1021{
1022    /* SGPRs */
1023    spr_register(env, SPR_SPRG4, "SPRG4",
1024                 SPR_NOACCESS, SPR_NOACCESS,
1025                 &spr_read_generic, &spr_write_generic,
1026                 0x00000000);
1027    spr_register(env, SPR_SPRG5, "SPRG5",
1028                 SPR_NOACCESS, SPR_NOACCESS,
1029                 &spr_read_generic, &spr_write_generic,
1030                 0x00000000);
1031    spr_register(env, SPR_SPRG6, "SPRG6",
1032                 SPR_NOACCESS, SPR_NOACCESS,
1033                 &spr_read_generic, &spr_write_generic,
1034                 0x00000000);
1035    spr_register(env, SPR_SPRG7, "SPRG7",
1036                 SPR_NOACCESS, SPR_NOACCESS,
1037                 &spr_read_generic, &spr_write_generic,
1038                 0x00000000);
1039}
1040
1041/* SPR common to all 7xx PowerPC implementations */
1042static void gen_spr_7xx(CPUPPCState *env)
1043{
1044    /* Breakpoints */
1045    /* XXX : not implemented */
1046    spr_register_kvm(env, SPR_DABR, "DABR",
1047                     SPR_NOACCESS, SPR_NOACCESS,
1048                     &spr_read_generic, &spr_write_generic,
1049                     KVM_REG_PPC_DABR, 0x00000000);
1050    /* XXX : not implemented */
1051    spr_register(env, SPR_IABR, "IABR",
1052                 SPR_NOACCESS, SPR_NOACCESS,
1053                 &spr_read_generic, &spr_write_generic,
1054                 0x00000000);
1055    /* Cache management */
1056    /* XXX : not implemented */
1057    spr_register(env, SPR_ICTC, "ICTC",
1058                 SPR_NOACCESS, SPR_NOACCESS,
1059                 &spr_read_generic, &spr_write_generic,
1060                 0x00000000);
1061    /* Performance monitors */
1062    /* XXX : not implemented */
1063    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1064                 SPR_NOACCESS, SPR_NOACCESS,
1065                 &spr_read_generic, &spr_write_generic,
1066                 0x00000000);
1067    /* XXX : not implemented */
1068    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1069                 SPR_NOACCESS, SPR_NOACCESS,
1070                 &spr_read_generic, &spr_write_generic,
1071                 0x00000000);
1072    /* XXX : not implemented */
1073    spr_register(env, SPR_7XX_PMC1, "PMC1",
1074                 SPR_NOACCESS, SPR_NOACCESS,
1075                 &spr_read_generic, &spr_write_generic,
1076                 0x00000000);
1077    /* XXX : not implemented */
1078    spr_register(env, SPR_7XX_PMC2, "PMC2",
1079                 SPR_NOACCESS, SPR_NOACCESS,
1080                 &spr_read_generic, &spr_write_generic,
1081                 0x00000000);
1082    /* XXX : not implemented */
1083    spr_register(env, SPR_7XX_PMC3, "PMC3",
1084                 SPR_NOACCESS, SPR_NOACCESS,
1085                 &spr_read_generic, &spr_write_generic,
1086                 0x00000000);
1087    /* XXX : not implemented */
1088    spr_register(env, SPR_7XX_PMC4, "PMC4",
1089                 SPR_NOACCESS, SPR_NOACCESS,
1090                 &spr_read_generic, &spr_write_generic,
1091                 0x00000000);
1092    /* XXX : not implemented */
1093    spr_register(env, SPR_7XX_SIAR, "SIAR",
1094                 SPR_NOACCESS, SPR_NOACCESS,
1095                 &spr_read_generic, SPR_NOACCESS,
1096                 0x00000000);
1097    /* XXX : not implemented */
1098    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1099                 &spr_read_ureg, SPR_NOACCESS,
1100                 &spr_read_ureg, SPR_NOACCESS,
1101                 0x00000000);
1102    /* XXX : not implemented */
1103    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1104                 &spr_read_ureg, SPR_NOACCESS,
1105                 &spr_read_ureg, SPR_NOACCESS,
1106                 0x00000000);
1107    /* XXX : not implemented */
1108    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1109                 &spr_read_ureg, SPR_NOACCESS,
1110                 &spr_read_ureg, SPR_NOACCESS,
1111                 0x00000000);
1112    /* XXX : not implemented */
1113    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1114                 &spr_read_ureg, SPR_NOACCESS,
1115                 &spr_read_ureg, SPR_NOACCESS,
1116                 0x00000000);
1117    /* XXX : not implemented */
1118    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1119                 &spr_read_ureg, SPR_NOACCESS,
1120                 &spr_read_ureg, SPR_NOACCESS,
1121                 0x00000000);
1122    /* XXX : not implemented */
1123    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1124                 &spr_read_ureg, SPR_NOACCESS,
1125                 &spr_read_ureg, SPR_NOACCESS,
1126                 0x00000000);
1127    /* XXX : not implemented */
1128    spr_register(env, SPR_7XX_USIAR, "USIAR",
1129                 &spr_read_ureg, SPR_NOACCESS,
1130                 &spr_read_ureg, SPR_NOACCESS,
1131                 0x00000000);
1132    /* External access control */
1133    /* XXX : not implemented */
1134    spr_register(env, SPR_EAR, "EAR",
1135                 SPR_NOACCESS, SPR_NOACCESS,
1136                 &spr_read_generic, &spr_write_generic,
1137                 0x00000000);
1138}
1139
1140#ifdef TARGET_PPC64
1141#ifndef CONFIG_USER_ONLY
1142static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1143{
1144    TCGv t0 = tcg_temp_new();
1145    TCGv t1 = tcg_temp_new();
1146    TCGv t2 = tcg_temp_new();
1147
1148    /*
1149     * Note, the HV=1 PR=0 case is handled earlier by simply using
1150     * spr_write_generic for HV mode in the SPR table
1151     */
1152
1153    /* Build insertion mask into t1 based on context */
1154    if (ctx->pr) {
1155        gen_load_spr(t1, SPR_UAMOR);
1156    } else {
1157        gen_load_spr(t1, SPR_AMOR);
1158    }
1159
1160    /* Mask new bits into t2 */
1161    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1162
1163    /* Load AMR and clear new bits in t0 */
1164    gen_load_spr(t0, SPR_AMR);
1165    tcg_gen_andc_tl(t0, t0, t1);
1166
1167    /* Or'in new bits and write it out */
1168    tcg_gen_or_tl(t0, t0, t2);
1169    gen_store_spr(SPR_AMR, t0);
1170    spr_store_dump_spr(SPR_AMR);
1171
1172    tcg_temp_free(t0);
1173    tcg_temp_free(t1);
1174    tcg_temp_free(t2);
1175}
1176
1177static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1178{
1179    TCGv t0 = tcg_temp_new();
1180    TCGv t1 = tcg_temp_new();
1181    TCGv t2 = tcg_temp_new();
1182
1183    /*
1184     * Note, the HV=1 case is handled earlier by simply using
1185     * spr_write_generic for HV mode in the SPR table
1186     */
1187
1188    /* Build insertion mask into t1 based on context */
1189    gen_load_spr(t1, SPR_AMOR);
1190
1191    /* Mask new bits into t2 */
1192    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1193
1194    /* Load AMR and clear new bits in t0 */
1195    gen_load_spr(t0, SPR_UAMOR);
1196    tcg_gen_andc_tl(t0, t0, t1);
1197
1198    /* Or'in new bits and write it out */
1199    tcg_gen_or_tl(t0, t0, t2);
1200    gen_store_spr(SPR_UAMOR, t0);
1201    spr_store_dump_spr(SPR_UAMOR);
1202
1203    tcg_temp_free(t0);
1204    tcg_temp_free(t1);
1205    tcg_temp_free(t2);
1206}
1207
1208static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1209{
1210    TCGv t0 = tcg_temp_new();
1211    TCGv t1 = tcg_temp_new();
1212    TCGv t2 = tcg_temp_new();
1213
1214    /*
1215     * Note, the HV=1 case is handled earlier by simply using
1216     * spr_write_generic for HV mode in the SPR table
1217     */
1218
1219    /* Build insertion mask into t1 based on context */
1220    gen_load_spr(t1, SPR_AMOR);
1221
1222    /* Mask new bits into t2 */
1223    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1224
1225    /* Load AMR and clear new bits in t0 */
1226    gen_load_spr(t0, SPR_IAMR);
1227    tcg_gen_andc_tl(t0, t0, t1);
1228
1229    /* Or'in new bits and write it out */
1230    tcg_gen_or_tl(t0, t0, t2);
1231    gen_store_spr(SPR_IAMR, t0);
1232    spr_store_dump_spr(SPR_IAMR);
1233
1234    tcg_temp_free(t0);
1235    tcg_temp_free(t1);
1236    tcg_temp_free(t2);
1237}
1238#endif /* CONFIG_USER_ONLY */
1239
1240static void gen_spr_amr(CPUPPCState *env)
1241{
1242#ifndef CONFIG_USER_ONLY
1243    /*
1244     * Virtual Page Class Key protection
1245     *
1246     * The AMR is accessible either via SPR 13 or SPR 29.  13 is
1247     * userspace accessible, 29 is privileged.  So we only need to set
1248     * the kvm ONE_REG id on one of them, we use 29
1249     */
1250    spr_register(env, SPR_UAMR, "UAMR",
1251                 &spr_read_generic, &spr_write_amr,
1252                 &spr_read_generic, &spr_write_amr,
1253                 0);
1254    spr_register_kvm_hv(env, SPR_AMR, "AMR",
1255                     SPR_NOACCESS, SPR_NOACCESS,
1256                     &spr_read_generic, &spr_write_amr,
1257                     &spr_read_generic, &spr_write_generic,
1258                     KVM_REG_PPC_AMR, 0);
1259    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1260                     SPR_NOACCESS, SPR_NOACCESS,
1261                     &spr_read_generic, &spr_write_uamor,
1262                     &spr_read_generic, &spr_write_generic,
1263                     KVM_REG_PPC_UAMOR, 0);
1264    spr_register_hv(env, SPR_AMOR, "AMOR",
1265                    SPR_NOACCESS, SPR_NOACCESS,
1266                    SPR_NOACCESS, SPR_NOACCESS,
1267                    &spr_read_generic, &spr_write_generic,
1268                    0);
1269#endif /* !CONFIG_USER_ONLY */
1270}
1271
1272static void gen_spr_iamr(CPUPPCState *env)
1273{
1274#ifndef CONFIG_USER_ONLY
1275    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1276                        SPR_NOACCESS, SPR_NOACCESS,
1277                        &spr_read_generic, &spr_write_iamr,
1278                        &spr_read_generic, &spr_write_generic,
1279                        KVM_REG_PPC_IAMR, 0);
1280#endif /* !CONFIG_USER_ONLY */
1281}
1282#endif /* TARGET_PPC64 */
1283
1284#ifndef CONFIG_USER_ONLY
1285static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1286{
1287    gen_helper_fixup_thrm(cpu_env);
1288    gen_load_spr(cpu_gpr[gprn], sprn);
1289    spr_load_dump_spr(sprn);
1290}
1291#endif /* !CONFIG_USER_ONLY */
1292
1293static void gen_spr_thrm(CPUPPCState *env)
1294{
1295    /* Thermal management */
1296    /* XXX : not implemented */
1297    spr_register(env, SPR_THRM1, "THRM1",
1298                 SPR_NOACCESS, SPR_NOACCESS,
1299                 &spr_read_thrm, &spr_write_generic,
1300                 0x00000000);
1301    /* XXX : not implemented */
1302    spr_register(env, SPR_THRM2, "THRM2",
1303                 SPR_NOACCESS, SPR_NOACCESS,
1304                 &spr_read_thrm, &spr_write_generic,
1305                 0x00000000);
1306    /* XXX : not implemented */
1307    spr_register(env, SPR_THRM3, "THRM3",
1308                 SPR_NOACCESS, SPR_NOACCESS,
1309                 &spr_read_thrm, &spr_write_generic,
1310                 0x00000000);
1311}
1312
1313/* SPR specific to PowerPC 604 implementation */
1314static void gen_spr_604(CPUPPCState *env)
1315{
1316    /* Processor identification */
1317    spr_register(env, SPR_PIR, "PIR",
1318                 SPR_NOACCESS, SPR_NOACCESS,
1319                 &spr_read_generic, &spr_write_pir,
1320                 0x00000000);
1321    /* Breakpoints */
1322    /* XXX : not implemented */
1323    spr_register(env, SPR_IABR, "IABR",
1324                 SPR_NOACCESS, SPR_NOACCESS,
1325                 &spr_read_generic, &spr_write_generic,
1326                 0x00000000);
1327    /* XXX : not implemented */
1328    spr_register_kvm(env, SPR_DABR, "DABR",
1329                     SPR_NOACCESS, SPR_NOACCESS,
1330                     &spr_read_generic, &spr_write_generic,
1331                     KVM_REG_PPC_DABR, 0x00000000);
1332    /* Performance counters */
1333    /* XXX : not implemented */
1334    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1335                 SPR_NOACCESS, SPR_NOACCESS,
1336                 &spr_read_generic, &spr_write_generic,
1337                 0x00000000);
1338    /* XXX : not implemented */
1339    spr_register(env, SPR_7XX_PMC1, "PMC1",
1340                 SPR_NOACCESS, SPR_NOACCESS,
1341                 &spr_read_generic, &spr_write_generic,
1342                 0x00000000);
1343    /* XXX : not implemented */
1344    spr_register(env, SPR_7XX_PMC2, "PMC2",
1345                 SPR_NOACCESS, SPR_NOACCESS,
1346                 &spr_read_generic, &spr_write_generic,
1347                 0x00000000);
1348    /* XXX : not implemented */
1349    spr_register(env, SPR_7XX_SIAR, "SIAR",
1350                 SPR_NOACCESS, SPR_NOACCESS,
1351                 &spr_read_generic, SPR_NOACCESS,
1352                 0x00000000);
1353    /* XXX : not implemented */
1354    spr_register(env, SPR_SDA, "SDA",
1355                 SPR_NOACCESS, SPR_NOACCESS,
1356                 &spr_read_generic, SPR_NOACCESS,
1357                 0x00000000);
1358    /* External access control */
1359    /* XXX : not implemented */
1360    spr_register(env, SPR_EAR, "EAR",
1361                 SPR_NOACCESS, SPR_NOACCESS,
1362                 &spr_read_generic, &spr_write_generic,
1363                 0x00000000);
1364}
1365
1366/* SPR specific to PowerPC 603 implementation */
1367static void gen_spr_603(CPUPPCState *env)
1368{
1369    /* External access control */
1370    /* XXX : not implemented */
1371    spr_register(env, SPR_EAR, "EAR",
1372                 SPR_NOACCESS, SPR_NOACCESS,
1373                 &spr_read_generic, &spr_write_generic,
1374                 0x00000000);
1375    /* Breakpoints */
1376    /* XXX : not implemented */
1377    spr_register(env, SPR_IABR, "IABR",
1378                 SPR_NOACCESS, SPR_NOACCESS,
1379                 &spr_read_generic, &spr_write_generic,
1380                 0x00000000);
1381
1382}
1383
1384/* SPR specific to PowerPC G2 implementation */
1385static void gen_spr_G2(CPUPPCState *env)
1386{
1387    /* Memory base address */
1388    /* MBAR */
1389    /* XXX : not implemented */
1390    spr_register(env, SPR_MBAR, "MBAR",
1391                 SPR_NOACCESS, SPR_NOACCESS,
1392                 &spr_read_generic, &spr_write_generic,
1393                 0x00000000);
1394    /* Exception processing */
1395    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1396                 SPR_NOACCESS, SPR_NOACCESS,
1397                 &spr_read_generic, &spr_write_generic,
1398                 0x00000000);
1399    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1400                 SPR_NOACCESS, SPR_NOACCESS,
1401                 &spr_read_generic, &spr_write_generic,
1402                 0x00000000);
1403    /* Breakpoints */
1404    /* XXX : not implemented */
1405    spr_register(env, SPR_DABR, "DABR",
1406                 SPR_NOACCESS, SPR_NOACCESS,
1407                 &spr_read_generic, &spr_write_generic,
1408                 0x00000000);
1409    /* XXX : not implemented */
1410    spr_register(env, SPR_DABR2, "DABR2",
1411                 SPR_NOACCESS, SPR_NOACCESS,
1412                 &spr_read_generic, &spr_write_generic,
1413                 0x00000000);
1414    /* XXX : not implemented */
1415    spr_register(env, SPR_IABR, "IABR",
1416                 SPR_NOACCESS, SPR_NOACCESS,
1417                 &spr_read_generic, &spr_write_generic,
1418                 0x00000000);
1419    /* XXX : not implemented */
1420    spr_register(env, SPR_IABR2, "IABR2",
1421                 SPR_NOACCESS, SPR_NOACCESS,
1422                 &spr_read_generic, &spr_write_generic,
1423                 0x00000000);
1424    /* XXX : not implemented */
1425    spr_register(env, SPR_IBCR, "IBCR",
1426                 SPR_NOACCESS, SPR_NOACCESS,
1427                 &spr_read_generic, &spr_write_generic,
1428                 0x00000000);
1429    /* XXX : not implemented */
1430    spr_register(env, SPR_DBCR, "DBCR",
1431                 SPR_NOACCESS, SPR_NOACCESS,
1432                 &spr_read_generic, &spr_write_generic,
1433                 0x00000000);
1434}
1435
1436/* SPR specific to PowerPC 602 implementation */
1437static void gen_spr_602(CPUPPCState *env)
1438{
1439    /* ESA registers */
1440    /* XXX : not implemented */
1441    spr_register(env, SPR_SER, "SER",
1442                 SPR_NOACCESS, SPR_NOACCESS,
1443                 &spr_read_generic, &spr_write_generic,
1444                 0x00000000);
1445    /* XXX : not implemented */
1446    spr_register(env, SPR_SEBR, "SEBR",
1447                 SPR_NOACCESS, SPR_NOACCESS,
1448                 &spr_read_generic, &spr_write_generic,
1449                 0x00000000);
1450    /* XXX : not implemented */
1451    spr_register(env, SPR_ESASRR, "ESASRR",
1452                 SPR_NOACCESS, SPR_NOACCESS,
1453                 &spr_read_generic, &spr_write_generic,
1454                 0x00000000);
1455    /* Floating point status */
1456    /* XXX : not implemented */
1457    spr_register(env, SPR_SP, "SP",
1458                 SPR_NOACCESS, SPR_NOACCESS,
1459                 &spr_read_generic, &spr_write_generic,
1460                 0x00000000);
1461    /* XXX : not implemented */
1462    spr_register(env, SPR_LT, "LT",
1463                 SPR_NOACCESS, SPR_NOACCESS,
1464                 &spr_read_generic, &spr_write_generic,
1465                 0x00000000);
1466    /* Watchdog timer */
1467    /* XXX : not implemented */
1468    spr_register(env, SPR_TCR, "TCR",
1469                 SPR_NOACCESS, SPR_NOACCESS,
1470                 &spr_read_generic, &spr_write_generic,
1471                 0x00000000);
1472    /* Interrupt base */
1473    spr_register(env, SPR_IBR, "IBR",
1474                 SPR_NOACCESS, SPR_NOACCESS,
1475                 &spr_read_generic, &spr_write_generic,
1476                 0x00000000);
1477    /* XXX : not implemented */
1478    spr_register(env, SPR_IABR, "IABR",
1479                 SPR_NOACCESS, SPR_NOACCESS,
1480                 &spr_read_generic, &spr_write_generic,
1481                 0x00000000);
1482}
1483
1484/* SPR specific to PowerPC 601 implementation */
1485static void gen_spr_601(CPUPPCState *env)
1486{
1487    /* Multiplication/division register */
1488    /* MQ */
1489    spr_register(env, SPR_MQ, "MQ",
1490                 &spr_read_generic, &spr_write_generic,
1491                 &spr_read_generic, &spr_write_generic,
1492                 0x00000000);
1493    /* RTC registers */
1494    spr_register(env, SPR_601_RTCU, "RTCU",
1495                 SPR_NOACCESS, SPR_NOACCESS,
1496                 SPR_NOACCESS, &spr_write_601_rtcu,
1497                 0x00000000);
1498    spr_register(env, SPR_601_VRTCU, "RTCU",
1499                 &spr_read_601_rtcu, SPR_NOACCESS,
1500                 &spr_read_601_rtcu, SPR_NOACCESS,
1501                 0x00000000);
1502    spr_register(env, SPR_601_RTCL, "RTCL",
1503                 SPR_NOACCESS, SPR_NOACCESS,
1504                 SPR_NOACCESS, &spr_write_601_rtcl,
1505                 0x00000000);
1506    spr_register(env, SPR_601_VRTCL, "RTCL",
1507                 &spr_read_601_rtcl, SPR_NOACCESS,
1508                 &spr_read_601_rtcl, SPR_NOACCESS,
1509                 0x00000000);
1510    /* Timer */
1511#if 0 /* ? */
1512    spr_register(env, SPR_601_UDECR, "UDECR",
1513                 &spr_read_decr, SPR_NOACCESS,
1514                 &spr_read_decr, SPR_NOACCESS,
1515                 0x00000000);
1516#endif
1517    /* External access control */
1518    /* XXX : not implemented */
1519    spr_register(env, SPR_EAR, "EAR",
1520                 SPR_NOACCESS, SPR_NOACCESS,
1521                 &spr_read_generic, &spr_write_generic,
1522                 0x00000000);
1523    /* Memory management */
1524#if !defined(CONFIG_USER_ONLY)
1525    spr_register(env, SPR_IBAT0U, "IBAT0U",
1526                 SPR_NOACCESS, SPR_NOACCESS,
1527                 &spr_read_601_ubat, &spr_write_601_ubatu,
1528                 0x00000000);
1529    spr_register(env, SPR_IBAT0L, "IBAT0L",
1530                 SPR_NOACCESS, SPR_NOACCESS,
1531                 &spr_read_601_ubat, &spr_write_601_ubatl,
1532                 0x00000000);
1533    spr_register(env, SPR_IBAT1U, "IBAT1U",
1534                 SPR_NOACCESS, SPR_NOACCESS,
1535                 &spr_read_601_ubat, &spr_write_601_ubatu,
1536                 0x00000000);
1537    spr_register(env, SPR_IBAT1L, "IBAT1L",
1538                 SPR_NOACCESS, SPR_NOACCESS,
1539                 &spr_read_601_ubat, &spr_write_601_ubatl,
1540                 0x00000000);
1541    spr_register(env, SPR_IBAT2U, "IBAT2U",
1542                 SPR_NOACCESS, SPR_NOACCESS,
1543                 &spr_read_601_ubat, &spr_write_601_ubatu,
1544                 0x00000000);
1545    spr_register(env, SPR_IBAT2L, "IBAT2L",
1546                 SPR_NOACCESS, SPR_NOACCESS,
1547                 &spr_read_601_ubat, &spr_write_601_ubatl,
1548                 0x00000000);
1549    spr_register(env, SPR_IBAT3U, "IBAT3U",
1550                 SPR_NOACCESS, SPR_NOACCESS,
1551                 &spr_read_601_ubat, &spr_write_601_ubatu,
1552                 0x00000000);
1553    spr_register(env, SPR_IBAT3L, "IBAT3L",
1554                 SPR_NOACCESS, SPR_NOACCESS,
1555                 &spr_read_601_ubat, &spr_write_601_ubatl,
1556                 0x00000000);
1557    env->nb_BATs = 4;
1558#endif
1559}
1560
1561static void gen_spr_74xx(CPUPPCState *env)
1562{
1563    /* Processor identification */
1564    spr_register(env, SPR_PIR, "PIR",
1565                 SPR_NOACCESS, SPR_NOACCESS,
1566                 &spr_read_generic, &spr_write_pir,
1567                 0x00000000);
1568    /* XXX : not implemented */
1569    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1570                 SPR_NOACCESS, SPR_NOACCESS,
1571                 &spr_read_generic, &spr_write_generic,
1572                 0x00000000);
1573    /* XXX : not implemented */
1574    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1575                 &spr_read_ureg, SPR_NOACCESS,
1576                 &spr_read_ureg, SPR_NOACCESS,
1577                 0x00000000);
1578    /* XXX: not implemented */
1579    spr_register(env, SPR_BAMR, "BAMR",
1580                 SPR_NOACCESS, SPR_NOACCESS,
1581                 &spr_read_generic, &spr_write_generic,
1582                 0x00000000);
1583    /* XXX : not implemented */
1584    spr_register(env, SPR_MSSCR0, "MSSCR0",
1585                 SPR_NOACCESS, SPR_NOACCESS,
1586                 &spr_read_generic, &spr_write_generic,
1587                 0x00000000);
1588    /* Hardware implementation registers */
1589    /* XXX : not implemented */
1590    spr_register(env, SPR_HID0, "HID0",
1591                 SPR_NOACCESS, SPR_NOACCESS,
1592                 &spr_read_generic, &spr_write_generic,
1593                 0x00000000);
1594    /* XXX : not implemented */
1595    spr_register(env, SPR_HID1, "HID1",
1596                 SPR_NOACCESS, SPR_NOACCESS,
1597                 &spr_read_generic, &spr_write_generic,
1598                 0x00000000);
1599    /* Altivec */
1600    spr_register(env, SPR_VRSAVE, "VRSAVE",
1601                 &spr_read_generic, &spr_write_generic,
1602                 &spr_read_generic, &spr_write_generic,
1603                 0x00000000);
1604    /* XXX : not implemented */
1605    spr_register(env, SPR_L2CR, "L2CR",
1606                 SPR_NOACCESS, SPR_NOACCESS,
1607                 &spr_read_generic, spr_access_nop,
1608                 0x00000000);
1609    /* Not strictly an SPR */
1610    vscr_init(env, 0x00010000);
1611}
1612
1613static void gen_l3_ctrl(CPUPPCState *env)
1614{
1615    /* L3CR */
1616    /* XXX : not implemented */
1617    spr_register(env, SPR_L3CR, "L3CR",
1618                 SPR_NOACCESS, SPR_NOACCESS,
1619                 &spr_read_generic, &spr_write_generic,
1620                 0x00000000);
1621    /* L3ITCR0 */
1622    /* XXX : not implemented */
1623    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1624                 SPR_NOACCESS, SPR_NOACCESS,
1625                 &spr_read_generic, &spr_write_generic,
1626                 0x00000000);
1627    /* L3PM */
1628    /* XXX : not implemented */
1629    spr_register(env, SPR_L3PM, "L3PM",
1630                 SPR_NOACCESS, SPR_NOACCESS,
1631                 &spr_read_generic, &spr_write_generic,
1632                 0x00000000);
1633}
1634
1635static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1636{
1637#if !defined(CONFIG_USER_ONLY)
1638    env->nb_tlb = nb_tlbs;
1639    env->nb_ways = nb_ways;
1640    env->id_tlbs = 1;
1641    env->tlb_type = TLB_6XX;
1642    /* XXX : not implemented */
1643    spr_register(env, SPR_PTEHI, "PTEHI",
1644                 SPR_NOACCESS, SPR_NOACCESS,
1645                 &spr_read_generic, &spr_write_generic,
1646                 0x00000000);
1647    /* XXX : not implemented */
1648    spr_register(env, SPR_PTELO, "PTELO",
1649                 SPR_NOACCESS, SPR_NOACCESS,
1650                 &spr_read_generic, &spr_write_generic,
1651                 0x00000000);
1652    /* XXX : not implemented */
1653    spr_register(env, SPR_TLBMISS, "TLBMISS",
1654                 SPR_NOACCESS, SPR_NOACCESS,
1655                 &spr_read_generic, &spr_write_generic,
1656                 0x00000000);
1657#endif
1658}
1659
1660#if !defined(CONFIG_USER_ONLY)
1661static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1662{
1663    TCGv t0 = tcg_temp_new();
1664
1665    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1666    gen_store_spr(sprn, t0);
1667    tcg_temp_free(t0);
1668}
1669
1670static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1671{
1672    TCGv t0 = tcg_temp_new();
1673
1674    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1675    gen_store_spr(sprn, t0);
1676    tcg_temp_free(t0);
1677}
1678
1679static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1680{
1681    gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1682}
1683
1684static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1685{
1686    TCGv_i32 t0 = tcg_const_i32(sprn);
1687    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1688    tcg_temp_free_i32(t0);
1689}
1690static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1691{
1692    gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1693}
1694static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1695{
1696    gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1697}
1698
1699#endif
1700
1701static void gen_spr_usprg3(CPUPPCState *env)
1702{
1703    spr_register(env, SPR_USPRG3, "USPRG3",
1704                 &spr_read_ureg, SPR_NOACCESS,
1705                 &spr_read_ureg, SPR_NOACCESS,
1706                 0x00000000);
1707}
1708
1709static void gen_spr_usprgh(CPUPPCState *env)
1710{
1711    spr_register(env, SPR_USPRG4, "USPRG4",
1712                 &spr_read_ureg, SPR_NOACCESS,
1713                 &spr_read_ureg, SPR_NOACCESS,
1714                 0x00000000);
1715    spr_register(env, SPR_USPRG5, "USPRG5",
1716                 &spr_read_ureg, SPR_NOACCESS,
1717                 &spr_read_ureg, SPR_NOACCESS,
1718                 0x00000000);
1719    spr_register(env, SPR_USPRG6, "USPRG6",
1720                 &spr_read_ureg, SPR_NOACCESS,
1721                 &spr_read_ureg, SPR_NOACCESS,
1722                 0x00000000);
1723    spr_register(env, SPR_USPRG7, "USPRG7",
1724                 &spr_read_ureg, SPR_NOACCESS,
1725                 &spr_read_ureg, SPR_NOACCESS,
1726                 0x00000000);
1727}
1728
1729/* PowerPC BookE SPR */
1730static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1731{
1732    const char *ivor_names[64] = {
1733        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1734        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1735        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1736        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1737        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1738        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1739        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1740        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1741        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1742        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1743        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1744        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1745        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1746        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1747        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1748        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1749    };
1750#define SPR_BOOKE_IVORxx (-1)
1751    int ivor_sprn[64] = {
1752        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1753        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1754        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1755        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1756        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1757        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1758        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1759        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1760        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1761        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1762        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1763        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1764        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1765        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1766        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1767        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1768    };
1769    int i;
1770
1771    /* Interrupt processing */
1772    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1773                 SPR_NOACCESS, SPR_NOACCESS,
1774                 &spr_read_generic, &spr_write_generic,
1775                 0x00000000);
1776    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1777                 SPR_NOACCESS, SPR_NOACCESS,
1778                 &spr_read_generic, &spr_write_generic,
1779                 0x00000000);
1780    /* Debug */
1781    /* XXX : not implemented */
1782    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1783                 SPR_NOACCESS, SPR_NOACCESS,
1784                 &spr_read_generic, &spr_write_generic,
1785                 0x00000000);
1786    /* XXX : not implemented */
1787    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1788                 SPR_NOACCESS, SPR_NOACCESS,
1789                 &spr_read_generic, &spr_write_generic,
1790                 0x00000000);
1791    /* XXX : not implemented */
1792    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1793                 SPR_NOACCESS, SPR_NOACCESS,
1794                 &spr_read_generic, &spr_write_generic,
1795                 0x00000000);
1796    /* XXX : not implemented */
1797    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1798                 SPR_NOACCESS, SPR_NOACCESS,
1799                 &spr_read_generic, &spr_write_generic,
1800                 0x00000000);
1801    /* XXX : not implemented */
1802    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1803                 SPR_NOACCESS, SPR_NOACCESS,
1804                 &spr_read_generic, &spr_write_40x_dbcr0,
1805                 0x00000000);
1806    /* XXX : not implemented */
1807    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1808                 SPR_NOACCESS, SPR_NOACCESS,
1809                 &spr_read_generic, &spr_write_generic,
1810                 0x00000000);
1811    /* XXX : not implemented */
1812    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1813                 SPR_NOACCESS, SPR_NOACCESS,
1814                 &spr_read_generic, &spr_write_generic,
1815                 0x00000000);
1816    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1817                 SPR_NOACCESS, SPR_NOACCESS,
1818                 &spr_read_generic, &spr_write_generic,
1819                 0x00000000);
1820    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1821                 SPR_NOACCESS, SPR_NOACCESS,
1822                 &spr_read_generic, &spr_write_generic,
1823                 0x00000000);
1824    /* XXX : not implemented */
1825    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1826                 SPR_NOACCESS, SPR_NOACCESS,
1827                 &spr_read_generic, &spr_write_clear,
1828                 0x00000000);
1829    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1830                 SPR_NOACCESS, SPR_NOACCESS,
1831                 &spr_read_generic, &spr_write_generic,
1832                 0x00000000);
1833    spr_register(env, SPR_BOOKE_ESR, "ESR",
1834                 SPR_NOACCESS, SPR_NOACCESS,
1835                 &spr_read_generic, &spr_write_generic,
1836                 0x00000000);
1837    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1838                 SPR_NOACCESS, SPR_NOACCESS,
1839                 &spr_read_generic, &spr_write_excp_prefix,
1840                 0x00000000);
1841    /* Exception vectors */
1842    for (i = 0; i < 64; i++) {
1843        if (ivor_mask & (1ULL << i)) {
1844            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1845                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1846                exit(1);
1847            }
1848            spr_register(env, ivor_sprn[i], ivor_names[i],
1849                         SPR_NOACCESS, SPR_NOACCESS,
1850                         &spr_read_generic, &spr_write_excp_vector,
1851                         0x00000000);
1852        }
1853    }
1854    spr_register(env, SPR_BOOKE_PID, "PID",
1855                 SPR_NOACCESS, SPR_NOACCESS,
1856                 &spr_read_generic, &spr_write_booke_pid,
1857                 0x00000000);
1858    spr_register(env, SPR_BOOKE_TCR, "TCR",
1859                 SPR_NOACCESS, SPR_NOACCESS,
1860                 &spr_read_generic, &spr_write_booke_tcr,
1861                 0x00000000);
1862    spr_register(env, SPR_BOOKE_TSR, "TSR",
1863                 SPR_NOACCESS, SPR_NOACCESS,
1864                 &spr_read_generic, &spr_write_booke_tsr,
1865                 0x00000000);
1866    /* Timer */
1867    spr_register(env, SPR_DECR, "DECR",
1868                 SPR_NOACCESS, SPR_NOACCESS,
1869                 &spr_read_decr, &spr_write_decr,
1870                 0x00000000);
1871    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1872                 SPR_NOACCESS, SPR_NOACCESS,
1873                 SPR_NOACCESS, &spr_write_generic,
1874                 0x00000000);
1875    /* SPRGs */
1876    spr_register(env, SPR_USPRG0, "USPRG0",
1877                 &spr_read_generic, &spr_write_generic,
1878                 &spr_read_generic, &spr_write_generic,
1879                 0x00000000);
1880    spr_register(env, SPR_SPRG4, "SPRG4",
1881                 SPR_NOACCESS, SPR_NOACCESS,
1882                 &spr_read_generic, &spr_write_generic,
1883                 0x00000000);
1884    spr_register(env, SPR_SPRG5, "SPRG5",
1885                 SPR_NOACCESS, SPR_NOACCESS,
1886                 &spr_read_generic, &spr_write_generic,
1887                 0x00000000);
1888    spr_register(env, SPR_SPRG6, "SPRG6",
1889                 SPR_NOACCESS, SPR_NOACCESS,
1890                 &spr_read_generic, &spr_write_generic,
1891                 0x00000000);
1892    spr_register(env, SPR_SPRG7, "SPRG7",
1893                 SPR_NOACCESS, SPR_NOACCESS,
1894                 &spr_read_generic, &spr_write_generic,
1895                 0x00000000);
1896    spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1897                 SPR_NOACCESS, SPR_NOACCESS,
1898                 &spr_read_generic, &spr_write_generic,
1899                 0x00000000);
1900    spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1901                 SPR_NOACCESS, SPR_NOACCESS,
1902                 &spr_read_generic, &spr_write_generic,
1903                 0x00000000);
1904}
1905
1906static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1907                                   uint32_t maxsize, uint32_t flags,
1908                                   uint32_t nentries)
1909{
1910    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1911           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1912           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1913           flags | nentries;
1914}
1915
1916/* BookE 2.06 storage control registers */
1917static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1918                             uint32_t *tlbncfg, uint32_t mmucfg)
1919{
1920#if !defined(CONFIG_USER_ONLY)
1921    const char *mas_names[8] = {
1922        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1923    };
1924    int mas_sprn[8] = {
1925        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1926        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1927    };
1928    int i;
1929
1930    /* TLB assist registers */
1931    /* XXX : not implemented */
1932    for (i = 0; i < 8; i++) {
1933        void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1934            &spr_write_generic32;
1935        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1936            uea_write = &spr_write_generic;
1937        }
1938        if (mas_mask & (1 << i)) {
1939            spr_register(env, mas_sprn[i], mas_names[i],
1940                         SPR_NOACCESS, SPR_NOACCESS,
1941                         &spr_read_generic, uea_write,
1942                         0x00000000);
1943        }
1944    }
1945    if (env->nb_pids > 1) {
1946        /* XXX : not implemented */
1947        spr_register(env, SPR_BOOKE_PID1, "PID1",
1948                     SPR_NOACCESS, SPR_NOACCESS,
1949                     &spr_read_generic, &spr_write_booke_pid,
1950                     0x00000000);
1951    }
1952    if (env->nb_pids > 2) {
1953        /* XXX : not implemented */
1954        spr_register(env, SPR_BOOKE_PID2, "PID2",
1955                     SPR_NOACCESS, SPR_NOACCESS,
1956                     &spr_read_generic, &spr_write_booke_pid,
1957                     0x00000000);
1958    }
1959
1960    spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1961                 SPR_NOACCESS, SPR_NOACCESS,
1962                 &spr_read_generic, &spr_write_eplc,
1963                 0x00000000);
1964    spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1965                 SPR_NOACCESS, SPR_NOACCESS,
1966                 &spr_read_generic, &spr_write_epsc,
1967                 0x00000000);
1968
1969    /* XXX : not implemented */
1970    spr_register(env, SPR_MMUCFG, "MMUCFG",
1971                 SPR_NOACCESS, SPR_NOACCESS,
1972                 &spr_read_generic, SPR_NOACCESS,
1973                 mmucfg);
1974    switch (env->nb_ways) {
1975    case 4:
1976        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1977                     SPR_NOACCESS, SPR_NOACCESS,
1978                     &spr_read_generic, SPR_NOACCESS,
1979                     tlbncfg[3]);
1980        /* Fallthru */
1981    case 3:
1982        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1983                     SPR_NOACCESS, SPR_NOACCESS,
1984                     &spr_read_generic, SPR_NOACCESS,
1985                     tlbncfg[2]);
1986        /* Fallthru */
1987    case 2:
1988        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1989                     SPR_NOACCESS, SPR_NOACCESS,
1990                     &spr_read_generic, SPR_NOACCESS,
1991                     tlbncfg[1]);
1992        /* Fallthru */
1993    case 1:
1994        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1995                     SPR_NOACCESS, SPR_NOACCESS,
1996                     &spr_read_generic, SPR_NOACCESS,
1997                     tlbncfg[0]);
1998        /* Fallthru */
1999    case 0:
2000    default:
2001        break;
2002    }
2003#endif
2004
2005    gen_spr_usprgh(env);
2006}
2007
2008/* SPR specific to PowerPC 440 implementation */
2009static void gen_spr_440(CPUPPCState *env)
2010{
2011    /* Cache control */
2012    /* XXX : not implemented */
2013    spr_register(env, SPR_440_DNV0, "DNV0",
2014                 SPR_NOACCESS, SPR_NOACCESS,
2015                 &spr_read_generic, &spr_write_generic,
2016                 0x00000000);
2017    /* XXX : not implemented */
2018    spr_register(env, SPR_440_DNV1, "DNV1",
2019                 SPR_NOACCESS, SPR_NOACCESS,
2020                 &spr_read_generic, &spr_write_generic,
2021                 0x00000000);
2022    /* XXX : not implemented */
2023    spr_register(env, SPR_440_DNV2, "DNV2",
2024                 SPR_NOACCESS, SPR_NOACCESS,
2025                 &spr_read_generic, &spr_write_generic,
2026                 0x00000000);
2027    /* XXX : not implemented */
2028    spr_register(env, SPR_440_DNV3, "DNV3",
2029                 SPR_NOACCESS, SPR_NOACCESS,
2030                 &spr_read_generic, &spr_write_generic,
2031                 0x00000000);
2032    /* XXX : not implemented */
2033    spr_register(env, SPR_440_DTV0, "DTV0",
2034                 SPR_NOACCESS, SPR_NOACCESS,
2035                 &spr_read_generic, &spr_write_generic,
2036                 0x00000000);
2037    /* XXX : not implemented */
2038    spr_register(env, SPR_440_DTV1, "DTV1",
2039                 SPR_NOACCESS, SPR_NOACCESS,
2040                 &spr_read_generic, &spr_write_generic,
2041                 0x00000000);
2042    /* XXX : not implemented */
2043    spr_register(env, SPR_440_DTV2, "DTV2",
2044                 SPR_NOACCESS, SPR_NOACCESS,
2045                 &spr_read_generic, &spr_write_generic,
2046                 0x00000000);
2047    /* XXX : not implemented */
2048    spr_register(env, SPR_440_DTV3, "DTV3",
2049                 SPR_NOACCESS, SPR_NOACCESS,
2050                 &spr_read_generic, &spr_write_generic,
2051                 0x00000000);
2052    /* XXX : not implemented */
2053    spr_register(env, SPR_440_DVLIM, "DVLIM",
2054                 SPR_NOACCESS, SPR_NOACCESS,
2055                 &spr_read_generic, &spr_write_generic,
2056                 0x00000000);
2057    /* XXX : not implemented */
2058    spr_register(env, SPR_440_INV0, "INV0",
2059                 SPR_NOACCESS, SPR_NOACCESS,
2060                 &spr_read_generic, &spr_write_generic,
2061                 0x00000000);
2062    /* XXX : not implemented */
2063    spr_register(env, SPR_440_INV1, "INV1",
2064                 SPR_NOACCESS, SPR_NOACCESS,
2065                 &spr_read_generic, &spr_write_generic,
2066                 0x00000000);
2067    /* XXX : not implemented */
2068    spr_register(env, SPR_440_INV2, "INV2",
2069                 SPR_NOACCESS, SPR_NOACCESS,
2070                 &spr_read_generic, &spr_write_generic,
2071                 0x00000000);
2072    /* XXX : not implemented */
2073    spr_register(env, SPR_440_INV3, "INV3",
2074                 SPR_NOACCESS, SPR_NOACCESS,
2075                 &spr_read_generic, &spr_write_generic,
2076                 0x00000000);
2077    /* XXX : not implemented */
2078    spr_register(env, SPR_440_ITV0, "ITV0",
2079                 SPR_NOACCESS, SPR_NOACCESS,
2080                 &spr_read_generic, &spr_write_generic,
2081                 0x00000000);
2082    /* XXX : not implemented */
2083    spr_register(env, SPR_440_ITV1, "ITV1",
2084                 SPR_NOACCESS, SPR_NOACCESS,
2085                 &spr_read_generic, &spr_write_generic,
2086                 0x00000000);
2087    /* XXX : not implemented */
2088    spr_register(env, SPR_440_ITV2, "ITV2",
2089                 SPR_NOACCESS, SPR_NOACCESS,
2090                 &spr_read_generic, &spr_write_generic,
2091                 0x00000000);
2092    /* XXX : not implemented */
2093    spr_register(env, SPR_440_ITV3, "ITV3",
2094                 SPR_NOACCESS, SPR_NOACCESS,
2095                 &spr_read_generic, &spr_write_generic,
2096                 0x00000000);
2097    /* XXX : not implemented */
2098    spr_register(env, SPR_440_IVLIM, "IVLIM",
2099                 SPR_NOACCESS, SPR_NOACCESS,
2100                 &spr_read_generic, &spr_write_generic,
2101                 0x00000000);
2102    /* Cache debug */
2103    /* XXX : not implemented */
2104    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2105                 SPR_NOACCESS, SPR_NOACCESS,
2106                 &spr_read_generic, SPR_NOACCESS,
2107                 0x00000000);
2108    /* XXX : not implemented */
2109    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2110                 SPR_NOACCESS, SPR_NOACCESS,
2111                 &spr_read_generic, SPR_NOACCESS,
2112                 0x00000000);
2113    /* XXX : not implemented */
2114    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2115                 SPR_NOACCESS, SPR_NOACCESS,
2116                 &spr_read_generic, SPR_NOACCESS,
2117                 0x00000000);
2118    /* XXX : not implemented */
2119    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2120                 SPR_NOACCESS, SPR_NOACCESS,
2121                 &spr_read_generic, SPR_NOACCESS,
2122                 0x00000000);
2123    /* XXX : not implemented */
2124    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2125                 SPR_NOACCESS, SPR_NOACCESS,
2126                 &spr_read_generic, SPR_NOACCESS,
2127                 0x00000000);
2128    /* XXX : not implemented */
2129    spr_register(env, SPR_440_DBDR, "DBDR",
2130                 SPR_NOACCESS, SPR_NOACCESS,
2131                 &spr_read_generic, &spr_write_generic,
2132                 0x00000000);
2133    /* Processor control */
2134    spr_register(env, SPR_4xx_CCR0, "CCR0",
2135                 SPR_NOACCESS, SPR_NOACCESS,
2136                 &spr_read_generic, &spr_write_generic,
2137                 0x00000000);
2138    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2139                 SPR_NOACCESS, SPR_NOACCESS,
2140                 &spr_read_generic, SPR_NOACCESS,
2141                 0x00000000);
2142    /* Storage control */
2143    spr_register(env, SPR_440_MMUCR, "MMUCR",
2144                 SPR_NOACCESS, SPR_NOACCESS,
2145                 &spr_read_generic, &spr_write_generic,
2146                 0x00000000);
2147}
2148
2149/* SPR shared between PowerPC 40x implementations */
2150static void gen_spr_40x(CPUPPCState *env)
2151{
2152    /* Cache */
2153    /* not emulated, as QEMU do not emulate caches */
2154    spr_register(env, SPR_40x_DCCR, "DCCR",
2155                 SPR_NOACCESS, SPR_NOACCESS,
2156                 &spr_read_generic, &spr_write_generic,
2157                 0x00000000);
2158    /* not emulated, as QEMU do not emulate caches */
2159    spr_register(env, SPR_40x_ICCR, "ICCR",
2160                 SPR_NOACCESS, SPR_NOACCESS,
2161                 &spr_read_generic, &spr_write_generic,
2162                 0x00000000);
2163    /* not emulated, as QEMU do not emulate caches */
2164    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2165                 SPR_NOACCESS, SPR_NOACCESS,
2166                 &spr_read_generic, SPR_NOACCESS,
2167                 0x00000000);
2168    /* Exception */
2169    spr_register(env, SPR_40x_DEAR, "DEAR",
2170                 SPR_NOACCESS, SPR_NOACCESS,
2171                 &spr_read_generic, &spr_write_generic,
2172                 0x00000000);
2173    spr_register(env, SPR_40x_ESR, "ESR",
2174                 SPR_NOACCESS, SPR_NOACCESS,
2175                 &spr_read_generic, &spr_write_generic,
2176                 0x00000000);
2177    spr_register(env, SPR_40x_EVPR, "EVPR",
2178                 SPR_NOACCESS, SPR_NOACCESS,
2179                 &spr_read_generic, &spr_write_excp_prefix,
2180                 0x00000000);
2181    spr_register(env, SPR_40x_SRR2, "SRR2",
2182                 &spr_read_generic, &spr_write_generic,
2183                 &spr_read_generic, &spr_write_generic,
2184                 0x00000000);
2185    spr_register(env, SPR_40x_SRR3, "SRR3",
2186                 &spr_read_generic, &spr_write_generic,
2187                 &spr_read_generic, &spr_write_generic,
2188                 0x00000000);
2189    /* Timers */
2190    spr_register(env, SPR_40x_PIT, "PIT",
2191                 SPR_NOACCESS, SPR_NOACCESS,
2192                 &spr_read_40x_pit, &spr_write_40x_pit,
2193                 0x00000000);
2194    spr_register(env, SPR_40x_TCR, "TCR",
2195                 SPR_NOACCESS, SPR_NOACCESS,
2196                 &spr_read_generic, &spr_write_booke_tcr,
2197                 0x00000000);
2198    spr_register(env, SPR_40x_TSR, "TSR",
2199                 SPR_NOACCESS, SPR_NOACCESS,
2200                 &spr_read_generic, &spr_write_booke_tsr,
2201                 0x00000000);
2202}
2203
2204/* SPR specific to PowerPC 405 implementation */
2205static void gen_spr_405(CPUPPCState *env)
2206{
2207    /* MMU */
2208    spr_register(env, SPR_40x_PID, "PID",
2209                 SPR_NOACCESS, SPR_NOACCESS,
2210                 &spr_read_generic, &spr_write_generic,
2211                 0x00000000);
2212    spr_register(env, SPR_4xx_CCR0, "CCR0",
2213                 SPR_NOACCESS, SPR_NOACCESS,
2214                 &spr_read_generic, &spr_write_generic,
2215                 0x00700000);
2216    /* Debug interface */
2217    /* XXX : not implemented */
2218    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2219                 SPR_NOACCESS, SPR_NOACCESS,
2220                 &spr_read_generic, &spr_write_40x_dbcr0,
2221                 0x00000000);
2222    /* XXX : not implemented */
2223    spr_register(env, SPR_405_DBCR1, "DBCR1",
2224                 SPR_NOACCESS, SPR_NOACCESS,
2225                 &spr_read_generic, &spr_write_generic,
2226                 0x00000000);
2227    /* XXX : not implemented */
2228    spr_register(env, SPR_40x_DBSR, "DBSR",
2229                 SPR_NOACCESS, SPR_NOACCESS,
2230                 &spr_read_generic, &spr_write_clear,
2231                 /* Last reset was system reset */
2232                 0x00000300);
2233    /* XXX : not implemented */
2234    spr_register(env, SPR_40x_DAC1, "DAC1",
2235                 SPR_NOACCESS, SPR_NOACCESS,
2236                 &spr_read_generic, &spr_write_generic,
2237                 0x00000000);
2238    spr_register(env, SPR_40x_DAC2, "DAC2",
2239                 SPR_NOACCESS, SPR_NOACCESS,
2240                 &spr_read_generic, &spr_write_generic,
2241                 0x00000000);
2242    /* XXX : not implemented */
2243    spr_register(env, SPR_405_DVC1, "DVC1",
2244                 SPR_NOACCESS, SPR_NOACCESS,
2245                 &spr_read_generic, &spr_write_generic,
2246                 0x00000000);
2247    /* XXX : not implemented */
2248    spr_register(env, SPR_405_DVC2, "DVC2",
2249                 SPR_NOACCESS, SPR_NOACCESS,
2250                 &spr_read_generic, &spr_write_generic,
2251                 0x00000000);
2252    /* XXX : not implemented */
2253    spr_register(env, SPR_40x_IAC1, "IAC1",
2254                 SPR_NOACCESS, SPR_NOACCESS,
2255                 &spr_read_generic, &spr_write_generic,
2256                 0x00000000);
2257    spr_register(env, SPR_40x_IAC2, "IAC2",
2258                 SPR_NOACCESS, SPR_NOACCESS,
2259                 &spr_read_generic, &spr_write_generic,
2260                 0x00000000);
2261    /* XXX : not implemented */
2262    spr_register(env, SPR_405_IAC3, "IAC3",
2263                 SPR_NOACCESS, SPR_NOACCESS,
2264                 &spr_read_generic, &spr_write_generic,
2265                 0x00000000);
2266    /* XXX : not implemented */
2267    spr_register(env, SPR_405_IAC4, "IAC4",
2268                 SPR_NOACCESS, SPR_NOACCESS,
2269                 &spr_read_generic, &spr_write_generic,
2270                 0x00000000);
2271    /* Storage control */
2272    /* XXX: TODO: not implemented */
2273    spr_register(env, SPR_405_SLER, "SLER",
2274                 SPR_NOACCESS, SPR_NOACCESS,
2275                 &spr_read_generic, &spr_write_40x_sler,
2276                 0x00000000);
2277    spr_register(env, SPR_40x_ZPR, "ZPR",
2278                 SPR_NOACCESS, SPR_NOACCESS,
2279                 &spr_read_generic, &spr_write_generic,
2280                 0x00000000);
2281    /* XXX : not implemented */
2282    spr_register(env, SPR_405_SU0R, "SU0R",
2283                 SPR_NOACCESS, SPR_NOACCESS,
2284                 &spr_read_generic, &spr_write_generic,
2285                 0x00000000);
2286    /* SPRG */
2287    spr_register(env, SPR_USPRG0, "USPRG0",
2288                 &spr_read_ureg, SPR_NOACCESS,
2289                 &spr_read_ureg, SPR_NOACCESS,
2290                 0x00000000);
2291    spr_register(env, SPR_SPRG4, "SPRG4",
2292                 SPR_NOACCESS, SPR_NOACCESS,
2293                 &spr_read_generic, &spr_write_generic,
2294                 0x00000000);
2295    spr_register(env, SPR_SPRG5, "SPRG5",
2296                 SPR_NOACCESS, SPR_NOACCESS,
2297                 spr_read_generic, &spr_write_generic,
2298                 0x00000000);
2299    spr_register(env, SPR_SPRG6, "SPRG6",
2300                 SPR_NOACCESS, SPR_NOACCESS,
2301                 spr_read_generic, &spr_write_generic,
2302                 0x00000000);
2303    spr_register(env, SPR_SPRG7, "SPRG7",
2304                 SPR_NOACCESS, SPR_NOACCESS,
2305                 spr_read_generic, &spr_write_generic,
2306                 0x00000000);
2307    gen_spr_usprgh(env);
2308}
2309
2310/* SPR shared between PowerPC 401 & 403 implementations */
2311static void gen_spr_401_403(CPUPPCState *env)
2312{
2313    /* Time base */
2314    spr_register(env, SPR_403_VTBL,  "TBL",
2315                 &spr_read_tbl, SPR_NOACCESS,
2316                 &spr_read_tbl, SPR_NOACCESS,
2317                 0x00000000);
2318    spr_register(env, SPR_403_TBL,   "TBL",
2319                 SPR_NOACCESS, SPR_NOACCESS,
2320                 SPR_NOACCESS, &spr_write_tbl,
2321                 0x00000000);
2322    spr_register(env, SPR_403_VTBU,  "TBU",
2323                 &spr_read_tbu, SPR_NOACCESS,
2324                 &spr_read_tbu, SPR_NOACCESS,
2325                 0x00000000);
2326    spr_register(env, SPR_403_TBU,   "TBU",
2327                 SPR_NOACCESS, SPR_NOACCESS,
2328                 SPR_NOACCESS, &spr_write_tbu,
2329                 0x00000000);
2330    /* Debug */
2331    /* not emulated, as QEMU do not emulate caches */
2332    spr_register(env, SPR_403_CDBCR, "CDBCR",
2333                 SPR_NOACCESS, SPR_NOACCESS,
2334                 &spr_read_generic, &spr_write_generic,
2335                 0x00000000);
2336}
2337
2338/* SPR specific to PowerPC 401 implementation */
2339static void gen_spr_401(CPUPPCState *env)
2340{
2341    /* Debug interface */
2342    /* XXX : not implemented */
2343    spr_register(env, SPR_40x_DBCR0, "DBCR",
2344                 SPR_NOACCESS, SPR_NOACCESS,
2345                 &spr_read_generic, &spr_write_40x_dbcr0,
2346                 0x00000000);
2347    /* XXX : not implemented */
2348    spr_register(env, SPR_40x_DBSR, "DBSR",
2349                 SPR_NOACCESS, SPR_NOACCESS,
2350                 &spr_read_generic, &spr_write_clear,
2351                 /* Last reset was system reset */
2352                 0x00000300);
2353    /* XXX : not implemented */
2354    spr_register(env, SPR_40x_DAC1, "DAC",
2355                 SPR_NOACCESS, SPR_NOACCESS,
2356                 &spr_read_generic, &spr_write_generic,
2357                 0x00000000);
2358    /* XXX : not implemented */
2359    spr_register(env, SPR_40x_IAC1, "IAC",
2360                 SPR_NOACCESS, SPR_NOACCESS,
2361                 &spr_read_generic, &spr_write_generic,
2362                 0x00000000);
2363    /* Storage control */
2364    /* XXX: TODO: not implemented */
2365    spr_register(env, SPR_405_SLER, "SLER",
2366                 SPR_NOACCESS, SPR_NOACCESS,
2367                 &spr_read_generic, &spr_write_40x_sler,
2368                 0x00000000);
2369    /* not emulated, as QEMU never does speculative access */
2370    spr_register(env, SPR_40x_SGR, "SGR",
2371                 SPR_NOACCESS, SPR_NOACCESS,
2372                 &spr_read_generic, &spr_write_generic,
2373                 0xFFFFFFFF);
2374    /* not emulated, as QEMU do not emulate caches */
2375    spr_register(env, SPR_40x_DCWR, "DCWR",
2376                 SPR_NOACCESS, SPR_NOACCESS,
2377                 &spr_read_generic, &spr_write_generic,
2378                 0x00000000);
2379}
2380
2381static void gen_spr_401x2(CPUPPCState *env)
2382{
2383    gen_spr_401(env);
2384    spr_register(env, SPR_40x_PID, "PID",
2385                 SPR_NOACCESS, SPR_NOACCESS,
2386                 &spr_read_generic, &spr_write_generic,
2387                 0x00000000);
2388    spr_register(env, SPR_40x_ZPR, "ZPR",
2389                 SPR_NOACCESS, SPR_NOACCESS,
2390                 &spr_read_generic, &spr_write_generic,
2391                 0x00000000);
2392}
2393
2394/* SPR specific to PowerPC 403 implementation */
2395static void gen_spr_403(CPUPPCState *env)
2396{
2397    /* Debug interface */
2398    /* XXX : not implemented */
2399    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2400                 SPR_NOACCESS, SPR_NOACCESS,
2401                 &spr_read_generic, &spr_write_40x_dbcr0,
2402                 0x00000000);
2403    /* XXX : not implemented */
2404    spr_register(env, SPR_40x_DBSR, "DBSR",
2405                 SPR_NOACCESS, SPR_NOACCESS,
2406                 &spr_read_generic, &spr_write_clear,
2407                 /* Last reset was system reset */
2408                 0x00000300);
2409    /* XXX : not implemented */
2410    spr_register(env, SPR_40x_DAC1, "DAC1",
2411                 SPR_NOACCESS, SPR_NOACCESS,
2412                 &spr_read_generic, &spr_write_generic,
2413                 0x00000000);
2414    /* XXX : not implemented */
2415    spr_register(env, SPR_40x_DAC2, "DAC2",
2416                 SPR_NOACCESS, SPR_NOACCESS,
2417                 &spr_read_generic, &spr_write_generic,
2418                 0x00000000);
2419    /* XXX : not implemented */
2420    spr_register(env, SPR_40x_IAC1, "IAC1",
2421                 SPR_NOACCESS, SPR_NOACCESS,
2422                 &spr_read_generic, &spr_write_generic,
2423                 0x00000000);
2424    /* XXX : not implemented */
2425    spr_register(env, SPR_40x_IAC2, "IAC2",
2426                 SPR_NOACCESS, SPR_NOACCESS,
2427                 &spr_read_generic, &spr_write_generic,
2428                 0x00000000);
2429}
2430
2431static void gen_spr_403_real(CPUPPCState *env)
2432{
2433    spr_register(env, SPR_403_PBL1,  "PBL1",
2434                 SPR_NOACCESS, SPR_NOACCESS,
2435                 &spr_read_403_pbr, &spr_write_403_pbr,
2436                 0x00000000);
2437    spr_register(env, SPR_403_PBU1,  "PBU1",
2438                 SPR_NOACCESS, SPR_NOACCESS,
2439                 &spr_read_403_pbr, &spr_write_403_pbr,
2440                 0x00000000);
2441    spr_register(env, SPR_403_PBL2,  "PBL2",
2442                 SPR_NOACCESS, SPR_NOACCESS,
2443                 &spr_read_403_pbr, &spr_write_403_pbr,
2444                 0x00000000);
2445    spr_register(env, SPR_403_PBU2,  "PBU2",
2446                 SPR_NOACCESS, SPR_NOACCESS,
2447                 &spr_read_403_pbr, &spr_write_403_pbr,
2448                 0x00000000);
2449}
2450
2451static void gen_spr_403_mmu(CPUPPCState *env)
2452{
2453    /* MMU */
2454    spr_register(env, SPR_40x_PID, "PID",
2455                 SPR_NOACCESS, SPR_NOACCESS,
2456                 &spr_read_generic, &spr_write_generic,
2457                 0x00000000);
2458    spr_register(env, SPR_40x_ZPR, "ZPR",
2459                 SPR_NOACCESS, SPR_NOACCESS,
2460                 &spr_read_generic, &spr_write_generic,
2461                 0x00000000);
2462}
2463
2464/* SPR specific to PowerPC compression coprocessor extension */
2465static void gen_spr_compress(CPUPPCState *env)
2466{
2467    /* XXX : not implemented */
2468    spr_register(env, SPR_401_SKR, "SKR",
2469                 SPR_NOACCESS, SPR_NOACCESS,
2470                 &spr_read_generic, &spr_write_generic,
2471                 0x00000000);
2472}
2473
2474static void gen_spr_5xx_8xx(CPUPPCState *env)
2475{
2476    /* Exception processing */
2477    spr_register_kvm(env, SPR_DSISR, "DSISR",
2478                     SPR_NOACCESS, SPR_NOACCESS,
2479                     &spr_read_generic, &spr_write_generic,
2480                     KVM_REG_PPC_DSISR, 0x00000000);
2481    spr_register_kvm(env, SPR_DAR, "DAR",
2482                     SPR_NOACCESS, SPR_NOACCESS,
2483                     &spr_read_generic, &spr_write_generic,
2484                     KVM_REG_PPC_DAR, 0x00000000);
2485    /* Timer */
2486    spr_register(env, SPR_DECR, "DECR",
2487                 SPR_NOACCESS, SPR_NOACCESS,
2488                 &spr_read_decr, &spr_write_decr,
2489                 0x00000000);
2490    /* XXX : not implemented */
2491    spr_register(env, SPR_MPC_EIE, "EIE",
2492                 SPR_NOACCESS, SPR_NOACCESS,
2493                 &spr_read_generic, &spr_write_generic,
2494                 0x00000000);
2495    /* XXX : not implemented */
2496    spr_register(env, SPR_MPC_EID, "EID",
2497                 SPR_NOACCESS, SPR_NOACCESS,
2498                 &spr_read_generic, &spr_write_generic,
2499                 0x00000000);
2500    /* XXX : not implemented */
2501    spr_register(env, SPR_MPC_NRI, "NRI",
2502                 SPR_NOACCESS, SPR_NOACCESS,
2503                 &spr_read_generic, &spr_write_generic,
2504                 0x00000000);
2505    /* XXX : not implemented */
2506    spr_register(env, SPR_MPC_CMPA, "CMPA",
2507                 SPR_NOACCESS, SPR_NOACCESS,
2508                 &spr_read_generic, &spr_write_generic,
2509                 0x00000000);
2510    /* XXX : not implemented */
2511    spr_register(env, SPR_MPC_CMPB, "CMPB",
2512                 SPR_NOACCESS, SPR_NOACCESS,
2513                 &spr_read_generic, &spr_write_generic,
2514                 0x00000000);
2515    /* XXX : not implemented */
2516    spr_register(env, SPR_MPC_CMPC, "CMPC",
2517                 SPR_NOACCESS, SPR_NOACCESS,
2518                 &spr_read_generic, &spr_write_generic,
2519                 0x00000000);
2520    /* XXX : not implemented */
2521    spr_register(env, SPR_MPC_CMPD, "CMPD",
2522                 SPR_NOACCESS, SPR_NOACCESS,
2523                 &spr_read_generic, &spr_write_generic,
2524                 0x00000000);
2525    /* XXX : not implemented */
2526    spr_register(env, SPR_MPC_ECR, "ECR",
2527                 SPR_NOACCESS, SPR_NOACCESS,
2528                 &spr_read_generic, &spr_write_generic,
2529                 0x00000000);
2530    /* XXX : not implemented */
2531    spr_register(env, SPR_MPC_DER, "DER",
2532                 SPR_NOACCESS, SPR_NOACCESS,
2533                 &spr_read_generic, &spr_write_generic,
2534                 0x00000000);
2535    /* XXX : not implemented */
2536    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2537                 SPR_NOACCESS, SPR_NOACCESS,
2538                 &spr_read_generic, &spr_write_generic,
2539                 0x00000000);
2540    /* XXX : not implemented */
2541    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2542                 SPR_NOACCESS, SPR_NOACCESS,
2543                 &spr_read_generic, &spr_write_generic,
2544                 0x00000000);
2545    /* XXX : not implemented */
2546    spr_register(env, SPR_MPC_CMPE, "CMPE",
2547                 SPR_NOACCESS, SPR_NOACCESS,
2548                 &spr_read_generic, &spr_write_generic,
2549                 0x00000000);
2550    /* XXX : not implemented */
2551    spr_register(env, SPR_MPC_CMPF, "CMPF",
2552                 SPR_NOACCESS, SPR_NOACCESS,
2553                 &spr_read_generic, &spr_write_generic,
2554                 0x00000000);
2555    /* XXX : not implemented */
2556    spr_register(env, SPR_MPC_CMPG, "CMPG",
2557                 SPR_NOACCESS, SPR_NOACCESS,
2558                 &spr_read_generic, &spr_write_generic,
2559                 0x00000000);
2560    /* XXX : not implemented */
2561    spr_register(env, SPR_MPC_CMPH, "CMPH",
2562                 SPR_NOACCESS, SPR_NOACCESS,
2563                 &spr_read_generic, &spr_write_generic,
2564                 0x00000000);
2565    /* XXX : not implemented */
2566    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2567                 SPR_NOACCESS, SPR_NOACCESS,
2568                 &spr_read_generic, &spr_write_generic,
2569                 0x00000000);
2570    /* XXX : not implemented */
2571    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2572                 SPR_NOACCESS, SPR_NOACCESS,
2573                 &spr_read_generic, &spr_write_generic,
2574                 0x00000000);
2575    /* XXX : not implemented */
2576    spr_register(env, SPR_MPC_BAR, "BAR",
2577                 SPR_NOACCESS, SPR_NOACCESS,
2578                 &spr_read_generic, &spr_write_generic,
2579                 0x00000000);
2580    /* XXX : not implemented */
2581    spr_register(env, SPR_MPC_DPDR, "DPDR",
2582                 SPR_NOACCESS, SPR_NOACCESS,
2583                 &spr_read_generic, &spr_write_generic,
2584                 0x00000000);
2585    /* XXX : not implemented */
2586    spr_register(env, SPR_MPC_IMMR, "IMMR",
2587                 SPR_NOACCESS, SPR_NOACCESS,
2588                 &spr_read_generic, &spr_write_generic,
2589                 0x00000000);
2590}
2591
2592static void gen_spr_5xx(CPUPPCState *env)
2593{
2594    /* XXX : not implemented */
2595    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2596                 SPR_NOACCESS, SPR_NOACCESS,
2597                 &spr_read_generic, &spr_write_generic,
2598                 0x00000000);
2599    /* XXX : not implemented */
2600    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2601                 SPR_NOACCESS, SPR_NOACCESS,
2602                 &spr_read_generic, &spr_write_generic,
2603                 0x00000000);
2604    /* XXX : not implemented */
2605    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2606                 SPR_NOACCESS, SPR_NOACCESS,
2607                 &spr_read_generic, &spr_write_generic,
2608                 0x00000000);
2609    /* XXX : not implemented */
2610    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2611                 SPR_NOACCESS, SPR_NOACCESS,
2612                 &spr_read_generic, &spr_write_generic,
2613                 0x00000000);
2614    /* XXX : not implemented */
2615    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2616                 SPR_NOACCESS, SPR_NOACCESS,
2617                 &spr_read_generic, &spr_write_generic,
2618                 0x00000000);
2619    /* XXX : not implemented */
2620    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2621                 SPR_NOACCESS, SPR_NOACCESS,
2622                 &spr_read_generic, &spr_write_generic,
2623                 0x00000000);
2624    /* XXX : not implemented */
2625    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2626                 SPR_NOACCESS, SPR_NOACCESS,
2627                 &spr_read_generic, &spr_write_generic,
2628                 0x00000000);
2629    /* XXX : not implemented */
2630    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2631                 SPR_NOACCESS, SPR_NOACCESS,
2632                 &spr_read_generic, &spr_write_generic,
2633                 0x00000000);
2634    /* XXX : not implemented */
2635    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2636                 SPR_NOACCESS, SPR_NOACCESS,
2637                 &spr_read_generic, &spr_write_generic,
2638                 0x00000000);
2639    /* XXX : not implemented */
2640    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2641                 SPR_NOACCESS, SPR_NOACCESS,
2642                 &spr_read_generic, &spr_write_generic,
2643                 0x00000000);
2644    /* XXX : not implemented */
2645    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2646                 SPR_NOACCESS, SPR_NOACCESS,
2647                 &spr_read_generic, &spr_write_generic,
2648                 0x00000000);
2649    /* XXX : not implemented */
2650    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2651                 SPR_NOACCESS, SPR_NOACCESS,
2652                 &spr_read_generic, &spr_write_generic,
2653                 0x00000000);
2654    /* XXX : not implemented */
2655    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2656                 SPR_NOACCESS, SPR_NOACCESS,
2657                 &spr_read_generic, &spr_write_generic,
2658                 0x00000000);
2659    /* XXX : not implemented */
2660    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2661                 SPR_NOACCESS, SPR_NOACCESS,
2662                 &spr_read_generic, &spr_write_generic,
2663                 0x00000000);
2664    /* XXX : not implemented */
2665    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2666                 SPR_NOACCESS, SPR_NOACCESS,
2667                 &spr_read_generic, &spr_write_generic,
2668                 0x00000000);
2669    /* XXX : not implemented */
2670    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2671                 SPR_NOACCESS, SPR_NOACCESS,
2672                 &spr_read_generic, &spr_write_generic,
2673                 0x00000000);
2674    /* XXX : not implemented */
2675    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2676                 SPR_NOACCESS, SPR_NOACCESS,
2677                 &spr_read_generic, &spr_write_generic,
2678                 0x00000000);
2679    /* XXX : not implemented */
2680    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2681                 SPR_NOACCESS, SPR_NOACCESS,
2682                 &spr_read_generic, &spr_write_generic,
2683                 0x00000000);
2684    /* XXX : not implemented */
2685    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2686                 SPR_NOACCESS, SPR_NOACCESS,
2687                 &spr_read_generic, &spr_write_generic,
2688                 0x00000000);
2689    /* XXX : not implemented */
2690    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2691                 SPR_NOACCESS, SPR_NOACCESS,
2692                 &spr_read_generic, &spr_write_generic,
2693                 0x00000000);
2694    /* XXX : not implemented */
2695    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2696                 SPR_NOACCESS, SPR_NOACCESS,
2697                 &spr_read_generic, &spr_write_generic,
2698                 0x00000000);
2699}
2700
2701static void gen_spr_8xx(CPUPPCState *env)
2702{
2703    /* XXX : not implemented */
2704    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2705                 SPR_NOACCESS, SPR_NOACCESS,
2706                 &spr_read_generic, &spr_write_generic,
2707                 0x00000000);
2708    /* XXX : not implemented */
2709    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2710                 SPR_NOACCESS, SPR_NOACCESS,
2711                 &spr_read_generic, &spr_write_generic,
2712                 0x00000000);
2713    /* XXX : not implemented */
2714    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2715                 SPR_NOACCESS, SPR_NOACCESS,
2716                 &spr_read_generic, &spr_write_generic,
2717                 0x00000000);
2718    /* XXX : not implemented */
2719    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2720                 SPR_NOACCESS, SPR_NOACCESS,
2721                 &spr_read_generic, &spr_write_generic,
2722                 0x00000000);
2723    /* XXX : not implemented */
2724    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2725                 SPR_NOACCESS, SPR_NOACCESS,
2726                 &spr_read_generic, &spr_write_generic,
2727                 0x00000000);
2728    /* XXX : not implemented */
2729    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2730                 SPR_NOACCESS, SPR_NOACCESS,
2731                 &spr_read_generic, &spr_write_generic,
2732                 0x00000000);
2733    /* XXX : not implemented */
2734    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2735                 SPR_NOACCESS, SPR_NOACCESS,
2736                 &spr_read_generic, &spr_write_generic,
2737                 0x00000000);
2738    /* XXX : not implemented */
2739    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2740                 SPR_NOACCESS, SPR_NOACCESS,
2741                 &spr_read_generic, &spr_write_generic,
2742                 0x00000000);
2743    /* XXX : not implemented */
2744    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2745                 SPR_NOACCESS, SPR_NOACCESS,
2746                 &spr_read_generic, &spr_write_generic,
2747                 0x00000000);
2748    /* XXX : not implemented */
2749    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2750                 SPR_NOACCESS, SPR_NOACCESS,
2751                 &spr_read_generic, &spr_write_generic,
2752                 0x00000000);
2753    /* XXX : not implemented */
2754    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2755                 SPR_NOACCESS, SPR_NOACCESS,
2756                 &spr_read_generic, &spr_write_generic,
2757                 0x00000000);
2758    /* XXX : not implemented */
2759    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2760                 SPR_NOACCESS, SPR_NOACCESS,
2761                 &spr_read_generic, &spr_write_generic,
2762                 0x00000000);
2763    /* XXX : not implemented */
2764    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2765                 SPR_NOACCESS, SPR_NOACCESS,
2766                 &spr_read_generic, &spr_write_generic,
2767                 0x00000000);
2768    /* XXX : not implemented */
2769    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2770                 SPR_NOACCESS, SPR_NOACCESS,
2771                 &spr_read_generic, &spr_write_generic,
2772                 0x00000000);
2773    /* XXX : not implemented */
2774    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2775                 SPR_NOACCESS, SPR_NOACCESS,
2776                 &spr_read_generic, &spr_write_generic,
2777                 0x00000000);
2778    /* XXX : not implemented */
2779    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2780                 SPR_NOACCESS, SPR_NOACCESS,
2781                 &spr_read_generic, &spr_write_generic,
2782                 0x00000000);
2783    /* XXX : not implemented */
2784    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2785                 SPR_NOACCESS, SPR_NOACCESS,
2786                 &spr_read_generic, &spr_write_generic,
2787                 0x00000000);
2788    /* XXX : not implemented */
2789    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2790                 SPR_NOACCESS, SPR_NOACCESS,
2791                 &spr_read_generic, &spr_write_generic,
2792                 0x00000000);
2793    /* XXX : not implemented */
2794    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2795                 SPR_NOACCESS, SPR_NOACCESS,
2796                 &spr_read_generic, &spr_write_generic,
2797                 0x00000000);
2798    /* XXX : not implemented */
2799    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2800                 SPR_NOACCESS, SPR_NOACCESS,
2801                 &spr_read_generic, &spr_write_generic,
2802                 0x00000000);
2803    /* XXX : not implemented */
2804    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2805                 SPR_NOACCESS, SPR_NOACCESS,
2806                 &spr_read_generic, &spr_write_generic,
2807                 0x00000000);
2808    /* XXX : not implemented */
2809    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2810                 SPR_NOACCESS, SPR_NOACCESS,
2811                 &spr_read_generic, &spr_write_generic,
2812                 0x00000000);
2813    /* XXX : not implemented */
2814    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2815                 SPR_NOACCESS, SPR_NOACCESS,
2816                 &spr_read_generic, &spr_write_generic,
2817                 0x00000000);
2818    /* XXX : not implemented */
2819    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2820                 SPR_NOACCESS, SPR_NOACCESS,
2821                 &spr_read_generic, &spr_write_generic,
2822                 0x00000000);
2823    /* XXX : not implemented */
2824    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2825                 SPR_NOACCESS, SPR_NOACCESS,
2826                 &spr_read_generic, &spr_write_generic,
2827                 0x00000000);
2828}
2829
2830/*
2831 * AMR     => SPR 29 (Power 2.04)
2832 * CTRL    => SPR 136 (Power 2.04)
2833 * CTRL    => SPR 152 (Power 2.04)
2834 * SCOMC   => SPR 276 (64 bits ?)
2835 * SCOMD   => SPR 277 (64 bits ?)
2836 * TBU40   => SPR 286 (Power 2.04 hypv)
2837 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2838 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2839 * HDSISR  => SPR 306 (Power 2.04 hypv)
2840 * HDAR    => SPR 307 (Power 2.04 hypv)
2841 * PURR    => SPR 309 (Power 2.04 hypv)
2842 * HDEC    => SPR 310 (Power 2.04 hypv)
2843 * HIOR    => SPR 311 (hypv)
2844 * RMOR    => SPR 312 (970)
2845 * HRMOR   => SPR 313 (Power 2.04 hypv)
2846 * HSRR0   => SPR 314 (Power 2.04 hypv)
2847 * HSRR1   => SPR 315 (Power 2.04 hypv)
2848 * LPIDR   => SPR 317 (970)
2849 * EPR     => SPR 702 (Power 2.04 emb)
2850 * perf    => 768-783 (Power 2.04)
2851 * perf    => 784-799 (Power 2.04)
2852 * PPR     => SPR 896 (Power 2.04)
2853 * DABRX   => 1015    (Power 2.04 hypv)
2854 * FPECR   => SPR 1022 (?)
2855 * ... and more (thermal management, performance counters, ...)
2856 */
2857
2858/*****************************************************************************/
2859/* Exception vectors models                                                  */
2860static void init_excp_4xx_real(CPUPPCState *env)
2861{
2862#if !defined(CONFIG_USER_ONLY)
2863    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2864    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2865    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2866    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2867    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2868    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2869    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2870    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2871    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2872    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2873    env->ivor_mask = 0x0000FFF0UL;
2874    env->ivpr_mask = 0xFFFF0000UL;
2875    /* Hardware reset vector */
2876    env->hreset_vector = 0xFFFFFFFCUL;
2877#endif
2878}
2879
2880static void init_excp_4xx_softmmu(CPUPPCState *env)
2881{
2882#if !defined(CONFIG_USER_ONLY)
2883    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2884    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2885    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2886    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2887    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2888    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2889    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2890    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2891    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2892    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2893    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2894    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2895    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2896    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2897    env->ivor_mask = 0x0000FFF0UL;
2898    env->ivpr_mask = 0xFFFF0000UL;
2899    /* Hardware reset vector */
2900    env->hreset_vector = 0xFFFFFFFCUL;
2901#endif
2902}
2903
2904static void init_excp_MPC5xx(CPUPPCState *env)
2905{
2906#if !defined(CONFIG_USER_ONLY)
2907    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2908    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2909    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2910    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2911    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2912    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2913    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2914    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2915    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2916    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2917    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2918    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2919    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2920    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2921    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2922    env->ivor_mask = 0x0000FFF0UL;
2923    env->ivpr_mask = 0xFFFF0000UL;
2924    /* Hardware reset vector */
2925    env->hreset_vector = 0x00000100UL;
2926#endif
2927}
2928
2929static void init_excp_MPC8xx(CPUPPCState *env)
2930{
2931#if !defined(CONFIG_USER_ONLY)
2932    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2933    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2934    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2935    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2936    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2937    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2938    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2939    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2940    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2941    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2942    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2943    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2944    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2945    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2946    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2947    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2948    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2949    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2950    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2951    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2952    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2953    env->ivor_mask = 0x0000FFF0UL;
2954    env->ivpr_mask = 0xFFFF0000UL;
2955    /* Hardware reset vector */
2956    env->hreset_vector = 0x00000100UL;
2957#endif
2958}
2959
2960static void init_excp_G2(CPUPPCState *env)
2961{
2962#if !defined(CONFIG_USER_ONLY)
2963    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2964    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2965    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2966    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2967    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2969    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2970    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2971    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2972    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2973    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2974    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2975    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2976    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2977    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2978    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2979    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2980    /* Hardware reset vector */
2981    env->hreset_vector = 0x00000100UL;
2982#endif
2983}
2984
2985static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2986{
2987#if !defined(CONFIG_USER_ONLY)
2988    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2989    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2990    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2991    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2992    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2993    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2994    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2995    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2996    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2997    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2998    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2999    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
3000    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
3001    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3002    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3003    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3004    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3005    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
3006    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
3007    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
3008    env->ivor_mask = 0x0000FFF7UL;
3009    env->ivpr_mask = ivpr_mask;
3010    /* Hardware reset vector */
3011    env->hreset_vector = 0xFFFFFFFCUL;
3012#endif
3013}
3014
3015static void init_excp_BookE(CPUPPCState *env)
3016{
3017#if !defined(CONFIG_USER_ONLY)
3018    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3019    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
3020    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
3021    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
3022    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3023    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
3024    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
3025    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
3026    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
3027    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
3028    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
3029    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
3030    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3031    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3032    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3033    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3034    env->ivor_mask = 0x0000FFF0UL;
3035    env->ivpr_mask = 0xFFFF0000UL;
3036    /* Hardware reset vector */
3037    env->hreset_vector = 0xFFFFFFFCUL;
3038#endif
3039}
3040
3041static void init_excp_601(CPUPPCState *env)
3042{
3043#if !defined(CONFIG_USER_ONLY)
3044    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3045    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3046    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3047    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3048    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3049    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3050    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3051    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3052    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3053    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
3054    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3055    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
3056    /* Hardware reset vector */
3057    env->hreset_vector = 0x00000100UL;
3058#endif
3059}
3060
3061static void init_excp_602(CPUPPCState *env)
3062{
3063#if !defined(CONFIG_USER_ONLY)
3064    /* XXX: exception prefix has a special behavior on 602 */
3065    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3066    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3067    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3068    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3069    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3070    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3071    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3072    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3073    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3074    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3075    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3076    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3077    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3078    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3079    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3080    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3081    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
3082    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
3083    /* Hardware reset vector */
3084    env->hreset_vector = 0x00000100UL;
3085#endif
3086}
3087
3088static void init_excp_603(CPUPPCState *env)
3089{
3090#if !defined(CONFIG_USER_ONLY)
3091    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3092    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3093    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3094    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3095    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3096    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3097    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3098    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3099    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3100    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3101    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3102    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3103    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3104    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3105    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3106    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3107    /* Hardware reset vector */
3108    env->hreset_vector = 0x00000100UL;
3109#endif
3110}
3111
3112static void init_excp_604(CPUPPCState *env)
3113{
3114#if !defined(CONFIG_USER_ONLY)
3115    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3116    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3117    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3118    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3119    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3120    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3121    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3122    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3123    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3124    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3125    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3126    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3127    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3128    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3129    /* Hardware reset vector */
3130    env->hreset_vector = 0x00000100UL;
3131#endif
3132}
3133
3134static void init_excp_7x0(CPUPPCState *env)
3135{
3136#if !defined(CONFIG_USER_ONLY)
3137    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3138    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3139    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3140    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3141    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3142    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3143    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3144    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3145    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3146    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3147    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3148    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3149    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3150    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3151    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3152    /* Hardware reset vector */
3153    env->hreset_vector = 0x00000100UL;
3154#endif
3155}
3156
3157static void init_excp_750cl(CPUPPCState *env)
3158{
3159#if !defined(CONFIG_USER_ONLY)
3160    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3161    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3162    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3163    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3164    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3165    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3166    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3167    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3168    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3169    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3170    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3171    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3172    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3173    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3174    /* Hardware reset vector */
3175    env->hreset_vector = 0x00000100UL;
3176#endif
3177}
3178
3179static void init_excp_750cx(CPUPPCState *env)
3180{
3181#if !defined(CONFIG_USER_ONLY)
3182    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3183    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3184    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3185    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3186    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3187    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3188    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3189    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3190    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3191    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3192    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3193    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3194    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3195    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3196    /* Hardware reset vector */
3197    env->hreset_vector = 0x00000100UL;
3198#endif
3199}
3200
3201/* XXX: Check if this is correct */
3202static void init_excp_7x5(CPUPPCState *env)
3203{
3204#if !defined(CONFIG_USER_ONLY)
3205    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3206    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3207    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3208    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3209    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3210    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3211    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3212    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3213    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3214    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3215    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3216    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3217    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3218    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3219    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3220    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3221    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3222    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3223    /* Hardware reset vector */
3224    env->hreset_vector = 0x00000100UL;
3225#endif
3226}
3227
3228static void init_excp_7400(CPUPPCState *env)
3229{
3230#if !defined(CONFIG_USER_ONLY)
3231    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3232    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3233    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3234    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3235    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3236    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3237    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3238    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3239    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3240    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3241    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3242    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3243    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3244    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3245    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3246    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3247    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3248    /* Hardware reset vector */
3249    env->hreset_vector = 0x00000100UL;
3250#endif
3251}
3252
3253static void init_excp_7450(CPUPPCState *env)
3254{
3255#if !defined(CONFIG_USER_ONLY)
3256    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3257    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3258    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3259    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3260    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3261    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3262    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3263    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3264    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3265    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3266    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3267    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3268    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3269    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3270    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3271    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3272    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3273    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3274    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3275    /* Hardware reset vector */
3276    env->hreset_vector = 0x00000100UL;
3277#endif
3278}
3279
3280#if defined(TARGET_PPC64)
3281static void init_excp_970(CPUPPCState *env)
3282{
3283#if !defined(CONFIG_USER_ONLY)
3284    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3285    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3286    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3287    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3288    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3289    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3290    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3291    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3292    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3293    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3294    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3295    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3296    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3297    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3298    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3299    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3300    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3301    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3302    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3303    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3304    /* Hardware reset vector */
3305    env->hreset_vector = 0x0000000000000100ULL;
3306#endif
3307}
3308
3309static void init_excp_POWER7(CPUPPCState *env)
3310{
3311#if !defined(CONFIG_USER_ONLY)
3312    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3313    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3314    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3315    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3316    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3317    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3318    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3319    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3320    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3321    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3322    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3323    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3324    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3325    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3326    env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
3327    env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
3328    env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
3329    env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3330    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3331    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3332    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
3333    /* Hardware reset vector */
3334    env->hreset_vector = 0x0000000000000100ULL;
3335#endif
3336}
3337
3338static void init_excp_POWER8(CPUPPCState *env)
3339{
3340    init_excp_POWER7(env);
3341
3342#if !defined(CONFIG_USER_ONLY)
3343    env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
3344    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
3345    env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
3346    env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3347#endif
3348}
3349
3350static void init_excp_POWER9(CPUPPCState *env)
3351{
3352    init_excp_POWER8(env);
3353
3354#if !defined(CONFIG_USER_ONLY)
3355    env->excp_vectors[POWERPC_EXCP_HVIRT]    = 0x00000EA0;
3356#endif
3357}
3358
3359#endif
3360
3361/*****************************************************************************/
3362/* Power management enable checks                                            */
3363static int check_pow_none(CPUPPCState *env)
3364{
3365    return 0;
3366}
3367
3368static int check_pow_nocheck(CPUPPCState *env)
3369{
3370    return 1;
3371}
3372
3373static int check_pow_hid0(CPUPPCState *env)
3374{
3375    if (env->spr[SPR_HID0] & 0x00E00000) {
3376        return 1;
3377    }
3378
3379    return 0;
3380}
3381
3382static int check_pow_hid0_74xx(CPUPPCState *env)
3383{
3384    if (env->spr[SPR_HID0] & 0x00600000) {
3385        return 1;
3386    }
3387
3388    return 0;
3389}
3390
3391static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3392{
3393    return true;
3394}
3395
3396#ifdef TARGET_PPC64
3397static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3398{
3399    return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3400}
3401#endif
3402
3403/*****************************************************************************/
3404/* PowerPC implementations definitions                                       */
3405
3406#define POWERPC_FAMILY(_name)                                               \
3407    static void                                                             \
3408    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3409                                                                            \
3410    static const TypeInfo                                                   \
3411    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3412        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3413        .parent = TYPE_POWERPC_CPU,                                         \
3414        .abstract = true,                                                   \
3415        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3416    };                                                                      \
3417                                                                            \
3418    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3419    {                                                                       \
3420        type_register_static(                                               \
3421            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3422    }                                                                       \
3423                                                                            \
3424    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3425                                                                            \
3426    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3427
3428static void init_proc_401(CPUPPCState *env)
3429{
3430    gen_spr_40x(env);
3431    gen_spr_401_403(env);
3432    gen_spr_401(env);
3433    init_excp_4xx_real(env);
3434    env->dcache_line_size = 32;
3435    env->icache_line_size = 32;
3436    /* Allocate hardware IRQ controller */
3437    ppc40x_irq_init(env_archcpu(env));
3438
3439    SET_FIT_PERIOD(12, 16, 20, 24);
3440    SET_WDT_PERIOD(16, 20, 24, 28);
3441}
3442
3443POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3444{
3445    DeviceClass *dc = DEVICE_CLASS(oc);
3446    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3447
3448    dc->desc = "PowerPC 401";
3449    pcc->init_proc = init_proc_401;
3450    pcc->check_pow = check_pow_nocheck;
3451    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3452                       PPC_WRTEE | PPC_DCR |
3453                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3454                       PPC_CACHE_DCBZ |
3455                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3456                       PPC_4xx_COMMON | PPC_40x_EXCP;
3457    pcc->msr_mask = (1ull << MSR_KEY) |
3458                    (1ull << MSR_POW) |
3459                    (1ull << MSR_CE) |
3460                    (1ull << MSR_ILE) |
3461                    (1ull << MSR_EE) |
3462                    (1ull << MSR_PR) |
3463                    (1ull << MSR_ME) |
3464                    (1ull << MSR_DE) |
3465                    (1ull << MSR_LE);
3466    pcc->mmu_model = POWERPC_MMU_REAL;
3467    pcc->excp_model = POWERPC_EXCP_40x;
3468    pcc->bus_model = PPC_FLAGS_INPUT_401;
3469    pcc->bfd_mach = bfd_mach_ppc_403;
3470    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3471                 POWERPC_FLAG_BUS_CLK;
3472}
3473
3474static void init_proc_401x2(CPUPPCState *env)
3475{
3476    gen_spr_40x(env);
3477    gen_spr_401_403(env);
3478    gen_spr_401x2(env);
3479    gen_spr_compress(env);
3480    /* Memory management */
3481#if !defined(CONFIG_USER_ONLY)
3482    env->nb_tlb = 64;
3483    env->nb_ways = 1;
3484    env->id_tlbs = 0;
3485    env->tlb_type = TLB_EMB;
3486#endif
3487    init_excp_4xx_softmmu(env);
3488    env->dcache_line_size = 32;
3489    env->icache_line_size = 32;
3490    /* Allocate hardware IRQ controller */
3491    ppc40x_irq_init(env_archcpu(env));
3492
3493    SET_FIT_PERIOD(12, 16, 20, 24);
3494    SET_WDT_PERIOD(16, 20, 24, 28);
3495}
3496
3497POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3498{
3499    DeviceClass *dc = DEVICE_CLASS(oc);
3500    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3501
3502    dc->desc = "PowerPC 401x2";
3503    pcc->init_proc = init_proc_401x2;
3504    pcc->check_pow = check_pow_nocheck;
3505    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3506                       PPC_DCR | PPC_WRTEE |
3507                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3508                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3509                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3510                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3511                       PPC_4xx_COMMON | PPC_40x_EXCP;
3512    pcc->msr_mask = (1ull << 20) |
3513                    (1ull << MSR_KEY) |
3514                    (1ull << MSR_POW) |
3515                    (1ull << MSR_CE) |
3516                    (1ull << MSR_ILE) |
3517                    (1ull << MSR_EE) |
3518                    (1ull << MSR_PR) |
3519                    (1ull << MSR_ME) |
3520                    (1ull << MSR_DE) |
3521                    (1ull << MSR_IR) |
3522                    (1ull << MSR_DR) |
3523                    (1ull << MSR_LE);
3524    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3525    pcc->excp_model = POWERPC_EXCP_40x;
3526    pcc->bus_model = PPC_FLAGS_INPUT_401;
3527    pcc->bfd_mach = bfd_mach_ppc_403;
3528    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3529                 POWERPC_FLAG_BUS_CLK;
3530}
3531
3532static void init_proc_401x3(CPUPPCState *env)
3533{
3534    gen_spr_40x(env);
3535    gen_spr_401_403(env);
3536    gen_spr_401(env);
3537    gen_spr_401x2(env);
3538    gen_spr_compress(env);
3539    init_excp_4xx_softmmu(env);
3540    env->dcache_line_size = 32;
3541    env->icache_line_size = 32;
3542    /* Allocate hardware IRQ controller */
3543    ppc40x_irq_init(env_archcpu(env));
3544
3545    SET_FIT_PERIOD(12, 16, 20, 24);
3546    SET_WDT_PERIOD(16, 20, 24, 28);
3547}
3548
3549POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3550{
3551    DeviceClass *dc = DEVICE_CLASS(oc);
3552    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3553
3554    dc->desc = "PowerPC 401x3";
3555    pcc->init_proc = init_proc_401x3;
3556    pcc->check_pow = check_pow_nocheck;
3557    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3558                       PPC_DCR | PPC_WRTEE |
3559                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3560                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3561                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3562                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3563                       PPC_4xx_COMMON | PPC_40x_EXCP;
3564    pcc->msr_mask = (1ull << 20) |
3565                    (1ull << MSR_KEY) |
3566                    (1ull << MSR_POW) |
3567                    (1ull << MSR_CE) |
3568                    (1ull << MSR_ILE) |
3569                    (1ull << MSR_EE) |
3570                    (1ull << MSR_PR) |
3571                    (1ull << MSR_ME) |
3572                    (1ull << MSR_DWE) |
3573                    (1ull << MSR_DE) |
3574                    (1ull << MSR_IR) |
3575                    (1ull << MSR_DR) |
3576                    (1ull << MSR_LE);
3577    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3578    pcc->excp_model = POWERPC_EXCP_40x;
3579    pcc->bus_model = PPC_FLAGS_INPUT_401;
3580    pcc->bfd_mach = bfd_mach_ppc_403;
3581    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3582                 POWERPC_FLAG_BUS_CLK;
3583}
3584
3585static void init_proc_IOP480(CPUPPCState *env)
3586{
3587    gen_spr_40x(env);
3588    gen_spr_401_403(env);
3589    gen_spr_401x2(env);
3590    gen_spr_compress(env);
3591    /* Memory management */
3592#if !defined(CONFIG_USER_ONLY)
3593    env->nb_tlb = 64;
3594    env->nb_ways = 1;
3595    env->id_tlbs = 0;
3596    env->tlb_type = TLB_EMB;
3597#endif
3598    init_excp_4xx_softmmu(env);
3599    env->dcache_line_size = 32;
3600    env->icache_line_size = 32;
3601    /* Allocate hardware IRQ controller */
3602    ppc40x_irq_init(env_archcpu(env));
3603
3604    SET_FIT_PERIOD(8, 12, 16, 20);
3605    SET_WDT_PERIOD(16, 20, 24, 28);
3606}
3607
3608POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3609{
3610    DeviceClass *dc = DEVICE_CLASS(oc);
3611    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3612
3613    dc->desc = "IOP480";
3614    pcc->init_proc = init_proc_IOP480;
3615    pcc->check_pow = check_pow_nocheck;
3616    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3617                       PPC_DCR | PPC_WRTEE |
3618                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3619                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3620                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3621                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3622                       PPC_4xx_COMMON | PPC_40x_EXCP;
3623    pcc->msr_mask = (1ull << 20) |
3624                    (1ull << MSR_KEY) |
3625                    (1ull << MSR_POW) |
3626                    (1ull << MSR_CE) |
3627                    (1ull << MSR_ILE) |
3628                    (1ull << MSR_EE) |
3629                    (1ull << MSR_PR) |
3630                    (1ull << MSR_ME) |
3631                    (1ull << MSR_DE) |
3632                    (1ull << MSR_IR) |
3633                    (1ull << MSR_DR) |
3634                    (1ull << MSR_LE);
3635    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3636    pcc->excp_model = POWERPC_EXCP_40x;
3637    pcc->bus_model = PPC_FLAGS_INPUT_401;
3638    pcc->bfd_mach = bfd_mach_ppc_403;
3639    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3640                 POWERPC_FLAG_BUS_CLK;
3641}
3642
3643static void init_proc_403(CPUPPCState *env)
3644{
3645    gen_spr_40x(env);
3646    gen_spr_401_403(env);
3647    gen_spr_403(env);
3648    gen_spr_403_real(env);
3649    init_excp_4xx_real(env);
3650    env->dcache_line_size = 32;
3651    env->icache_line_size = 32;
3652    /* Allocate hardware IRQ controller */
3653    ppc40x_irq_init(env_archcpu(env));
3654
3655    SET_FIT_PERIOD(8, 12, 16, 20);
3656    SET_WDT_PERIOD(16, 20, 24, 28);
3657}
3658
3659POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3660{
3661    DeviceClass *dc = DEVICE_CLASS(oc);
3662    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3663
3664    dc->desc = "PowerPC 403";
3665    pcc->init_proc = init_proc_403;
3666    pcc->check_pow = check_pow_nocheck;
3667    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3668                       PPC_DCR | PPC_WRTEE |
3669                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3670                       PPC_CACHE_DCBZ |
3671                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3672                       PPC_4xx_COMMON | PPC_40x_EXCP;
3673    pcc->msr_mask = (1ull << MSR_POW) |
3674                    (1ull << MSR_CE) |
3675                    (1ull << MSR_ILE) |
3676                    (1ull << MSR_EE) |
3677                    (1ull << MSR_PR) |
3678                    (1ull << MSR_ME) |
3679                    (1ull << MSR_PE) |
3680                    (1ull << MSR_PX) |
3681                    (1ull << MSR_LE);
3682    pcc->mmu_model = POWERPC_MMU_REAL;
3683    pcc->excp_model = POWERPC_EXCP_40x;
3684    pcc->bus_model = PPC_FLAGS_INPUT_401;
3685    pcc->bfd_mach = bfd_mach_ppc_403;
3686    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3687                 POWERPC_FLAG_BUS_CLK;
3688}
3689
3690static void init_proc_403GCX(CPUPPCState *env)
3691{
3692    gen_spr_40x(env);
3693    gen_spr_401_403(env);
3694    gen_spr_403(env);
3695    gen_spr_403_real(env);
3696    gen_spr_403_mmu(env);
3697    /* Bus access control */
3698    /* not emulated, as QEMU never does speculative access */
3699    spr_register(env, SPR_40x_SGR, "SGR",
3700                 SPR_NOACCESS, SPR_NOACCESS,
3701                 &spr_read_generic, &spr_write_generic,
3702                 0xFFFFFFFF);
3703    /* not emulated, as QEMU do not emulate caches */
3704    spr_register(env, SPR_40x_DCWR, "DCWR",
3705                 SPR_NOACCESS, SPR_NOACCESS,
3706                 &spr_read_generic, &spr_write_generic,
3707                 0x00000000);
3708    /* Memory management */
3709#if !defined(CONFIG_USER_ONLY)
3710    env->nb_tlb = 64;
3711    env->nb_ways = 1;
3712    env->id_tlbs = 0;
3713    env->tlb_type = TLB_EMB;
3714#endif
3715    init_excp_4xx_softmmu(env);
3716    env->dcache_line_size = 32;
3717    env->icache_line_size = 32;
3718    /* Allocate hardware IRQ controller */
3719    ppc40x_irq_init(env_archcpu(env));
3720
3721    SET_FIT_PERIOD(8, 12, 16, 20);
3722    SET_WDT_PERIOD(16, 20, 24, 28);
3723}
3724
3725POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3726{
3727    DeviceClass *dc = DEVICE_CLASS(oc);
3728    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3729
3730    dc->desc = "PowerPC 403 GCX";
3731    pcc->init_proc = init_proc_403GCX;
3732    pcc->check_pow = check_pow_nocheck;
3733    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3734                       PPC_DCR | PPC_WRTEE |
3735                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3736                       PPC_CACHE_DCBZ |
3737                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3738                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3739                       PPC_4xx_COMMON | PPC_40x_EXCP;
3740    pcc->msr_mask = (1ull << MSR_POW) |
3741                    (1ull << MSR_CE) |
3742                    (1ull << MSR_ILE) |
3743                    (1ull << MSR_EE) |
3744                    (1ull << MSR_PR) |
3745                    (1ull << MSR_ME) |
3746                    (1ull << MSR_PE) |
3747                    (1ull << MSR_PX) |
3748                    (1ull << MSR_LE);
3749    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3750    pcc->excp_model = POWERPC_EXCP_40x;
3751    pcc->bus_model = PPC_FLAGS_INPUT_401;
3752    pcc->bfd_mach = bfd_mach_ppc_403;
3753    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3754                 POWERPC_FLAG_BUS_CLK;
3755}
3756
3757static void init_proc_405(CPUPPCState *env)
3758{
3759    /* Time base */
3760    gen_tbl(env);
3761    gen_spr_40x(env);
3762    gen_spr_405(env);
3763    /* Bus access control */
3764    /* not emulated, as QEMU never does speculative access */
3765    spr_register(env, SPR_40x_SGR, "SGR",
3766                 SPR_NOACCESS, SPR_NOACCESS,
3767                 &spr_read_generic, &spr_write_generic,
3768                 0xFFFFFFFF);
3769    /* not emulated, as QEMU do not emulate caches */
3770    spr_register(env, SPR_40x_DCWR, "DCWR",
3771                 SPR_NOACCESS, SPR_NOACCESS,
3772                 &spr_read_generic, &spr_write_generic,
3773                 0x00000000);
3774    /* Memory management */
3775#if !defined(CONFIG_USER_ONLY)
3776    env->nb_tlb = 64;
3777    env->nb_ways = 1;
3778    env->id_tlbs = 0;
3779    env->tlb_type = TLB_EMB;
3780#endif
3781    init_excp_4xx_softmmu(env);
3782    env->dcache_line_size = 32;
3783    env->icache_line_size = 32;
3784    /* Allocate hardware IRQ controller */
3785    ppc40x_irq_init(env_archcpu(env));
3786
3787    SET_FIT_PERIOD(8, 12, 16, 20);
3788    SET_WDT_PERIOD(16, 20, 24, 28);
3789}
3790
3791POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3792{
3793    DeviceClass *dc = DEVICE_CLASS(oc);
3794    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3795
3796    dc->desc = "PowerPC 405";
3797    pcc->init_proc = init_proc_405;
3798    pcc->check_pow = check_pow_nocheck;
3799    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3800                       PPC_DCR | PPC_WRTEE |
3801                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3802                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3803                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3804                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3805                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3806    pcc->msr_mask = (1ull << MSR_POW) |
3807                    (1ull << MSR_CE) |
3808                    (1ull << MSR_EE) |
3809                    (1ull << MSR_PR) |
3810                    (1ull << MSR_FP) |
3811                    (1ull << MSR_DWE) |
3812                    (1ull << MSR_DE) |
3813                    (1ull << MSR_IR) |
3814                    (1ull << MSR_DR);
3815    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3816    pcc->excp_model = POWERPC_EXCP_40x;
3817    pcc->bus_model = PPC_FLAGS_INPUT_405;
3818    pcc->bfd_mach = bfd_mach_ppc_403;
3819    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3820                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3821}
3822
3823static void init_proc_440EP(CPUPPCState *env)
3824{
3825    /* Time base */
3826    gen_tbl(env);
3827    gen_spr_BookE(env, 0x000000000000FFFFULL);
3828    gen_spr_440(env);
3829    gen_spr_usprgh(env);
3830    /* Processor identification */
3831    spr_register(env, SPR_BOOKE_PIR, "PIR",
3832                 SPR_NOACCESS, SPR_NOACCESS,
3833                 &spr_read_generic, &spr_write_pir,
3834                 0x00000000);
3835    /* XXX : not implemented */
3836    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3837                 SPR_NOACCESS, SPR_NOACCESS,
3838                 &spr_read_generic, &spr_write_generic,
3839                 0x00000000);
3840    /* XXX : not implemented */
3841    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3842                 SPR_NOACCESS, SPR_NOACCESS,
3843                 &spr_read_generic, &spr_write_generic,
3844                 0x00000000);
3845    /* XXX : not implemented */
3846    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3847                 SPR_NOACCESS, SPR_NOACCESS,
3848                 &spr_read_generic, &spr_write_generic,
3849                 0x00000000);
3850    /* XXX : not implemented */
3851    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3852                 SPR_NOACCESS, SPR_NOACCESS,
3853                 &spr_read_generic, &spr_write_generic,
3854                 0x00000000);
3855    /* XXX : not implemented */
3856    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3857                 SPR_NOACCESS, SPR_NOACCESS,
3858                 &spr_read_generic, &spr_write_generic,
3859                 0x00000000);
3860    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3861                 SPR_NOACCESS, SPR_NOACCESS,
3862                 &spr_read_generic, &spr_write_generic,
3863                 0x00000000);
3864    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3865                 SPR_NOACCESS, SPR_NOACCESS,
3866                 &spr_read_generic, &spr_write_generic,
3867                 0x00000000);
3868    /* XXX : not implemented */
3869    spr_register(env, SPR_440_CCR1, "CCR1",
3870                 SPR_NOACCESS, SPR_NOACCESS,
3871                 &spr_read_generic, &spr_write_generic,
3872                 0x00000000);
3873    /* Memory management */
3874#if !defined(CONFIG_USER_ONLY)
3875    env->nb_tlb = 64;
3876    env->nb_ways = 1;
3877    env->id_tlbs = 0;
3878    env->tlb_type = TLB_EMB;
3879#endif
3880    init_excp_BookE(env);
3881    env->dcache_line_size = 32;
3882    env->icache_line_size = 32;
3883    ppc40x_irq_init(env_archcpu(env));
3884
3885    SET_FIT_PERIOD(12, 16, 20, 24);
3886    SET_WDT_PERIOD(20, 24, 28, 32);
3887}
3888
3889POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3890{
3891    DeviceClass *dc = DEVICE_CLASS(oc);
3892    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3893
3894    dc->desc = "PowerPC 440 EP";
3895    pcc->init_proc = init_proc_440EP;
3896    pcc->check_pow = check_pow_nocheck;
3897    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3898                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3899                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3900                       PPC_FLOAT_STFIWX |
3901                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3902                       PPC_CACHE | PPC_CACHE_ICBI |
3903                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3904                       PPC_MEM_TLBSYNC | PPC_MFTB |
3905                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3906                       PPC_440_SPEC;
3907    pcc->msr_mask = (1ull << MSR_POW) |
3908                    (1ull << MSR_CE) |
3909                    (1ull << MSR_EE) |
3910                    (1ull << MSR_PR) |
3911                    (1ull << MSR_FP) |
3912                    (1ull << MSR_ME) |
3913                    (1ull << MSR_FE0) |
3914                    (1ull << MSR_DWE) |
3915                    (1ull << MSR_DE) |
3916                    (1ull << MSR_FE1) |
3917                    (1ull << MSR_IR) |
3918                    (1ull << MSR_DR);
3919    pcc->mmu_model = POWERPC_MMU_BOOKE;
3920    pcc->excp_model = POWERPC_EXCP_BOOKE;
3921    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3922    pcc->bfd_mach = bfd_mach_ppc_403;
3923    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3924                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3925}
3926
3927POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3928{
3929    DeviceClass *dc = DEVICE_CLASS(oc);
3930    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3931
3932    dc->desc = "PowerPC 460 EX";
3933    pcc->init_proc = init_proc_440EP;
3934    pcc->check_pow = check_pow_nocheck;
3935    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3936                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3937                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3938                       PPC_FLOAT_STFIWX |
3939                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3940                       PPC_CACHE | PPC_CACHE_ICBI |
3941                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3942                       PPC_MEM_TLBSYNC | PPC_MFTB |
3943                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3944                       PPC_440_SPEC;
3945    pcc->msr_mask = (1ull << MSR_POW) |
3946                    (1ull << MSR_CE) |
3947                    (1ull << MSR_EE) |
3948                    (1ull << MSR_PR) |
3949                    (1ull << MSR_FP) |
3950                    (1ull << MSR_ME) |
3951                    (1ull << MSR_FE0) |
3952                    (1ull << MSR_DWE) |
3953                    (1ull << MSR_DE) |
3954                    (1ull << MSR_FE1) |
3955                    (1ull << MSR_IR) |
3956                    (1ull << MSR_DR);
3957    pcc->mmu_model = POWERPC_MMU_BOOKE;
3958    pcc->excp_model = POWERPC_EXCP_BOOKE;
3959    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3960    pcc->bfd_mach = bfd_mach_ppc_403;
3961    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3962                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3963}
3964
3965static void init_proc_440GP(CPUPPCState *env)
3966{
3967    /* Time base */
3968    gen_tbl(env);
3969    gen_spr_BookE(env, 0x000000000000FFFFULL);
3970    gen_spr_440(env);
3971    gen_spr_usprgh(env);
3972    /* Processor identification */
3973    spr_register(env, SPR_BOOKE_PIR, "PIR",
3974                 SPR_NOACCESS, SPR_NOACCESS,
3975                 &spr_read_generic, &spr_write_pir,
3976                 0x00000000);
3977    /* XXX : not implemented */
3978    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3979                 SPR_NOACCESS, SPR_NOACCESS,
3980                 &spr_read_generic, &spr_write_generic,
3981                 0x00000000);
3982    /* XXX : not implemented */
3983    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3984                 SPR_NOACCESS, SPR_NOACCESS,
3985                 &spr_read_generic, &spr_write_generic,
3986                 0x00000000);
3987    /* XXX : not implemented */
3988    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3989                 SPR_NOACCESS, SPR_NOACCESS,
3990                 &spr_read_generic, &spr_write_generic,
3991                 0x00000000);
3992    /* XXX : not implemented */
3993    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3994                 SPR_NOACCESS, SPR_NOACCESS,
3995                 &spr_read_generic, &spr_write_generic,
3996                 0x00000000);
3997    /* Memory management */
3998#if !defined(CONFIG_USER_ONLY)
3999    env->nb_tlb = 64;
4000    env->nb_ways = 1;
4001    env->id_tlbs = 0;
4002    env->tlb_type = TLB_EMB;
4003#endif
4004    init_excp_BookE(env);
4005    env->dcache_line_size = 32;
4006    env->icache_line_size = 32;
4007    /* XXX: TODO: allocate internal IRQ controller */
4008
4009    SET_FIT_PERIOD(12, 16, 20, 24);
4010    SET_WDT_PERIOD(20, 24, 28, 32);
4011}
4012
4013POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
4014{
4015    DeviceClass *dc = DEVICE_CLASS(oc);
4016    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4017
4018    dc->desc = "PowerPC 440 GP";
4019    pcc->init_proc = init_proc_440GP;
4020    pcc->check_pow = check_pow_nocheck;
4021    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4022                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
4023                       PPC_CACHE | PPC_CACHE_ICBI |
4024                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4025                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
4026                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4027                       PPC_440_SPEC;
4028    pcc->msr_mask = (1ull << MSR_POW) |
4029                    (1ull << MSR_CE) |
4030                    (1ull << MSR_EE) |
4031                    (1ull << MSR_PR) |
4032                    (1ull << MSR_FP) |
4033                    (1ull << MSR_ME) |
4034                    (1ull << MSR_FE0) |
4035                    (1ull << MSR_DWE) |
4036                    (1ull << MSR_DE) |
4037                    (1ull << MSR_FE1) |
4038                    (1ull << MSR_IR) |
4039                    (1ull << MSR_DR);
4040    pcc->mmu_model = POWERPC_MMU_BOOKE;
4041    pcc->excp_model = POWERPC_EXCP_BOOKE;
4042    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4043    pcc->bfd_mach = bfd_mach_ppc_403;
4044    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4045                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4046}
4047
4048static void init_proc_440x4(CPUPPCState *env)
4049{
4050    /* Time base */
4051    gen_tbl(env);
4052    gen_spr_BookE(env, 0x000000000000FFFFULL);
4053    gen_spr_440(env);
4054    gen_spr_usprgh(env);
4055    /* Processor identification */
4056    spr_register(env, SPR_BOOKE_PIR, "PIR",
4057                 SPR_NOACCESS, SPR_NOACCESS,
4058                 &spr_read_generic, &spr_write_pir,
4059                 0x00000000);
4060    /* XXX : not implemented */
4061    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4062                 SPR_NOACCESS, SPR_NOACCESS,
4063                 &spr_read_generic, &spr_write_generic,
4064                 0x00000000);
4065    /* XXX : not implemented */
4066    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4067                 SPR_NOACCESS, SPR_NOACCESS,
4068                 &spr_read_generic, &spr_write_generic,
4069                 0x00000000);
4070    /* XXX : not implemented */
4071    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4072                 SPR_NOACCESS, SPR_NOACCESS,
4073                 &spr_read_generic, &spr_write_generic,
4074                 0x00000000);
4075    /* XXX : not implemented */
4076    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4077                 SPR_NOACCESS, SPR_NOACCESS,
4078                 &spr_read_generic, &spr_write_generic,
4079                 0x00000000);
4080    /* Memory management */
4081#if !defined(CONFIG_USER_ONLY)
4082    env->nb_tlb = 64;
4083    env->nb_ways = 1;
4084    env->id_tlbs = 0;
4085    env->tlb_type = TLB_EMB;
4086#endif
4087    init_excp_BookE(env);
4088    env->dcache_line_size = 32;
4089    env->icache_line_size = 32;
4090    /* XXX: TODO: allocate internal IRQ controller */
4091
4092    SET_FIT_PERIOD(12, 16, 20, 24);
4093    SET_WDT_PERIOD(20, 24, 28, 32);
4094}
4095
4096POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4097{
4098    DeviceClass *dc = DEVICE_CLASS(oc);
4099    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4100
4101    dc->desc = "PowerPC 440x4";
4102    pcc->init_proc = init_proc_440x4;
4103    pcc->check_pow = check_pow_nocheck;
4104    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4105                       PPC_DCR | PPC_WRTEE |
4106                       PPC_CACHE | PPC_CACHE_ICBI |
4107                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4108                       PPC_MEM_TLBSYNC | PPC_MFTB |
4109                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4110                       PPC_440_SPEC;
4111    pcc->msr_mask = (1ull << MSR_POW) |
4112                    (1ull << MSR_CE) |
4113                    (1ull << MSR_EE) |
4114                    (1ull << MSR_PR) |
4115                    (1ull << MSR_FP) |
4116                    (1ull << MSR_ME) |
4117                    (1ull << MSR_FE0) |
4118                    (1ull << MSR_DWE) |
4119                    (1ull << MSR_DE) |
4120                    (1ull << MSR_FE1) |
4121                    (1ull << MSR_IR) |
4122                    (1ull << MSR_DR);
4123    pcc->mmu_model = POWERPC_MMU_BOOKE;
4124    pcc->excp_model = POWERPC_EXCP_BOOKE;
4125    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4126    pcc->bfd_mach = bfd_mach_ppc_403;
4127    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4128                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4129}
4130
4131static void init_proc_440x5(CPUPPCState *env)
4132{
4133    /* Time base */
4134    gen_tbl(env);
4135    gen_spr_BookE(env, 0x000000000000FFFFULL);
4136    gen_spr_440(env);
4137    gen_spr_usprgh(env);
4138    /* Processor identification */
4139    spr_register(env, SPR_BOOKE_PIR, "PIR",
4140                 SPR_NOACCESS, SPR_NOACCESS,
4141                 &spr_read_generic, &spr_write_pir,
4142                 0x00000000);
4143    /* XXX : not implemented */
4144    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4145                 SPR_NOACCESS, SPR_NOACCESS,
4146                 &spr_read_generic, &spr_write_generic,
4147                 0x00000000);
4148    /* XXX : not implemented */
4149    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4150                 SPR_NOACCESS, SPR_NOACCESS,
4151                 &spr_read_generic, &spr_write_generic,
4152                 0x00000000);
4153    /* XXX : not implemented */
4154    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4155                 SPR_NOACCESS, SPR_NOACCESS,
4156                 &spr_read_generic, &spr_write_generic,
4157                 0x00000000);
4158    /* XXX : not implemented */
4159    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4160                 SPR_NOACCESS, SPR_NOACCESS,
4161                 &spr_read_generic, &spr_write_generic,
4162                 0x00000000);
4163    /* XXX : not implemented */
4164    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4165                 SPR_NOACCESS, SPR_NOACCESS,
4166                 &spr_read_generic, &spr_write_generic,
4167                 0x00000000);
4168    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4169                 SPR_NOACCESS, SPR_NOACCESS,
4170                 &spr_read_generic, &spr_write_generic,
4171                 0x00000000);
4172    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4173                 SPR_NOACCESS, SPR_NOACCESS,
4174                 &spr_read_generic, &spr_write_generic,
4175                 0x00000000);
4176    /* XXX : not implemented */
4177    spr_register(env, SPR_440_CCR1, "CCR1",
4178                 SPR_NOACCESS, SPR_NOACCESS,
4179                 &spr_read_generic, &spr_write_generic,
4180                 0x00000000);
4181    /* Memory management */
4182#if !defined(CONFIG_USER_ONLY)
4183    env->nb_tlb = 64;
4184    env->nb_ways = 1;
4185    env->id_tlbs = 0;
4186    env->tlb_type = TLB_EMB;
4187#endif
4188    init_excp_BookE(env);
4189    env->dcache_line_size = 32;
4190    env->icache_line_size = 32;
4191    ppc40x_irq_init(env_archcpu(env));
4192
4193    SET_FIT_PERIOD(12, 16, 20, 24);
4194    SET_WDT_PERIOD(20, 24, 28, 32);
4195}
4196
4197POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4198{
4199    DeviceClass *dc = DEVICE_CLASS(oc);
4200    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4201
4202    dc->desc = "PowerPC 440x5";
4203    pcc->init_proc = init_proc_440x5;
4204    pcc->check_pow = check_pow_nocheck;
4205    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4206                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4207                       PPC_CACHE | PPC_CACHE_ICBI |
4208                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4209                       PPC_MEM_TLBSYNC | PPC_MFTB |
4210                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4211                       PPC_440_SPEC;
4212    pcc->msr_mask = (1ull << MSR_POW) |
4213                    (1ull << MSR_CE) |
4214                    (1ull << MSR_EE) |
4215                    (1ull << MSR_PR) |
4216                    (1ull << MSR_FP) |
4217                    (1ull << MSR_ME) |
4218                    (1ull << MSR_FE0) |
4219                    (1ull << MSR_DWE) |
4220                    (1ull << MSR_DE) |
4221                    (1ull << MSR_FE1) |
4222                    (1ull << MSR_IR) |
4223                    (1ull << MSR_DR);
4224    pcc->mmu_model = POWERPC_MMU_BOOKE;
4225    pcc->excp_model = POWERPC_EXCP_BOOKE;
4226    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4227    pcc->bfd_mach = bfd_mach_ppc_403;
4228    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4229                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4230}
4231
4232POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4233{
4234    DeviceClass *dc = DEVICE_CLASS(oc);
4235    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4236
4237    dc->desc = "PowerPC 440x5 with double precision FPU";
4238    pcc->init_proc = init_proc_440x5;
4239    pcc->check_pow = check_pow_nocheck;
4240    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4241                       PPC_FLOAT | PPC_FLOAT_FSQRT |
4242                       PPC_FLOAT_STFIWX |
4243                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4244                       PPC_CACHE | PPC_CACHE_ICBI |
4245                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4246                       PPC_MEM_TLBSYNC | PPC_MFTB |
4247                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4248                       PPC_440_SPEC;
4249    pcc->insns_flags2 = PPC2_FP_CVT_S64;
4250    pcc->msr_mask = (1ull << MSR_POW) |
4251                    (1ull << MSR_CE) |
4252                    (1ull << MSR_EE) |
4253                    (1ull << MSR_PR) |
4254                    (1ull << MSR_FP) |
4255                    (1ull << MSR_ME) |
4256                    (1ull << MSR_FE0) |
4257                    (1ull << MSR_DWE) |
4258                    (1ull << MSR_DE) |
4259                    (1ull << MSR_FE1) |
4260                    (1ull << MSR_IR) |
4261                    (1ull << MSR_DR);
4262    pcc->mmu_model = POWERPC_MMU_BOOKE;
4263    pcc->excp_model = POWERPC_EXCP_BOOKE;
4264    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4265    pcc->bfd_mach = bfd_mach_ppc_403;
4266    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4267                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4268}
4269
4270static void init_proc_MPC5xx(CPUPPCState *env)
4271{
4272    /* Time base */
4273    gen_tbl(env);
4274    gen_spr_5xx_8xx(env);
4275    gen_spr_5xx(env);
4276    init_excp_MPC5xx(env);
4277    env->dcache_line_size = 32;
4278    env->icache_line_size = 32;
4279    /* XXX: TODO: allocate internal IRQ controller */
4280}
4281
4282POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4283{
4284    DeviceClass *dc = DEVICE_CLASS(oc);
4285    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4286
4287    dc->desc = "Freescale 5xx cores (aka RCPU)";
4288    pcc->init_proc = init_proc_MPC5xx;
4289    pcc->check_pow = check_pow_none;
4290    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4291                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4292                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4293                       PPC_MFTB;
4294    pcc->msr_mask = (1ull << MSR_ILE) |
4295                    (1ull << MSR_EE) |
4296                    (1ull << MSR_PR) |
4297                    (1ull << MSR_FP) |
4298                    (1ull << MSR_ME) |
4299                    (1ull << MSR_FE0) |
4300                    (1ull << MSR_SE) |
4301                    (1ull << MSR_DE) |
4302                    (1ull << MSR_FE1) |
4303                    (1ull << MSR_EP) |
4304                    (1ull << MSR_RI) |
4305                    (1ull << MSR_LE);
4306    pcc->mmu_model = POWERPC_MMU_REAL;
4307    pcc->excp_model = POWERPC_EXCP_603;
4308    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4309    pcc->bfd_mach = bfd_mach_ppc_505;
4310    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4311                 POWERPC_FLAG_BUS_CLK;
4312}
4313
4314static void init_proc_MPC8xx(CPUPPCState *env)
4315{
4316    /* Time base */
4317    gen_tbl(env);
4318    gen_spr_5xx_8xx(env);
4319    gen_spr_8xx(env);
4320    init_excp_MPC8xx(env);
4321    env->dcache_line_size = 32;
4322    env->icache_line_size = 32;
4323    /* XXX: TODO: allocate internal IRQ controller */
4324}
4325
4326POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4327{
4328    DeviceClass *dc = DEVICE_CLASS(oc);
4329    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4330
4331    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4332    pcc->init_proc = init_proc_MPC8xx;
4333    pcc->check_pow = check_pow_none;
4334    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4335                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4336                       PPC_CACHE_ICBI | PPC_MFTB;
4337    pcc->msr_mask = (1ull << MSR_ILE) |
4338                    (1ull << MSR_EE) |
4339                    (1ull << MSR_PR) |
4340                    (1ull << MSR_FP) |
4341                    (1ull << MSR_ME) |
4342                    (1ull << MSR_SE) |
4343                    (1ull << MSR_DE) |
4344                    (1ull << MSR_EP) |
4345                    (1ull << MSR_IR) |
4346                    (1ull << MSR_DR) |
4347                    (1ull << MSR_RI) |
4348                    (1ull << MSR_LE);
4349    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4350    pcc->excp_model = POWERPC_EXCP_603;
4351    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4352    pcc->bfd_mach = bfd_mach_ppc_860;
4353    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4354                 POWERPC_FLAG_BUS_CLK;
4355}
4356
4357/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4358
4359static void init_proc_G2(CPUPPCState *env)
4360{
4361    gen_spr_ne_601(env);
4362    gen_spr_sdr1(env);
4363    gen_spr_G2_755(env);
4364    gen_spr_G2(env);
4365    /* Time base */
4366    gen_tbl(env);
4367    /* External access control */
4368    /* XXX : not implemented */
4369    spr_register(env, SPR_EAR, "EAR",
4370                 SPR_NOACCESS, SPR_NOACCESS,
4371                 &spr_read_generic, &spr_write_generic,
4372                 0x00000000);
4373    /* Hardware implementation register */
4374    /* XXX : not implemented */
4375    spr_register(env, SPR_HID0, "HID0",
4376                 SPR_NOACCESS, SPR_NOACCESS,
4377                 &spr_read_generic, &spr_write_generic,
4378                 0x00000000);
4379    /* XXX : not implemented */
4380    spr_register(env, SPR_HID1, "HID1",
4381                 SPR_NOACCESS, SPR_NOACCESS,
4382                 &spr_read_generic, &spr_write_generic,
4383                 0x00000000);
4384    /* XXX : not implemented */
4385    spr_register(env, SPR_HID2, "HID2",
4386                 SPR_NOACCESS, SPR_NOACCESS,
4387                 &spr_read_generic, &spr_write_generic,
4388                 0x00000000);
4389    /* Memory management */
4390    gen_low_BATs(env);
4391    gen_high_BATs(env);
4392    gen_6xx_7xx_soft_tlb(env, 64, 2);
4393    init_excp_G2(env);
4394    env->dcache_line_size = 32;
4395    env->icache_line_size = 32;
4396    /* Allocate hardware IRQ controller */
4397    ppc6xx_irq_init(env_archcpu(env));
4398}
4399
4400POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4401{
4402    DeviceClass *dc = DEVICE_CLASS(oc);
4403    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4404
4405    dc->desc = "PowerPC G2";
4406    pcc->init_proc = init_proc_G2;
4407    pcc->check_pow = check_pow_hid0;
4408    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4409                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4410                       PPC_FLOAT_STFIWX |
4411                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4412                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4413                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4414                       PPC_SEGMENT | PPC_EXTERN;
4415    pcc->msr_mask = (1ull << MSR_POW) |
4416                    (1ull << MSR_TGPR) |
4417                    (1ull << MSR_EE) |
4418                    (1ull << MSR_PR) |
4419                    (1ull << MSR_FP) |
4420                    (1ull << MSR_ME) |
4421                    (1ull << MSR_FE0) |
4422                    (1ull << MSR_SE) |
4423                    (1ull << MSR_DE) |
4424                    (1ull << MSR_FE1) |
4425                    (1ull << MSR_AL) |
4426                    (1ull << MSR_EP) |
4427                    (1ull << MSR_IR) |
4428                    (1ull << MSR_DR) |
4429                    (1ull << MSR_RI);
4430    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4431    pcc->excp_model = POWERPC_EXCP_G2;
4432    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4433    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4434    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4435                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4436}
4437
4438static void init_proc_G2LE(CPUPPCState *env)
4439{
4440    gen_spr_ne_601(env);
4441    gen_spr_sdr1(env);
4442    gen_spr_G2_755(env);
4443    gen_spr_G2(env);
4444    /* Time base */
4445    gen_tbl(env);
4446    /* External access control */
4447    /* XXX : not implemented */
4448    spr_register(env, SPR_EAR, "EAR",
4449                 SPR_NOACCESS, SPR_NOACCESS,
4450                 &spr_read_generic, &spr_write_generic,
4451                 0x00000000);
4452    /* Hardware implementation register */
4453    /* XXX : not implemented */
4454    spr_register(env, SPR_HID0, "HID0",
4455                 SPR_NOACCESS, SPR_NOACCESS,
4456                 &spr_read_generic, &spr_write_generic,
4457                 0x00000000);
4458    /* XXX : not implemented */
4459    spr_register(env, SPR_HID1, "HID1",
4460                 SPR_NOACCESS, SPR_NOACCESS,
4461                 &spr_read_generic, &spr_write_generic,
4462                 0x00000000);
4463    /* XXX : not implemented */
4464    spr_register(env, SPR_HID2, "HID2",
4465                 SPR_NOACCESS, SPR_NOACCESS,
4466                 &spr_read_generic, &spr_write_generic,
4467                 0x00000000);
4468
4469    /* Memory management */
4470    gen_low_BATs(env);
4471    gen_high_BATs(env);
4472    gen_6xx_7xx_soft_tlb(env, 64, 2);
4473    init_excp_G2(env);
4474    env->dcache_line_size = 32;
4475    env->icache_line_size = 32;
4476    /* Allocate hardware IRQ controller */
4477    ppc6xx_irq_init(env_archcpu(env));
4478}
4479
4480POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4481{
4482    DeviceClass *dc = DEVICE_CLASS(oc);
4483    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4484
4485    dc->desc = "PowerPC G2LE";
4486    pcc->init_proc = init_proc_G2LE;
4487    pcc->check_pow = check_pow_hid0;
4488    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4489                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4490                       PPC_FLOAT_STFIWX |
4491                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4492                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4493                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4494                       PPC_SEGMENT | PPC_EXTERN;
4495    pcc->msr_mask = (1ull << MSR_POW) |
4496                    (1ull << MSR_TGPR) |
4497                    (1ull << MSR_ILE) |
4498                    (1ull << MSR_EE) |
4499                    (1ull << MSR_PR) |
4500                    (1ull << MSR_FP) |
4501                    (1ull << MSR_ME) |
4502                    (1ull << MSR_FE0) |
4503                    (1ull << MSR_SE) |
4504                    (1ull << MSR_DE) |
4505                    (1ull << MSR_FE1) |
4506                    (1ull << MSR_AL) |
4507                    (1ull << MSR_EP) |
4508                    (1ull << MSR_IR) |
4509                    (1ull << MSR_DR) |
4510                    (1ull << MSR_RI) |
4511                    (1ull << MSR_LE);
4512    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4513    pcc->excp_model = POWERPC_EXCP_G2;
4514    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4515    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4516    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4517                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4518}
4519
4520static void init_proc_e200(CPUPPCState *env)
4521{
4522    /* Time base */
4523    gen_tbl(env);
4524    gen_spr_BookE(env, 0x000000070000FFFFULL);
4525    /* XXX : not implemented */
4526    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4527                 &spr_read_spefscr, &spr_write_spefscr,
4528                 &spr_read_spefscr, &spr_write_spefscr,
4529                 0x00000000);
4530    /* Memory management */
4531    gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4532    /* XXX : not implemented */
4533    spr_register(env, SPR_HID0, "HID0",
4534                 SPR_NOACCESS, SPR_NOACCESS,
4535                 &spr_read_generic, &spr_write_generic,
4536                 0x00000000);
4537    /* XXX : not implemented */
4538    spr_register(env, SPR_HID1, "HID1",
4539                 SPR_NOACCESS, SPR_NOACCESS,
4540                 &spr_read_generic, &spr_write_generic,
4541                 0x00000000);
4542    /* XXX : not implemented */
4543    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4544                 SPR_NOACCESS, SPR_NOACCESS,
4545                 &spr_read_generic, &spr_write_generic,
4546                 0x00000000);
4547    /* XXX : not implemented */
4548    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4549                 SPR_NOACCESS, SPR_NOACCESS,
4550                 &spr_read_generic, &spr_write_generic,
4551                 0x00000000);
4552    /* XXX : not implemented */
4553    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4554                 SPR_NOACCESS, SPR_NOACCESS,
4555                 &spr_read_generic, &spr_write_generic,
4556                 0x00000000);
4557    /* XXX : not implemented */
4558    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4559                 SPR_NOACCESS, SPR_NOACCESS,
4560                 &spr_read_generic, &spr_write_generic,
4561                 0x00000000);
4562    /* XXX : not implemented */
4563    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4564                 SPR_NOACCESS, SPR_NOACCESS,
4565                 &spr_read_generic, &spr_write_generic,
4566                 0x00000000);
4567    /* XXX : not implemented */
4568    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4569                 &spr_read_generic, SPR_NOACCESS,
4570                 &spr_read_generic, SPR_NOACCESS,
4571                 0x00000000);
4572    /* XXX : not implemented */
4573    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4574                 SPR_NOACCESS, SPR_NOACCESS,
4575                 &spr_read_generic, &spr_write_generic,
4576                 0x00000000);
4577    /* XXX : not implemented */
4578    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4579                 SPR_NOACCESS, SPR_NOACCESS,
4580                 &spr_read_generic, &spr_write_generic,
4581                 0x00000000);
4582    /* XXX : not implemented */
4583    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4584                 SPR_NOACCESS, SPR_NOACCESS,
4585                 &spr_read_generic, &spr_write_generic,
4586                 0x00000000);
4587    /* XXX : not implemented */
4588    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4589                 SPR_NOACCESS, SPR_NOACCESS,
4590                 &spr_read_generic, &spr_write_generic,
4591                 0x00000000);
4592    /* XXX : not implemented */
4593    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4594                 SPR_NOACCESS, SPR_NOACCESS,
4595                 &spr_read_generic, &spr_write_generic,
4596                 0x00000000);
4597    /* XXX : not implemented */
4598    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4599                 SPR_NOACCESS, SPR_NOACCESS,
4600                 &spr_read_generic, &spr_write_generic,
4601                 0x00000000);
4602    /* XXX : not implemented */
4603    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4604                 SPR_NOACCESS, SPR_NOACCESS,
4605                 &spr_read_generic, &spr_write_generic,
4606                 0x00000000); /* TOFIX */
4607    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4608                 SPR_NOACCESS, SPR_NOACCESS,
4609                 &spr_read_generic, &spr_write_generic,
4610                 0x00000000);
4611    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4612                 SPR_NOACCESS, SPR_NOACCESS,
4613                 &spr_read_generic, &spr_write_generic,
4614                 0x00000000);
4615#if !defined(CONFIG_USER_ONLY)
4616    env->nb_tlb = 64;
4617    env->nb_ways = 1;
4618    env->id_tlbs = 0;
4619    env->tlb_type = TLB_EMB;
4620#endif
4621    init_excp_e200(env, 0xFFFF0000UL);
4622    env->dcache_line_size = 32;
4623    env->icache_line_size = 32;
4624    /* XXX: TODO: allocate internal IRQ controller */
4625}
4626
4627POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4628{
4629    DeviceClass *dc = DEVICE_CLASS(oc);
4630    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4631
4632    dc->desc = "e200 core";
4633    pcc->init_proc = init_proc_e200;
4634    pcc->check_pow = check_pow_hid0;
4635    /*
4636     * XXX: unimplemented instructions:
4637     * dcblc
4638     * dcbtlst
4639     * dcbtstls
4640     * icblc
4641     * icbtls
4642     * tlbivax
4643     * all SPE multiply-accumulate instructions
4644     */
4645    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4646                       PPC_SPE | PPC_SPE_SINGLE |
4647                       PPC_WRTEE | PPC_RFDI |
4648                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4649                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4650                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4651                       PPC_BOOKE;
4652    pcc->msr_mask = (1ull << MSR_UCLE) |
4653                    (1ull << MSR_SPE) |
4654                    (1ull << MSR_POW) |
4655                    (1ull << MSR_CE) |
4656                    (1ull << MSR_EE) |
4657                    (1ull << MSR_PR) |
4658                    (1ull << MSR_FP) |
4659                    (1ull << MSR_ME) |
4660                    (1ull << MSR_FE0) |
4661                    (1ull << MSR_DWE) |
4662                    (1ull << MSR_DE) |
4663                    (1ull << MSR_FE1) |
4664                    (1ull << MSR_IR) |
4665                    (1ull << MSR_DR);
4666    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4667    pcc->excp_model = POWERPC_EXCP_BOOKE;
4668    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4669    pcc->bfd_mach = bfd_mach_ppc_860;
4670    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4671                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4672                 POWERPC_FLAG_BUS_CLK;
4673}
4674
4675static void init_proc_e300(CPUPPCState *env)
4676{
4677    gen_spr_ne_601(env);
4678    gen_spr_sdr1(env);
4679    gen_spr_603(env);
4680    /* Time base */
4681    gen_tbl(env);
4682    /* hardware implementation registers */
4683    /* XXX : not implemented */
4684    spr_register(env, SPR_HID0, "HID0",
4685                 SPR_NOACCESS, SPR_NOACCESS,
4686                 &spr_read_generic, &spr_write_generic,
4687                 0x00000000);
4688    /* XXX : not implemented */
4689    spr_register(env, SPR_HID1, "HID1",
4690                 SPR_NOACCESS, SPR_NOACCESS,
4691                 &spr_read_generic, &spr_write_generic,
4692                 0x00000000);
4693    /* XXX : not implemented */
4694    spr_register(env, SPR_HID2, "HID2",
4695                 SPR_NOACCESS, SPR_NOACCESS,
4696                 &spr_read_generic, &spr_write_generic,
4697                 0x00000000);
4698    /* Breakpoints */
4699    /* XXX : not implemented */
4700    spr_register(env, SPR_DABR, "DABR",
4701                 SPR_NOACCESS, SPR_NOACCESS,
4702                 &spr_read_generic, &spr_write_generic,
4703                 0x00000000);
4704    /* XXX : not implemented */
4705    spr_register(env, SPR_DABR2, "DABR2",
4706                 SPR_NOACCESS, SPR_NOACCESS,
4707                 &spr_read_generic, &spr_write_generic,
4708                 0x00000000);
4709    /* XXX : not implemented */
4710    spr_register(env, SPR_IABR2, "IABR2",
4711                 SPR_NOACCESS, SPR_NOACCESS,
4712                 &spr_read_generic, &spr_write_generic,
4713                 0x00000000);
4714    /* XXX : not implemented */
4715    spr_register(env, SPR_IBCR, "IBCR",
4716                 SPR_NOACCESS, SPR_NOACCESS,
4717                 &spr_read_generic, &spr_write_generic,
4718                 0x00000000);
4719    /* XXX : not implemented */
4720    spr_register(env, SPR_DBCR, "DBCR",
4721                 SPR_NOACCESS, SPR_NOACCESS,
4722                 &spr_read_generic, &spr_write_generic,
4723                 0x00000000);
4724    /* Memory management */
4725    gen_low_BATs(env);
4726    gen_high_BATs(env);
4727    gen_6xx_7xx_soft_tlb(env, 64, 2);
4728    init_excp_603(env);
4729    env->dcache_line_size = 32;
4730    env->icache_line_size = 32;
4731    /* Allocate hardware IRQ controller */
4732    ppc6xx_irq_init(env_archcpu(env));
4733}
4734
4735POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4736{
4737    DeviceClass *dc = DEVICE_CLASS(oc);
4738    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4739
4740    dc->desc = "e300 core";
4741    pcc->init_proc = init_proc_e300;
4742    pcc->check_pow = check_pow_hid0;
4743    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4744                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4745                       PPC_FLOAT_STFIWX |
4746                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4747                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4748                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4749                       PPC_SEGMENT | PPC_EXTERN;
4750    pcc->msr_mask = (1ull << MSR_POW) |
4751                    (1ull << MSR_TGPR) |
4752                    (1ull << MSR_ILE) |
4753                    (1ull << MSR_EE) |
4754                    (1ull << MSR_PR) |
4755                    (1ull << MSR_FP) |
4756                    (1ull << MSR_ME) |
4757                    (1ull << MSR_FE0) |
4758                    (1ull << MSR_SE) |
4759                    (1ull << MSR_DE) |
4760                    (1ull << MSR_FE1) |
4761                    (1ull << MSR_AL) |
4762                    (1ull << MSR_EP) |
4763                    (1ull << MSR_IR) |
4764                    (1ull << MSR_DR) |
4765                    (1ull << MSR_RI) |
4766                    (1ull << MSR_LE);
4767    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4768    pcc->excp_model = POWERPC_EXCP_603;
4769    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4770    pcc->bfd_mach = bfd_mach_ppc_603;
4771    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4772                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4773}
4774
4775#if !defined(CONFIG_USER_ONLY)
4776static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4777{
4778    TCGv val = tcg_temp_new();
4779    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4780    gen_store_spr(SPR_BOOKE_MAS3, val);
4781    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4782    gen_store_spr(SPR_BOOKE_MAS7, val);
4783    tcg_temp_free(val);
4784}
4785
4786static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4787{
4788    TCGv mas7 = tcg_temp_new();
4789    TCGv mas3 = tcg_temp_new();
4790    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4791    tcg_gen_shli_tl(mas7, mas7, 32);
4792    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4793    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4794    tcg_temp_free(mas3);
4795    tcg_temp_free(mas7);
4796}
4797
4798#endif
4799
4800enum fsl_e500_version {
4801    fsl_e500v1,
4802    fsl_e500v2,
4803    fsl_e500mc,
4804    fsl_e5500,
4805    fsl_e6500,
4806};
4807
4808static void init_proc_e500(CPUPPCState *env, int version)
4809{
4810    uint32_t tlbncfg[2];
4811    uint64_t ivor_mask;
4812    uint64_t ivpr_mask = 0xFFFF0000ULL;
4813    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4814                    | 0x0020; /* 32 kb */
4815    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4816                    | 0x0020; /* 32 kb */
4817    uint32_t mmucfg = 0;
4818#if !defined(CONFIG_USER_ONLY)
4819    int i;
4820#endif
4821
4822    /* Time base */
4823    gen_tbl(env);
4824    /*
4825     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4826     *     complain when accessing them.
4827     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4828     */
4829    switch (version) {
4830    case fsl_e500v1:
4831    case fsl_e500v2:
4832    default:
4833        ivor_mask = 0x0000000F0000FFFFULL;
4834        break;
4835    case fsl_e500mc:
4836    case fsl_e5500:
4837        ivor_mask = 0x000003FE0000FFFFULL;
4838        break;
4839    case fsl_e6500:
4840        ivor_mask = 0x000003FF0000FFFFULL;
4841        break;
4842    }
4843    gen_spr_BookE(env, ivor_mask);
4844    gen_spr_usprg3(env);
4845    /* Processor identification */
4846    spr_register(env, SPR_BOOKE_PIR, "PIR",
4847                 SPR_NOACCESS, SPR_NOACCESS,
4848                 &spr_read_generic, &spr_write_pir,
4849                 0x00000000);
4850    /* XXX : not implemented */
4851    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4852                 &spr_read_spefscr, &spr_write_spefscr,
4853                 &spr_read_spefscr, &spr_write_spefscr,
4854                 0x00000000);
4855#if !defined(CONFIG_USER_ONLY)
4856    /* Memory management */
4857    env->nb_pids = 3;
4858    env->nb_ways = 2;
4859    env->id_tlbs = 0;
4860    switch (version) {
4861    case fsl_e500v1:
4862        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4863        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4864        break;
4865    case fsl_e500v2:
4866        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4867        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4868        break;
4869    case fsl_e500mc:
4870    case fsl_e5500:
4871        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4872        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4873        break;
4874    case fsl_e6500:
4875        mmucfg = 0x6510B45;
4876        env->nb_pids = 1;
4877        tlbncfg[0] = 0x08052400;
4878        tlbncfg[1] = 0x40028040;
4879        break;
4880    default:
4881        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4882                  env->spr[SPR_PVR]);
4883    }
4884#endif
4885    /* Cache sizes */
4886    switch (version) {
4887    case fsl_e500v1:
4888    case fsl_e500v2:
4889        env->dcache_line_size = 32;
4890        env->icache_line_size = 32;
4891        break;
4892    case fsl_e500mc:
4893    case fsl_e5500:
4894        env->dcache_line_size = 64;
4895        env->icache_line_size = 64;
4896        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4897        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4898        break;
4899    case fsl_e6500:
4900        env->dcache_line_size = 32;
4901        env->icache_line_size = 32;
4902        l1cfg0 |= 0x0F83820;
4903        l1cfg1 |= 0x0B83820;
4904        break;
4905    default:
4906        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4907                  env->spr[SPR_PVR]);
4908    }
4909    gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4910    /* XXX : not implemented */
4911    spr_register(env, SPR_HID0, "HID0",
4912                 SPR_NOACCESS, SPR_NOACCESS,
4913                 &spr_read_generic, &spr_write_generic,
4914                 0x00000000);
4915    /* XXX : not implemented */
4916    spr_register(env, SPR_HID1, "HID1",
4917                 SPR_NOACCESS, SPR_NOACCESS,
4918                 &spr_read_generic, &spr_write_generic,
4919                 0x00000000);
4920    /* XXX : not implemented */
4921    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4922                 SPR_NOACCESS, SPR_NOACCESS,
4923                 &spr_read_generic, &spr_write_generic,
4924                 0x00000000);
4925    /* XXX : not implemented */
4926    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4927                 SPR_NOACCESS, SPR_NOACCESS,
4928                 &spr_read_generic, &spr_write_generic,
4929