qemu/target/ppc/translate_init.inc.c
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   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "disas/dis-asm.h"
  22#include "exec/gdbstub.h"
  23#include "kvm_ppc.h"
  24#include "sysemu/arch_init.h"
  25#include "sysemu/cpus.h"
  26#include "sysemu/hw_accel.h"
  27#include "sysemu/tcg.h"
  28#include "cpu-models.h"
  29#include "mmu-hash32.h"
  30#include "mmu-hash64.h"
  31#include "qemu/error-report.h"
  32#include "qemu/module.h"
  33#include "qemu/qemu-print.h"
  34#include "qapi/error.h"
  35#include "qapi/qmp/qnull.h"
  36#include "qapi/visitor.h"
  37#include "hw/qdev-properties.h"
  38#include "hw/ppc/ppc.h"
  39#include "mmu-book3s-v3.h"
  40#include "sysemu/qtest.h"
  41#include "qemu/cutils.h"
  42#include "disas/capstone.h"
  43#include "fpu/softfloat.h"
  44#include "qapi/qapi-commands-machine-target.h"
  45
  46/* #define PPC_DUMP_CPU */
  47/* #define PPC_DEBUG_SPR */
  48/* #define PPC_DUMP_SPR_ACCESSES */
  49/* #define USE_APPLE_GDB */
  50
  51/*
  52 * Generic callbacks:
  53 * do nothing but store/retrieve spr value
  54 */
  55static void spr_load_dump_spr(int sprn)
  56{
  57#ifdef PPC_DUMP_SPR_ACCESSES
  58    TCGv_i32 t0 = tcg_const_i32(sprn);
  59    gen_helper_load_dump_spr(cpu_env, t0);
  60    tcg_temp_free_i32(t0);
  61#endif
  62}
  63
  64static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
  65{
  66    gen_load_spr(cpu_gpr[gprn], sprn);
  67    spr_load_dump_spr(sprn);
  68}
  69
  70static void spr_store_dump_spr(int sprn)
  71{
  72#ifdef PPC_DUMP_SPR_ACCESSES
  73    TCGv_i32 t0 = tcg_const_i32(sprn);
  74    gen_helper_store_dump_spr(cpu_env, t0);
  75    tcg_temp_free_i32(t0);
  76#endif
  77}
  78
  79static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
  80{
  81    gen_store_spr(sprn, cpu_gpr[gprn]);
  82    spr_store_dump_spr(sprn);
  83}
  84
  85#if !defined(CONFIG_USER_ONLY)
  86static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
  87{
  88#ifdef TARGET_PPC64
  89    TCGv t0 = tcg_temp_new();
  90    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
  91    gen_store_spr(sprn, t0);
  92    tcg_temp_free(t0);
  93    spr_store_dump_spr(sprn);
  94#else
  95    spr_write_generic(ctx, sprn, gprn);
  96#endif
  97}
  98
  99static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
 100{
 101    TCGv t0 = tcg_temp_new();
 102    TCGv t1 = tcg_temp_new();
 103    gen_load_spr(t0, sprn);
 104    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 105    tcg_gen_and_tl(t0, t0, t1);
 106    gen_store_spr(sprn, t0);
 107    tcg_temp_free(t0);
 108    tcg_temp_free(t1);
 109}
 110
 111static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
 112{
 113}
 114
 115#endif
 116
 117/* SPR common to all PowerPC */
 118/* XER */
 119static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
 120{
 121    gen_read_xer(ctx, cpu_gpr[gprn]);
 122}
 123
 124static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
 125{
 126    gen_write_xer(cpu_gpr[gprn]);
 127}
 128
 129/* LR */
 130static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
 131{
 132    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 133}
 134
 135static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 136{
 137    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 138}
 139
 140/* CFAR */
 141#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 142static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 143{
 144    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
 145}
 146
 147static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 148{
 149    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
 150}
 151#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
 152
 153/* CTR */
 154static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
 155{
 156    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 157}
 158
 159static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
 160{
 161    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 162}
 163
 164/* User read access to SPR */
 165/* USPRx */
 166/* UMMCRx */
 167/* UPMCx */
 168/* USIA */
 169/* UDECR */
 170static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
 171{
 172    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 173}
 174
 175#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 176static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 177{
 178    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
 179}
 180#endif
 181
 182/* SPR common to all non-embedded PowerPC */
 183/* DECR */
 184#if !defined(CONFIG_USER_ONLY)
 185static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
 186{
 187    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 188        gen_io_start();
 189    }
 190    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 191    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 192        gen_stop_exception(ctx);
 193    }
 194}
 195
 196static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 197{
 198    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 199        gen_io_start();
 200    }
 201    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 202    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 203        gen_stop_exception(ctx);
 204    }
 205}
 206#endif
 207
 208/* SPR common to all non-embedded PowerPC, except 601 */
 209/* Time base */
 210static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
 211{
 212    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 213        gen_io_start();
 214    }
 215    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 216    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 217        gen_io_end();
 218        gen_stop_exception(ctx);
 219    }
 220}
 221
 222static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
 223{
 224    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 225        gen_io_start();
 226    }
 227    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 228    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 229        gen_io_end();
 230        gen_stop_exception(ctx);
 231    }
 232}
 233
 234ATTRIBUTE_UNUSED
 235static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
 236{
 237    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
 238}
 239
 240ATTRIBUTE_UNUSED
 241static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
 242{
 243    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
 244}
 245
 246#if !defined(CONFIG_USER_ONLY)
 247static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
 248{
 249    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 250        gen_io_start();
 251    }
 252    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 253    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 254        gen_io_end();
 255        gen_stop_exception(ctx);
 256    }
 257}
 258
 259static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
 260{
 261    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 262        gen_io_start();
 263    }
 264    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 265    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 266        gen_io_end();
 267        gen_stop_exception(ctx);
 268    }
 269}
 270
 271ATTRIBUTE_UNUSED
 272static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
 273{
 274    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
 275}
 276
 277ATTRIBUTE_UNUSED
 278static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
 279{
 280    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
 281}
 282
 283#if defined(TARGET_PPC64)
 284ATTRIBUTE_UNUSED
 285static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
 286{
 287    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 288}
 289
 290/* HDECR */
 291static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
 292{
 293    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 294        gen_io_start();
 295    }
 296    gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
 297    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 298        gen_io_end();
 299        gen_stop_exception(ctx);
 300    }
 301}
 302
 303static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
 304{
 305    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 306        gen_io_start();
 307    }
 308    gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
 309    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 310        gen_io_end();
 311        gen_stop_exception(ctx);
 312    }
 313}
 314
 315#endif
 316#endif
 317
 318#if !defined(CONFIG_USER_ONLY)
 319/* IBAT0U...IBAT0U */
 320/* IBAT0L...IBAT7L */
 321static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
 322{
 323    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 324                  offsetof(CPUPPCState,
 325                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 326}
 327
 328static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
 329{
 330    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 331                  offsetof(CPUPPCState,
 332                           IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
 333}
 334
 335static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
 336{
 337    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 338    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 339    tcg_temp_free_i32(t0);
 340}
 341
 342static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
 343{
 344    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 345    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 346    tcg_temp_free_i32(t0);
 347}
 348
 349static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
 350{
 351    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 352    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 353    tcg_temp_free_i32(t0);
 354}
 355
 356static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
 357{
 358    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 359    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 360    tcg_temp_free_i32(t0);
 361}
 362
 363/* DBAT0U...DBAT7U */
 364/* DBAT0L...DBAT7L */
 365static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
 366{
 367    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 368                  offsetof(CPUPPCState,
 369                           DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 370}
 371
 372static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
 373{
 374    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 375                  offsetof(CPUPPCState,
 376                           DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 377}
 378
 379static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
 380{
 381    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 382    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 383    tcg_temp_free_i32(t0);
 384}
 385
 386static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
 387{
 388    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 389    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 390    tcg_temp_free_i32(t0);
 391}
 392
 393static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
 394{
 395    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 396    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 397    tcg_temp_free_i32(t0);
 398}
 399
 400static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
 401{
 402    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 403    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 404    tcg_temp_free_i32(t0);
 405}
 406
 407/* SDR1 */
 408static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
 409{
 410    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
 411}
 412
 413#if defined(TARGET_PPC64)
 414/* 64 bits PowerPC specific SPRs */
 415/* PIDR */
 416static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
 417{
 418    gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
 419}
 420
 421static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
 422{
 423    gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
 424}
 425
 426static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
 427{
 428    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
 429}
 430
 431static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
 432{
 433    TCGv t0 = tcg_temp_new();
 434    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 435    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 436    tcg_temp_free(t0);
 437}
 438static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
 439{
 440    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
 441}
 442
 443static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
 444{
 445    gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
 446}
 447#endif
 448#endif
 449
 450/* PowerPC 601 specific registers */
 451/* RTC */
 452static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
 453{
 454    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
 455}
 456
 457static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
 458{
 459    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
 460}
 461
 462#if !defined(CONFIG_USER_ONLY)
 463static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
 464{
 465    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
 466}
 467
 468static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
 469{
 470    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
 471}
 472
 473static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
 474{
 475    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
 476    /* Must stop the translation as endianness may have changed */
 477    gen_stop_exception(ctx);
 478}
 479#endif
 480
 481/* Unified bats */
 482#if !defined(CONFIG_USER_ONLY)
 483static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
 484{
 485    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 486                  offsetof(CPUPPCState,
 487                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 488}
 489
 490static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
 491{
 492    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 493    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
 494    tcg_temp_free_i32(t0);
 495}
 496
 497static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
 498{
 499    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 500    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
 501    tcg_temp_free_i32(t0);
 502}
 503#endif
 504
 505/* PowerPC 40x specific registers */
 506#if !defined(CONFIG_USER_ONLY)
 507static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
 508{
 509    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 510}
 511
 512static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
 513{
 514    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 515}
 516
 517static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 518{
 519    gen_store_spr(sprn, cpu_gpr[gprn]);
 520    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
 521    /* We must stop translation as we may have rebooted */
 522    gen_stop_exception(ctx);
 523}
 524
 525static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
 526{
 527    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 528}
 529
 530static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
 531{
 532    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 533}
 534
 535static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
 536{
 537    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 538}
 539#endif
 540
 541/* PowerPC 403 specific registers */
 542/* PBL1 / PBU1 / PBL2 / PBU2 */
 543#if !defined(CONFIG_USER_ONLY)
 544static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
 545{
 546    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 547                  offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
 548}
 549
 550static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
 551{
 552    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 553    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
 554    tcg_temp_free_i32(t0);
 555}
 556
 557static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
 558{
 559    TCGv t0 = tcg_temp_new();
 560    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 561    gen_store_spr(SPR_PIR, t0);
 562    tcg_temp_free(t0);
 563}
 564#endif
 565
 566/* SPE specific registers */
 567static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
 568{
 569    TCGv_i32 t0 = tcg_temp_new_i32();
 570    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 571    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 572    tcg_temp_free_i32(t0);
 573}
 574
 575static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
 576{
 577    TCGv_i32 t0 = tcg_temp_new_i32();
 578    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 579    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 580    tcg_temp_free_i32(t0);
 581}
 582
 583#if !defined(CONFIG_USER_ONLY)
 584/* Callback used to write the exception vector base */
 585static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
 586{
 587    TCGv t0 = tcg_temp_new();
 588    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
 589    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 590    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 591    gen_store_spr(sprn, t0);
 592    tcg_temp_free(t0);
 593}
 594
 595static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
 596{
 597    int sprn_offs;
 598
 599    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 600        sprn_offs = sprn - SPR_BOOKE_IVOR0;
 601    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 602        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
 603    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
 604        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
 605    } else {
 606        printf("Trying to write an unknown exception vector %d %03x\n",
 607               sprn, sprn);
 608        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 609        return;
 610    }
 611
 612    TCGv t0 = tcg_temp_new();
 613    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
 614    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 615    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
 616    gen_store_spr(sprn, t0);
 617    tcg_temp_free(t0);
 618}
 619#endif
 620
 621static inline void vscr_init(CPUPPCState *env, uint32_t val)
 622{
 623    /* Altivec always uses round-to-nearest */
 624    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 625    helper_mtvscr(env, val);
 626}
 627
 628#ifdef CONFIG_USER_ONLY
 629#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 630                         oea_read, oea_write, one_reg_id, initial_value)       \
 631    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 632#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 633                            oea_read, oea_write, hea_read, hea_write,          \
 634                            one_reg_id, initial_value)                         \
 635    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 636#else
 637#if !defined(CONFIG_KVM)
 638#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 639                         oea_read, oea_write, one_reg_id, initial_value)       \
 640    _spr_register(env, num, name, uea_read, uea_write,                         \
 641                  oea_read, oea_write, oea_read, oea_write, initial_value)
 642#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 643                            oea_read, oea_write, hea_read, hea_write,          \
 644                            one_reg_id, initial_value)                         \
 645    _spr_register(env, num, name, uea_read, uea_write,                         \
 646                  oea_read, oea_write, hea_read, hea_write, initial_value)
 647#else
 648#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 649                         oea_read, oea_write, one_reg_id, initial_value)       \
 650    _spr_register(env, num, name, uea_read, uea_write,                         \
 651                  oea_read, oea_write, oea_read, oea_write,                    \
 652                  one_reg_id, initial_value)
 653#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 654                            oea_read, oea_write, hea_read, hea_write,          \
 655                            one_reg_id, initial_value)                         \
 656    _spr_register(env, num, name, uea_read, uea_write,                         \
 657                  oea_read, oea_write, hea_read, hea_write,                    \
 658                  one_reg_id, initial_value)
 659#endif
 660#endif
 661
 662#define spr_register(env, num, name, uea_read, uea_write,                      \
 663                     oea_read, oea_write, initial_value)                       \
 664    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
 665                     oea_read, oea_write, 0, initial_value)
 666
 667#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
 668                        oea_read, oea_write, hea_read, hea_write,              \
 669                        initial_value)                                         \
 670    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
 671                        oea_read, oea_write, hea_read, hea_write,              \
 672                        0, initial_value)
 673
 674static inline void _spr_register(CPUPPCState *env, int num,
 675                                 const char *name,
 676                                 void (*uea_read)(DisasContext *ctx,
 677                                                  int gprn, int sprn),
 678                                 void (*uea_write)(DisasContext *ctx,
 679                                                   int sprn, int gprn),
 680#if !defined(CONFIG_USER_ONLY)
 681
 682                                 void (*oea_read)(DisasContext *ctx,
 683                                                  int gprn, int sprn),
 684                                 void (*oea_write)(DisasContext *ctx,
 685                                                   int sprn, int gprn),
 686                                 void (*hea_read)(DisasContext *opaque,
 687                                                  int gprn, int sprn),
 688                                 void (*hea_write)(DisasContext *opaque,
 689                                                   int sprn, int gprn),
 690#endif
 691#if defined(CONFIG_KVM)
 692                                 uint64_t one_reg_id,
 693#endif
 694                                 target_ulong initial_value)
 695{
 696    ppc_spr_t *spr;
 697
 698    spr = &env->spr_cb[num];
 699    if (spr->name != NULL || env->spr[num] != 0x00000000 ||
 700#if !defined(CONFIG_USER_ONLY)
 701        spr->oea_read != NULL || spr->oea_write != NULL ||
 702#endif
 703        spr->uea_read != NULL || spr->uea_write != NULL) {
 704        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 705        exit(1);
 706    }
 707#if defined(PPC_DEBUG_SPR)
 708    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 709           name, initial_value);
 710#endif
 711    spr->name = name;
 712    spr->uea_read = uea_read;
 713    spr->uea_write = uea_write;
 714#if !defined(CONFIG_USER_ONLY)
 715    spr->oea_read = oea_read;
 716    spr->oea_write = oea_write;
 717    spr->hea_read = hea_read;
 718    spr->hea_write = hea_write;
 719#endif
 720#if defined(CONFIG_KVM)
 721    spr->one_reg_id = one_reg_id,
 722#endif
 723    env->spr[num] = spr->default_value = initial_value;
 724}
 725
 726/* Generic PowerPC SPRs */
 727static void gen_spr_generic(CPUPPCState *env)
 728{
 729    /* Integer processing */
 730    spr_register(env, SPR_XER, "XER",
 731                 &spr_read_xer, &spr_write_xer,
 732                 &spr_read_xer, &spr_write_xer,
 733                 0x00000000);
 734    /* Branch contol */
 735    spr_register(env, SPR_LR, "LR",
 736                 &spr_read_lr, &spr_write_lr,
 737                 &spr_read_lr, &spr_write_lr,
 738                 0x00000000);
 739    spr_register(env, SPR_CTR, "CTR",
 740                 &spr_read_ctr, &spr_write_ctr,
 741                 &spr_read_ctr, &spr_write_ctr,
 742                 0x00000000);
 743    /* Interrupt processing */
 744    spr_register(env, SPR_SRR0, "SRR0",
 745                 SPR_NOACCESS, SPR_NOACCESS,
 746                 &spr_read_generic, &spr_write_generic,
 747                 0x00000000);
 748    spr_register(env, SPR_SRR1, "SRR1",
 749                 SPR_NOACCESS, SPR_NOACCESS,
 750                 &spr_read_generic, &spr_write_generic,
 751                 0x00000000);
 752    /* Processor control */
 753    spr_register(env, SPR_SPRG0, "SPRG0",
 754                 SPR_NOACCESS, SPR_NOACCESS,
 755                 &spr_read_generic, &spr_write_generic,
 756                 0x00000000);
 757    spr_register(env, SPR_SPRG1, "SPRG1",
 758                 SPR_NOACCESS, SPR_NOACCESS,
 759                 &spr_read_generic, &spr_write_generic,
 760                 0x00000000);
 761    spr_register(env, SPR_SPRG2, "SPRG2",
 762                 SPR_NOACCESS, SPR_NOACCESS,
 763                 &spr_read_generic, &spr_write_generic,
 764                 0x00000000);
 765    spr_register(env, SPR_SPRG3, "SPRG3",
 766                 SPR_NOACCESS, SPR_NOACCESS,
 767                 &spr_read_generic, &spr_write_generic,
 768                 0x00000000);
 769}
 770
 771/* SPR common to all non-embedded PowerPC, including 601 */
 772static void gen_spr_ne_601(CPUPPCState *env)
 773{
 774    /* Exception processing */
 775    spr_register_kvm(env, SPR_DSISR, "DSISR",
 776                     SPR_NOACCESS, SPR_NOACCESS,
 777                     &spr_read_generic, &spr_write_generic,
 778                     KVM_REG_PPC_DSISR, 0x00000000);
 779    spr_register_kvm(env, SPR_DAR, "DAR",
 780                     SPR_NOACCESS, SPR_NOACCESS,
 781                     &spr_read_generic, &spr_write_generic,
 782                     KVM_REG_PPC_DAR, 0x00000000);
 783    /* Timer */
 784    spr_register(env, SPR_DECR, "DECR",
 785                 SPR_NOACCESS, SPR_NOACCESS,
 786                 &spr_read_decr, &spr_write_decr,
 787                 0x00000000);
 788}
 789
 790/* Storage Description Register 1 */
 791static void gen_spr_sdr1(CPUPPCState *env)
 792{
 793#ifndef CONFIG_USER_ONLY
 794    if (env->has_hv_mode) {
 795        /*
 796         * SDR1 is a hypervisor resource on CPUs which have a
 797         * hypervisor mode
 798         */
 799        spr_register_hv(env, SPR_SDR1, "SDR1",
 800                        SPR_NOACCESS, SPR_NOACCESS,
 801                        SPR_NOACCESS, SPR_NOACCESS,
 802                        &spr_read_generic, &spr_write_sdr1,
 803                        0x00000000);
 804    } else {
 805        spr_register(env, SPR_SDR1, "SDR1",
 806                     SPR_NOACCESS, SPR_NOACCESS,
 807                     &spr_read_generic, &spr_write_sdr1,
 808                     0x00000000);
 809    }
 810#endif
 811}
 812
 813/* BATs 0-3 */
 814static void gen_low_BATs(CPUPPCState *env)
 815{
 816#if !defined(CONFIG_USER_ONLY)
 817    spr_register(env, SPR_IBAT0U, "IBAT0U",
 818                 SPR_NOACCESS, SPR_NOACCESS,
 819                 &spr_read_ibat, &spr_write_ibatu,
 820                 0x00000000);
 821    spr_register(env, SPR_IBAT0L, "IBAT0L",
 822                 SPR_NOACCESS, SPR_NOACCESS,
 823                 &spr_read_ibat, &spr_write_ibatl,
 824                 0x00000000);
 825    spr_register(env, SPR_IBAT1U, "IBAT1U",
 826                 SPR_NOACCESS, SPR_NOACCESS,
 827                 &spr_read_ibat, &spr_write_ibatu,
 828                 0x00000000);
 829    spr_register(env, SPR_IBAT1L, "IBAT1L",
 830                 SPR_NOACCESS, SPR_NOACCESS,
 831                 &spr_read_ibat, &spr_write_ibatl,
 832                 0x00000000);
 833    spr_register(env, SPR_IBAT2U, "IBAT2U",
 834                 SPR_NOACCESS, SPR_NOACCESS,
 835                 &spr_read_ibat, &spr_write_ibatu,
 836                 0x00000000);
 837    spr_register(env, SPR_IBAT2L, "IBAT2L",
 838                 SPR_NOACCESS, SPR_NOACCESS,
 839                 &spr_read_ibat, &spr_write_ibatl,
 840                 0x00000000);
 841    spr_register(env, SPR_IBAT3U, "IBAT3U",
 842                 SPR_NOACCESS, SPR_NOACCESS,
 843                 &spr_read_ibat, &spr_write_ibatu,
 844                 0x00000000);
 845    spr_register(env, SPR_IBAT3L, "IBAT3L",
 846                 SPR_NOACCESS, SPR_NOACCESS,
 847                 &spr_read_ibat, &spr_write_ibatl,
 848                 0x00000000);
 849    spr_register(env, SPR_DBAT0U, "DBAT0U",
 850                 SPR_NOACCESS, SPR_NOACCESS,
 851                 &spr_read_dbat, &spr_write_dbatu,
 852                 0x00000000);
 853    spr_register(env, SPR_DBAT0L, "DBAT0L",
 854                 SPR_NOACCESS, SPR_NOACCESS,
 855                 &spr_read_dbat, &spr_write_dbatl,
 856                 0x00000000);
 857    spr_register(env, SPR_DBAT1U, "DBAT1U",
 858                 SPR_NOACCESS, SPR_NOACCESS,
 859                 &spr_read_dbat, &spr_write_dbatu,
 860                 0x00000000);
 861    spr_register(env, SPR_DBAT1L, "DBAT1L",
 862                 SPR_NOACCESS, SPR_NOACCESS,
 863                 &spr_read_dbat, &spr_write_dbatl,
 864                 0x00000000);
 865    spr_register(env, SPR_DBAT2U, "DBAT2U",
 866                 SPR_NOACCESS, SPR_NOACCESS,
 867                 &spr_read_dbat, &spr_write_dbatu,
 868                 0x00000000);
 869    spr_register(env, SPR_DBAT2L, "DBAT2L",
 870                 SPR_NOACCESS, SPR_NOACCESS,
 871                 &spr_read_dbat, &spr_write_dbatl,
 872                 0x00000000);
 873    spr_register(env, SPR_DBAT3U, "DBAT3U",
 874                 SPR_NOACCESS, SPR_NOACCESS,
 875                 &spr_read_dbat, &spr_write_dbatu,
 876                 0x00000000);
 877    spr_register(env, SPR_DBAT3L, "DBAT3L",
 878                 SPR_NOACCESS, SPR_NOACCESS,
 879                 &spr_read_dbat, &spr_write_dbatl,
 880                 0x00000000);
 881    env->nb_BATs += 4;
 882#endif
 883}
 884
 885/* BATs 4-7 */
 886static void gen_high_BATs(CPUPPCState *env)
 887{
 888#if !defined(CONFIG_USER_ONLY)
 889    spr_register(env, SPR_IBAT4U, "IBAT4U",
 890                 SPR_NOACCESS, SPR_NOACCESS,
 891                 &spr_read_ibat_h, &spr_write_ibatu_h,
 892                 0x00000000);
 893    spr_register(env, SPR_IBAT4L, "IBAT4L",
 894                 SPR_NOACCESS, SPR_NOACCESS,
 895                 &spr_read_ibat_h, &spr_write_ibatl_h,
 896                 0x00000000);
 897    spr_register(env, SPR_IBAT5U, "IBAT5U",
 898                 SPR_NOACCESS, SPR_NOACCESS,
 899                 &spr_read_ibat_h, &spr_write_ibatu_h,
 900                 0x00000000);
 901    spr_register(env, SPR_IBAT5L, "IBAT5L",
 902                 SPR_NOACCESS, SPR_NOACCESS,
 903                 &spr_read_ibat_h, &spr_write_ibatl_h,
 904                 0x00000000);
 905    spr_register(env, SPR_IBAT6U, "IBAT6U",
 906                 SPR_NOACCESS, SPR_NOACCESS,
 907                 &spr_read_ibat_h, &spr_write_ibatu_h,
 908                 0x00000000);
 909    spr_register(env, SPR_IBAT6L, "IBAT6L",
 910                 SPR_NOACCESS, SPR_NOACCESS,
 911                 &spr_read_ibat_h, &spr_write_ibatl_h,
 912                 0x00000000);
 913    spr_register(env, SPR_IBAT7U, "IBAT7U",
 914                 SPR_NOACCESS, SPR_NOACCESS,
 915                 &spr_read_ibat_h, &spr_write_ibatu_h,
 916                 0x00000000);
 917    spr_register(env, SPR_IBAT7L, "IBAT7L",
 918                 SPR_NOACCESS, SPR_NOACCESS,
 919                 &spr_read_ibat_h, &spr_write_ibatl_h,
 920                 0x00000000);
 921    spr_register(env, SPR_DBAT4U, "DBAT4U",
 922                 SPR_NOACCESS, SPR_NOACCESS,
 923                 &spr_read_dbat_h, &spr_write_dbatu_h,
 924                 0x00000000);
 925    spr_register(env, SPR_DBAT4L, "DBAT4L",
 926                 SPR_NOACCESS, SPR_NOACCESS,
 927                 &spr_read_dbat_h, &spr_write_dbatl_h,
 928                 0x00000000);
 929    spr_register(env, SPR_DBAT5U, "DBAT5U",
 930                 SPR_NOACCESS, SPR_NOACCESS,
 931                 &spr_read_dbat_h, &spr_write_dbatu_h,
 932                 0x00000000);
 933    spr_register(env, SPR_DBAT5L, "DBAT5L",
 934                 SPR_NOACCESS, SPR_NOACCESS,
 935                 &spr_read_dbat_h, &spr_write_dbatl_h,
 936                 0x00000000);
 937    spr_register(env, SPR_DBAT6U, "DBAT6U",
 938                 SPR_NOACCESS, SPR_NOACCESS,
 939                 &spr_read_dbat_h, &spr_write_dbatu_h,
 940                 0x00000000);
 941    spr_register(env, SPR_DBAT6L, "DBAT6L",
 942                 SPR_NOACCESS, SPR_NOACCESS,
 943                 &spr_read_dbat_h, &spr_write_dbatl_h,
 944                 0x00000000);
 945    spr_register(env, SPR_DBAT7U, "DBAT7U",
 946                 SPR_NOACCESS, SPR_NOACCESS,
 947                 &spr_read_dbat_h, &spr_write_dbatu_h,
 948                 0x00000000);
 949    spr_register(env, SPR_DBAT7L, "DBAT7L",
 950                 SPR_NOACCESS, SPR_NOACCESS,
 951                 &spr_read_dbat_h, &spr_write_dbatl_h,
 952                 0x00000000);
 953    env->nb_BATs += 4;
 954#endif
 955}
 956
 957/* Generic PowerPC time base */
 958static void gen_tbl(CPUPPCState *env)
 959{
 960    spr_register(env, SPR_VTBL,  "TBL",
 961                 &spr_read_tbl, SPR_NOACCESS,
 962                 &spr_read_tbl, SPR_NOACCESS,
 963                 0x00000000);
 964    spr_register(env, SPR_TBL,   "TBL",
 965                 &spr_read_tbl, SPR_NOACCESS,
 966                 &spr_read_tbl, &spr_write_tbl,
 967                 0x00000000);
 968    spr_register(env, SPR_VTBU,  "TBU",
 969                 &spr_read_tbu, SPR_NOACCESS,
 970                 &spr_read_tbu, SPR_NOACCESS,
 971                 0x00000000);
 972    spr_register(env, SPR_TBU,   "TBU",
 973                 &spr_read_tbu, SPR_NOACCESS,
 974                 &spr_read_tbu, &spr_write_tbu,
 975                 0x00000000);
 976}
 977
 978/* Softare table search registers */
 979static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 980{
 981#if !defined(CONFIG_USER_ONLY)
 982    env->nb_tlb = nb_tlbs;
 983    env->nb_ways = nb_ways;
 984    env->id_tlbs = 1;
 985    env->tlb_type = TLB_6XX;
 986    spr_register(env, SPR_DMISS, "DMISS",
 987                 SPR_NOACCESS, SPR_NOACCESS,
 988                 &spr_read_generic, SPR_NOACCESS,
 989                 0x00000000);
 990    spr_register(env, SPR_DCMP, "DCMP",
 991                 SPR_NOACCESS, SPR_NOACCESS,
 992                 &spr_read_generic, SPR_NOACCESS,
 993                 0x00000000);
 994    spr_register(env, SPR_HASH1, "HASH1",
 995                 SPR_NOACCESS, SPR_NOACCESS,
 996                 &spr_read_generic, SPR_NOACCESS,
 997                 0x00000000);
 998    spr_register(env, SPR_HASH2, "HASH2",
 999                 SPR_NOACCESS, SPR_NOACCESS,
1000                 &spr_read_generic, SPR_NOACCESS,
1001                 0x00000000);
1002    spr_register(env, SPR_IMISS, "IMISS",
1003                 SPR_NOACCESS, SPR_NOACCESS,
1004                 &spr_read_generic, SPR_NOACCESS,
1005                 0x00000000);
1006    spr_register(env, SPR_ICMP, "ICMP",
1007                 SPR_NOACCESS, SPR_NOACCESS,
1008                 &spr_read_generic, SPR_NOACCESS,
1009                 0x00000000);
1010    spr_register(env, SPR_RPA, "RPA",
1011                 SPR_NOACCESS, SPR_NOACCESS,
1012                 &spr_read_generic, &spr_write_generic,
1013                 0x00000000);
1014#endif
1015}
1016
1017/* SPR common to MPC755 and G2 */
1018static void gen_spr_G2_755(CPUPPCState *env)
1019{
1020    /* SGPRs */
1021    spr_register(env, SPR_SPRG4, "SPRG4",
1022                 SPR_NOACCESS, SPR_NOACCESS,
1023                 &spr_read_generic, &spr_write_generic,
1024                 0x00000000);
1025    spr_register(env, SPR_SPRG5, "SPRG5",
1026                 SPR_NOACCESS, SPR_NOACCESS,
1027                 &spr_read_generic, &spr_write_generic,
1028                 0x00000000);
1029    spr_register(env, SPR_SPRG6, "SPRG6",
1030                 SPR_NOACCESS, SPR_NOACCESS,
1031                 &spr_read_generic, &spr_write_generic,
1032                 0x00000000);
1033    spr_register(env, SPR_SPRG7, "SPRG7",
1034                 SPR_NOACCESS, SPR_NOACCESS,
1035                 &spr_read_generic, &spr_write_generic,
1036                 0x00000000);
1037}
1038
1039/* SPR common to all 7xx PowerPC implementations */
1040static void gen_spr_7xx(CPUPPCState *env)
1041{
1042    /* Breakpoints */
1043    /* XXX : not implemented */
1044    spr_register_kvm(env, SPR_DABR, "DABR",
1045                     SPR_NOACCESS, SPR_NOACCESS,
1046                     &spr_read_generic, &spr_write_generic,
1047                     KVM_REG_PPC_DABR, 0x00000000);
1048    /* XXX : not implemented */
1049    spr_register(env, SPR_IABR, "IABR",
1050                 SPR_NOACCESS, SPR_NOACCESS,
1051                 &spr_read_generic, &spr_write_generic,
1052                 0x00000000);
1053    /* Cache management */
1054    /* XXX : not implemented */
1055    spr_register(env, SPR_ICTC, "ICTC",
1056                 SPR_NOACCESS, SPR_NOACCESS,
1057                 &spr_read_generic, &spr_write_generic,
1058                 0x00000000);
1059    /* Performance monitors */
1060    /* XXX : not implemented */
1061    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1062                 SPR_NOACCESS, SPR_NOACCESS,
1063                 &spr_read_generic, &spr_write_generic,
1064                 0x00000000);
1065    /* XXX : not implemented */
1066    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1067                 SPR_NOACCESS, SPR_NOACCESS,
1068                 &spr_read_generic, &spr_write_generic,
1069                 0x00000000);
1070    /* XXX : not implemented */
1071    spr_register(env, SPR_7XX_PMC1, "PMC1",
1072                 SPR_NOACCESS, SPR_NOACCESS,
1073                 &spr_read_generic, &spr_write_generic,
1074                 0x00000000);
1075    /* XXX : not implemented */
1076    spr_register(env, SPR_7XX_PMC2, "PMC2",
1077                 SPR_NOACCESS, SPR_NOACCESS,
1078                 &spr_read_generic, &spr_write_generic,
1079                 0x00000000);
1080    /* XXX : not implemented */
1081    spr_register(env, SPR_7XX_PMC3, "PMC3",
1082                 SPR_NOACCESS, SPR_NOACCESS,
1083                 &spr_read_generic, &spr_write_generic,
1084                 0x00000000);
1085    /* XXX : not implemented */
1086    spr_register(env, SPR_7XX_PMC4, "PMC4",
1087                 SPR_NOACCESS, SPR_NOACCESS,
1088                 &spr_read_generic, &spr_write_generic,
1089                 0x00000000);
1090    /* XXX : not implemented */
1091    spr_register(env, SPR_7XX_SIAR, "SIAR",
1092                 SPR_NOACCESS, SPR_NOACCESS,
1093                 &spr_read_generic, SPR_NOACCESS,
1094                 0x00000000);
1095    /* XXX : not implemented */
1096    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1097                 &spr_read_ureg, SPR_NOACCESS,
1098                 &spr_read_ureg, SPR_NOACCESS,
1099                 0x00000000);
1100    /* XXX : not implemented */
1101    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1102                 &spr_read_ureg, SPR_NOACCESS,
1103                 &spr_read_ureg, SPR_NOACCESS,
1104                 0x00000000);
1105    /* XXX : not implemented */
1106    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1107                 &spr_read_ureg, SPR_NOACCESS,
1108                 &spr_read_ureg, SPR_NOACCESS,
1109                 0x00000000);
1110    /* XXX : not implemented */
1111    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1112                 &spr_read_ureg, SPR_NOACCESS,
1113                 &spr_read_ureg, SPR_NOACCESS,
1114                 0x00000000);
1115    /* XXX : not implemented */
1116    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1117                 &spr_read_ureg, SPR_NOACCESS,
1118                 &spr_read_ureg, SPR_NOACCESS,
1119                 0x00000000);
1120    /* XXX : not implemented */
1121    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1122                 &spr_read_ureg, SPR_NOACCESS,
1123                 &spr_read_ureg, SPR_NOACCESS,
1124                 0x00000000);
1125    /* XXX : not implemented */
1126    spr_register(env, SPR_7XX_USIAR, "USIAR",
1127                 &spr_read_ureg, SPR_NOACCESS,
1128                 &spr_read_ureg, SPR_NOACCESS,
1129                 0x00000000);
1130    /* External access control */
1131    /* XXX : not implemented */
1132    spr_register(env, SPR_EAR, "EAR",
1133                 SPR_NOACCESS, SPR_NOACCESS,
1134                 &spr_read_generic, &spr_write_generic,
1135                 0x00000000);
1136}
1137
1138#ifdef TARGET_PPC64
1139#ifndef CONFIG_USER_ONLY
1140static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1141{
1142    TCGv t0 = tcg_temp_new();
1143    TCGv t1 = tcg_temp_new();
1144    TCGv t2 = tcg_temp_new();
1145
1146    /*
1147     * Note, the HV=1 PR=0 case is handled earlier by simply using
1148     * spr_write_generic for HV mode in the SPR table
1149     */
1150
1151    /* Build insertion mask into t1 based on context */
1152    if (ctx->pr) {
1153        gen_load_spr(t1, SPR_UAMOR);
1154    } else {
1155        gen_load_spr(t1, SPR_AMOR);
1156    }
1157
1158    /* Mask new bits into t2 */
1159    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1160
1161    /* Load AMR and clear new bits in t0 */
1162    gen_load_spr(t0, SPR_AMR);
1163    tcg_gen_andc_tl(t0, t0, t1);
1164
1165    /* Or'in new bits and write it out */
1166    tcg_gen_or_tl(t0, t0, t2);
1167    gen_store_spr(SPR_AMR, t0);
1168    spr_store_dump_spr(SPR_AMR);
1169
1170    tcg_temp_free(t0);
1171    tcg_temp_free(t1);
1172    tcg_temp_free(t2);
1173}
1174
1175static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1176{
1177    TCGv t0 = tcg_temp_new();
1178    TCGv t1 = tcg_temp_new();
1179    TCGv t2 = tcg_temp_new();
1180
1181    /*
1182     * Note, the HV=1 case is handled earlier by simply using
1183     * spr_write_generic for HV mode in the SPR table
1184     */
1185
1186    /* Build insertion mask into t1 based on context */
1187    gen_load_spr(t1, SPR_AMOR);
1188
1189    /* Mask new bits into t2 */
1190    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1191
1192    /* Load AMR and clear new bits in t0 */
1193    gen_load_spr(t0, SPR_UAMOR);
1194    tcg_gen_andc_tl(t0, t0, t1);
1195
1196    /* Or'in new bits and write it out */
1197    tcg_gen_or_tl(t0, t0, t2);
1198    gen_store_spr(SPR_UAMOR, t0);
1199    spr_store_dump_spr(SPR_UAMOR);
1200
1201    tcg_temp_free(t0);
1202    tcg_temp_free(t1);
1203    tcg_temp_free(t2);
1204}
1205
1206static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1207{
1208    TCGv t0 = tcg_temp_new();
1209    TCGv t1 = tcg_temp_new();
1210    TCGv t2 = tcg_temp_new();
1211
1212    /*
1213     * Note, the HV=1 case is handled earlier by simply using
1214     * spr_write_generic for HV mode in the SPR table
1215     */
1216
1217    /* Build insertion mask into t1 based on context */
1218    gen_load_spr(t1, SPR_AMOR);
1219
1220    /* Mask new bits into t2 */
1221    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1222
1223    /* Load AMR and clear new bits in t0 */
1224    gen_load_spr(t0, SPR_IAMR);
1225    tcg_gen_andc_tl(t0, t0, t1);
1226
1227    /* Or'in new bits and write it out */
1228    tcg_gen_or_tl(t0, t0, t2);
1229    gen_store_spr(SPR_IAMR, t0);
1230    spr_store_dump_spr(SPR_IAMR);
1231
1232    tcg_temp_free(t0);
1233    tcg_temp_free(t1);
1234    tcg_temp_free(t2);
1235}
1236#endif /* CONFIG_USER_ONLY */
1237
1238static void gen_spr_amr(CPUPPCState *env)
1239{
1240#ifndef CONFIG_USER_ONLY
1241    /*
1242     * Virtual Page Class Key protection
1243     *
1244     * The AMR is accessible either via SPR 13 or SPR 29.  13 is
1245     * userspace accessible, 29 is privileged.  So we only need to set
1246     * the kvm ONE_REG id on one of them, we use 29
1247     */
1248    spr_register(env, SPR_UAMR, "UAMR",
1249                 &spr_read_generic, &spr_write_amr,
1250                 &spr_read_generic, &spr_write_amr,
1251                 0);
1252    spr_register_kvm_hv(env, SPR_AMR, "AMR",
1253                     SPR_NOACCESS, SPR_NOACCESS,
1254                     &spr_read_generic, &spr_write_amr,
1255                     &spr_read_generic, &spr_write_generic,
1256                     KVM_REG_PPC_AMR, 0);
1257    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1258                     SPR_NOACCESS, SPR_NOACCESS,
1259                     &spr_read_generic, &spr_write_uamor,
1260                     &spr_read_generic, &spr_write_generic,
1261                     KVM_REG_PPC_UAMOR, 0);
1262    spr_register_hv(env, SPR_AMOR, "AMOR",
1263                    SPR_NOACCESS, SPR_NOACCESS,
1264                    SPR_NOACCESS, SPR_NOACCESS,
1265                    &spr_read_generic, &spr_write_generic,
1266                    0);
1267#endif /* !CONFIG_USER_ONLY */
1268}
1269
1270static void gen_spr_iamr(CPUPPCState *env)
1271{
1272#ifndef CONFIG_USER_ONLY
1273    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1274                        SPR_NOACCESS, SPR_NOACCESS,
1275                        &spr_read_generic, &spr_write_iamr,
1276                        &spr_read_generic, &spr_write_generic,
1277                        KVM_REG_PPC_IAMR, 0);
1278#endif /* !CONFIG_USER_ONLY */
1279}
1280#endif /* TARGET_PPC64 */
1281
1282#ifndef CONFIG_USER_ONLY
1283static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1284{
1285    gen_helper_fixup_thrm(cpu_env);
1286    gen_load_spr(cpu_gpr[gprn], sprn);
1287    spr_load_dump_spr(sprn);
1288}
1289#endif /* !CONFIG_USER_ONLY */
1290
1291static void gen_spr_thrm(CPUPPCState *env)
1292{
1293    /* Thermal management */
1294    /* XXX : not implemented */
1295    spr_register(env, SPR_THRM1, "THRM1",
1296                 SPR_NOACCESS, SPR_NOACCESS,
1297                 &spr_read_thrm, &spr_write_generic,
1298                 0x00000000);
1299    /* XXX : not implemented */
1300    spr_register(env, SPR_THRM2, "THRM2",
1301                 SPR_NOACCESS, SPR_NOACCESS,
1302                 &spr_read_thrm, &spr_write_generic,
1303                 0x00000000);
1304    /* XXX : not implemented */
1305    spr_register(env, SPR_THRM3, "THRM3",
1306                 SPR_NOACCESS, SPR_NOACCESS,
1307                 &spr_read_thrm, &spr_write_generic,
1308                 0x00000000);
1309}
1310
1311/* SPR specific to PowerPC 604 implementation */
1312static void gen_spr_604(CPUPPCState *env)
1313{
1314    /* Processor identification */
1315    spr_register(env, SPR_PIR, "PIR",
1316                 SPR_NOACCESS, SPR_NOACCESS,
1317                 &spr_read_generic, &spr_write_pir,
1318                 0x00000000);
1319    /* Breakpoints */
1320    /* XXX : not implemented */
1321    spr_register(env, SPR_IABR, "IABR",
1322                 SPR_NOACCESS, SPR_NOACCESS,
1323                 &spr_read_generic, &spr_write_generic,
1324                 0x00000000);
1325    /* XXX : not implemented */
1326    spr_register_kvm(env, SPR_DABR, "DABR",
1327                     SPR_NOACCESS, SPR_NOACCESS,
1328                     &spr_read_generic, &spr_write_generic,
1329                     KVM_REG_PPC_DABR, 0x00000000);
1330    /* Performance counters */
1331    /* XXX : not implemented */
1332    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1333                 SPR_NOACCESS, SPR_NOACCESS,
1334                 &spr_read_generic, &spr_write_generic,
1335                 0x00000000);
1336    /* XXX : not implemented */
1337    spr_register(env, SPR_7XX_PMC1, "PMC1",
1338                 SPR_NOACCESS, SPR_NOACCESS,
1339                 &spr_read_generic, &spr_write_generic,
1340                 0x00000000);
1341    /* XXX : not implemented */
1342    spr_register(env, SPR_7XX_PMC2, "PMC2",
1343                 SPR_NOACCESS, SPR_NOACCESS,
1344                 &spr_read_generic, &spr_write_generic,
1345                 0x00000000);
1346    /* XXX : not implemented */
1347    spr_register(env, SPR_7XX_SIAR, "SIAR",
1348                 SPR_NOACCESS, SPR_NOACCESS,
1349                 &spr_read_generic, SPR_NOACCESS,
1350                 0x00000000);
1351    /* XXX : not implemented */
1352    spr_register(env, SPR_SDA, "SDA",
1353                 SPR_NOACCESS, SPR_NOACCESS,
1354                 &spr_read_generic, SPR_NOACCESS,
1355                 0x00000000);
1356    /* External access control */
1357    /* XXX : not implemented */
1358    spr_register(env, SPR_EAR, "EAR",
1359                 SPR_NOACCESS, SPR_NOACCESS,
1360                 &spr_read_generic, &spr_write_generic,
1361                 0x00000000);
1362}
1363
1364/* SPR specific to PowerPC 603 implementation */
1365static void gen_spr_603(CPUPPCState *env)
1366{
1367    /* External access control */
1368    /* XXX : not implemented */
1369    spr_register(env, SPR_EAR, "EAR",
1370                 SPR_NOACCESS, SPR_NOACCESS,
1371                 &spr_read_generic, &spr_write_generic,
1372                 0x00000000);
1373    /* Breakpoints */
1374    /* XXX : not implemented */
1375    spr_register(env, SPR_IABR, "IABR",
1376                 SPR_NOACCESS, SPR_NOACCESS,
1377                 &spr_read_generic, &spr_write_generic,
1378                 0x00000000);
1379
1380}
1381
1382/* SPR specific to PowerPC G2 implementation */
1383static void gen_spr_G2(CPUPPCState *env)
1384{
1385    /* Memory base address */
1386    /* MBAR */
1387    /* XXX : not implemented */
1388    spr_register(env, SPR_MBAR, "MBAR",
1389                 SPR_NOACCESS, SPR_NOACCESS,
1390                 &spr_read_generic, &spr_write_generic,
1391                 0x00000000);
1392    /* Exception processing */
1393    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1394                 SPR_NOACCESS, SPR_NOACCESS,
1395                 &spr_read_generic, &spr_write_generic,
1396                 0x00000000);
1397    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1398                 SPR_NOACCESS, SPR_NOACCESS,
1399                 &spr_read_generic, &spr_write_generic,
1400                 0x00000000);
1401    /* Breakpoints */
1402    /* XXX : not implemented */
1403    spr_register(env, SPR_DABR, "DABR",
1404                 SPR_NOACCESS, SPR_NOACCESS,
1405                 &spr_read_generic, &spr_write_generic,
1406                 0x00000000);
1407    /* XXX : not implemented */
1408    spr_register(env, SPR_DABR2, "DABR2",
1409                 SPR_NOACCESS, SPR_NOACCESS,
1410                 &spr_read_generic, &spr_write_generic,
1411                 0x00000000);
1412    /* XXX : not implemented */
1413    spr_register(env, SPR_IABR, "IABR",
1414                 SPR_NOACCESS, SPR_NOACCESS,
1415                 &spr_read_generic, &spr_write_generic,
1416                 0x00000000);
1417    /* XXX : not implemented */
1418    spr_register(env, SPR_IABR2, "IABR2",
1419                 SPR_NOACCESS, SPR_NOACCESS,
1420                 &spr_read_generic, &spr_write_generic,
1421                 0x00000000);
1422    /* XXX : not implemented */
1423    spr_register(env, SPR_IBCR, "IBCR",
1424                 SPR_NOACCESS, SPR_NOACCESS,
1425                 &spr_read_generic, &spr_write_generic,
1426                 0x00000000);
1427    /* XXX : not implemented */
1428    spr_register(env, SPR_DBCR, "DBCR",
1429                 SPR_NOACCESS, SPR_NOACCESS,
1430                 &spr_read_generic, &spr_write_generic,
1431                 0x00000000);
1432}
1433
1434/* SPR specific to PowerPC 602 implementation */
1435static void gen_spr_602(CPUPPCState *env)
1436{
1437    /* ESA registers */
1438    /* XXX : not implemented */
1439    spr_register(env, SPR_SER, "SER",
1440                 SPR_NOACCESS, SPR_NOACCESS,
1441                 &spr_read_generic, &spr_write_generic,
1442                 0x00000000);
1443    /* XXX : not implemented */
1444    spr_register(env, SPR_SEBR, "SEBR",
1445                 SPR_NOACCESS, SPR_NOACCESS,
1446                 &spr_read_generic, &spr_write_generic,
1447                 0x00000000);
1448    /* XXX : not implemented */
1449    spr_register(env, SPR_ESASRR, "ESASRR",
1450                 SPR_NOACCESS, SPR_NOACCESS,
1451                 &spr_read_generic, &spr_write_generic,
1452                 0x00000000);
1453    /* Floating point status */
1454    /* XXX : not implemented */
1455    spr_register(env, SPR_SP, "SP",
1456                 SPR_NOACCESS, SPR_NOACCESS,
1457                 &spr_read_generic, &spr_write_generic,
1458                 0x00000000);
1459    /* XXX : not implemented */
1460    spr_register(env, SPR_LT, "LT",
1461                 SPR_NOACCESS, SPR_NOACCESS,
1462                 &spr_read_generic, &spr_write_generic,
1463                 0x00000000);
1464    /* Watchdog timer */
1465    /* XXX : not implemented */
1466    spr_register(env, SPR_TCR, "TCR",
1467                 SPR_NOACCESS, SPR_NOACCESS,
1468                 &spr_read_generic, &spr_write_generic,
1469                 0x00000000);
1470    /* Interrupt base */
1471    spr_register(env, SPR_IBR, "IBR",
1472                 SPR_NOACCESS, SPR_NOACCESS,
1473                 &spr_read_generic, &spr_write_generic,
1474                 0x00000000);
1475    /* XXX : not implemented */
1476    spr_register(env, SPR_IABR, "IABR",
1477                 SPR_NOACCESS, SPR_NOACCESS,
1478                 &spr_read_generic, &spr_write_generic,
1479                 0x00000000);
1480}
1481
1482/* SPR specific to PowerPC 601 implementation */
1483static void gen_spr_601(CPUPPCState *env)
1484{
1485    /* Multiplication/division register */
1486    /* MQ */
1487    spr_register(env, SPR_MQ, "MQ",
1488                 &spr_read_generic, &spr_write_generic,
1489                 &spr_read_generic, &spr_write_generic,
1490                 0x00000000);
1491    /* RTC registers */
1492    spr_register(env, SPR_601_RTCU, "RTCU",
1493                 SPR_NOACCESS, SPR_NOACCESS,
1494                 SPR_NOACCESS, &spr_write_601_rtcu,
1495                 0x00000000);
1496    spr_register(env, SPR_601_VRTCU, "RTCU",
1497                 &spr_read_601_rtcu, SPR_NOACCESS,
1498                 &spr_read_601_rtcu, SPR_NOACCESS,
1499                 0x00000000);
1500    spr_register(env, SPR_601_RTCL, "RTCL",
1501                 SPR_NOACCESS, SPR_NOACCESS,
1502                 SPR_NOACCESS, &spr_write_601_rtcl,
1503                 0x00000000);
1504    spr_register(env, SPR_601_VRTCL, "RTCL",
1505                 &spr_read_601_rtcl, SPR_NOACCESS,
1506                 &spr_read_601_rtcl, SPR_NOACCESS,
1507                 0x00000000);
1508    /* Timer */
1509#if 0 /* ? */
1510    spr_register(env, SPR_601_UDECR, "UDECR",
1511                 &spr_read_decr, SPR_NOACCESS,
1512                 &spr_read_decr, SPR_NOACCESS,
1513                 0x00000000);
1514#endif
1515    /* External access control */
1516    /* XXX : not implemented */
1517    spr_register(env, SPR_EAR, "EAR",
1518                 SPR_NOACCESS, SPR_NOACCESS,
1519                 &spr_read_generic, &spr_write_generic,
1520                 0x00000000);
1521    /* Memory management */
1522#if !defined(CONFIG_USER_ONLY)
1523    spr_register(env, SPR_IBAT0U, "IBAT0U",
1524                 SPR_NOACCESS, SPR_NOACCESS,
1525                 &spr_read_601_ubat, &spr_write_601_ubatu,
1526                 0x00000000);
1527    spr_register(env, SPR_IBAT0L, "IBAT0L",
1528                 SPR_NOACCESS, SPR_NOACCESS,
1529                 &spr_read_601_ubat, &spr_write_601_ubatl,
1530                 0x00000000);
1531    spr_register(env, SPR_IBAT1U, "IBAT1U",
1532                 SPR_NOACCESS, SPR_NOACCESS,
1533                 &spr_read_601_ubat, &spr_write_601_ubatu,
1534                 0x00000000);
1535    spr_register(env, SPR_IBAT1L, "IBAT1L",
1536                 SPR_NOACCESS, SPR_NOACCESS,
1537                 &spr_read_601_ubat, &spr_write_601_ubatl,
1538                 0x00000000);
1539    spr_register(env, SPR_IBAT2U, "IBAT2U",
1540                 SPR_NOACCESS, SPR_NOACCESS,
1541                 &spr_read_601_ubat, &spr_write_601_ubatu,
1542                 0x00000000);
1543    spr_register(env, SPR_IBAT2L, "IBAT2L",
1544                 SPR_NOACCESS, SPR_NOACCESS,
1545                 &spr_read_601_ubat, &spr_write_601_ubatl,
1546                 0x00000000);
1547    spr_register(env, SPR_IBAT3U, "IBAT3U",
1548                 SPR_NOACCESS, SPR_NOACCESS,
1549                 &spr_read_601_ubat, &spr_write_601_ubatu,
1550                 0x00000000);
1551    spr_register(env, SPR_IBAT3L, "IBAT3L",
1552                 SPR_NOACCESS, SPR_NOACCESS,
1553                 &spr_read_601_ubat, &spr_write_601_ubatl,
1554                 0x00000000);
1555    env->nb_BATs = 4;
1556#endif
1557}
1558
1559static void gen_spr_74xx(CPUPPCState *env)
1560{
1561    /* Processor identification */
1562    spr_register(env, SPR_PIR, "PIR",
1563                 SPR_NOACCESS, SPR_NOACCESS,
1564                 &spr_read_generic, &spr_write_pir,
1565                 0x00000000);
1566    /* XXX : not implemented */
1567    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1568                 SPR_NOACCESS, SPR_NOACCESS,
1569                 &spr_read_generic, &spr_write_generic,
1570                 0x00000000);
1571    /* XXX : not implemented */
1572    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1573                 &spr_read_ureg, SPR_NOACCESS,
1574                 &spr_read_ureg, SPR_NOACCESS,
1575                 0x00000000);
1576    /* XXX: not implemented */
1577    spr_register(env, SPR_BAMR, "BAMR",
1578                 SPR_NOACCESS, SPR_NOACCESS,
1579                 &spr_read_generic, &spr_write_generic,
1580                 0x00000000);
1581    /* XXX : not implemented */
1582    spr_register(env, SPR_MSSCR0, "MSSCR0",
1583                 SPR_NOACCESS, SPR_NOACCESS,
1584                 &spr_read_generic, &spr_write_generic,
1585                 0x00000000);
1586    /* Hardware implementation registers */
1587    /* XXX : not implemented */
1588    spr_register(env, SPR_HID0, "HID0",
1589                 SPR_NOACCESS, SPR_NOACCESS,
1590                 &spr_read_generic, &spr_write_generic,
1591                 0x00000000);
1592    /* XXX : not implemented */
1593    spr_register(env, SPR_HID1, "HID1",
1594                 SPR_NOACCESS, SPR_NOACCESS,
1595                 &spr_read_generic, &spr_write_generic,
1596                 0x00000000);
1597    /* Altivec */
1598    spr_register(env, SPR_VRSAVE, "VRSAVE",
1599                 &spr_read_generic, &spr_write_generic,
1600                 &spr_read_generic, &spr_write_generic,
1601                 0x00000000);
1602    /* XXX : not implemented */
1603    spr_register(env, SPR_L2CR, "L2CR",
1604                 SPR_NOACCESS, SPR_NOACCESS,
1605                 &spr_read_generic, spr_access_nop,
1606                 0x00000000);
1607    /* Not strictly an SPR */
1608    vscr_init(env, 0x00010000);
1609}
1610
1611static void gen_l3_ctrl(CPUPPCState *env)
1612{
1613    /* L3CR */
1614    /* XXX : not implemented */
1615    spr_register(env, SPR_L3CR, "L3CR",
1616                 SPR_NOACCESS, SPR_NOACCESS,
1617                 &spr_read_generic, &spr_write_generic,
1618                 0x00000000);
1619    /* L3ITCR0 */
1620    /* XXX : not implemented */
1621    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1622                 SPR_NOACCESS, SPR_NOACCESS,
1623                 &spr_read_generic, &spr_write_generic,
1624                 0x00000000);
1625    /* L3PM */
1626    /* XXX : not implemented */
1627    spr_register(env, SPR_L3PM, "L3PM",
1628                 SPR_NOACCESS, SPR_NOACCESS,
1629                 &spr_read_generic, &spr_write_generic,
1630                 0x00000000);
1631}
1632
1633static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1634{
1635#if !defined(CONFIG_USER_ONLY)
1636    env->nb_tlb = nb_tlbs;
1637    env->nb_ways = nb_ways;
1638    env->id_tlbs = 1;
1639    env->tlb_type = TLB_6XX;
1640    /* XXX : not implemented */
1641    spr_register(env, SPR_PTEHI, "PTEHI",
1642                 SPR_NOACCESS, SPR_NOACCESS,
1643                 &spr_read_generic, &spr_write_generic,
1644                 0x00000000);
1645    /* XXX : not implemented */
1646    spr_register(env, SPR_PTELO, "PTELO",
1647                 SPR_NOACCESS, SPR_NOACCESS,
1648                 &spr_read_generic, &spr_write_generic,
1649                 0x00000000);
1650    /* XXX : not implemented */
1651    spr_register(env, SPR_TLBMISS, "TLBMISS",
1652                 SPR_NOACCESS, SPR_NOACCESS,
1653                 &spr_read_generic, &spr_write_generic,
1654                 0x00000000);
1655#endif
1656}
1657
1658#if !defined(CONFIG_USER_ONLY)
1659static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1660{
1661    TCGv t0 = tcg_temp_new();
1662
1663    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1664    gen_store_spr(sprn, t0);
1665    tcg_temp_free(t0);
1666}
1667
1668static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1669{
1670    TCGv t0 = tcg_temp_new();
1671
1672    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1673    gen_store_spr(sprn, t0);
1674    tcg_temp_free(t0);
1675}
1676
1677static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1678{
1679    gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1680}
1681
1682static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1683{
1684    TCGv_i32 t0 = tcg_const_i32(sprn);
1685    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1686    tcg_temp_free_i32(t0);
1687}
1688static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1689{
1690    gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1691}
1692static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1693{
1694    gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1695}
1696
1697#endif
1698
1699static void gen_spr_usprg3(CPUPPCState *env)
1700{
1701    spr_register(env, SPR_USPRG3, "USPRG3",
1702                 &spr_read_ureg, SPR_NOACCESS,
1703                 &spr_read_ureg, SPR_NOACCESS,
1704                 0x00000000);
1705}
1706
1707static void gen_spr_usprgh(CPUPPCState *env)
1708{
1709    spr_register(env, SPR_USPRG4, "USPRG4",
1710                 &spr_read_ureg, SPR_NOACCESS,
1711                 &spr_read_ureg, SPR_NOACCESS,
1712                 0x00000000);
1713    spr_register(env, SPR_USPRG5, "USPRG5",
1714                 &spr_read_ureg, SPR_NOACCESS,
1715                 &spr_read_ureg, SPR_NOACCESS,
1716                 0x00000000);
1717    spr_register(env, SPR_USPRG6, "USPRG6",
1718                 &spr_read_ureg, SPR_NOACCESS,
1719                 &spr_read_ureg, SPR_NOACCESS,
1720                 0x00000000);
1721    spr_register(env, SPR_USPRG7, "USPRG7",
1722                 &spr_read_ureg, SPR_NOACCESS,
1723                 &spr_read_ureg, SPR_NOACCESS,
1724                 0x00000000);
1725}
1726
1727/* PowerPC BookE SPR */
1728static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1729{
1730    const char *ivor_names[64] = {
1731        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1732        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1733        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1734        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1735        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1736        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1737        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1738        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1739        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1740        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1741        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1742        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1743        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1744        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1745        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1746        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1747    };
1748#define SPR_BOOKE_IVORxx (-1)
1749    int ivor_sprn[64] = {
1750        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1751        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1752        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1753        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1754        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1755        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1756        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1757        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1758        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1759        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1760        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1761        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1762        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1763        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1764        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1765        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1766    };
1767    int i;
1768
1769    /* Interrupt processing */
1770    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1771                 SPR_NOACCESS, SPR_NOACCESS,
1772                 &spr_read_generic, &spr_write_generic,
1773                 0x00000000);
1774    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1775                 SPR_NOACCESS, SPR_NOACCESS,
1776                 &spr_read_generic, &spr_write_generic,
1777                 0x00000000);
1778    /* Debug */
1779    /* XXX : not implemented */
1780    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1781                 SPR_NOACCESS, SPR_NOACCESS,
1782                 &spr_read_generic, &spr_write_generic,
1783                 0x00000000);
1784    /* XXX : not implemented */
1785    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1786                 SPR_NOACCESS, SPR_NOACCESS,
1787                 &spr_read_generic, &spr_write_generic,
1788                 0x00000000);
1789    /* XXX : not implemented */
1790    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1791                 SPR_NOACCESS, SPR_NOACCESS,
1792                 &spr_read_generic, &spr_write_generic,
1793                 0x00000000);
1794    /* XXX : not implemented */
1795    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1796                 SPR_NOACCESS, SPR_NOACCESS,
1797                 &spr_read_generic, &spr_write_generic,
1798                 0x00000000);
1799    /* XXX : not implemented */
1800    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1801                 SPR_NOACCESS, SPR_NOACCESS,
1802                 &spr_read_generic, &spr_write_40x_dbcr0,
1803                 0x00000000);
1804    /* XXX : not implemented */
1805    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1806                 SPR_NOACCESS, SPR_NOACCESS,
1807                 &spr_read_generic, &spr_write_generic,
1808                 0x00000000);
1809    /* XXX : not implemented */
1810    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1811                 SPR_NOACCESS, SPR_NOACCESS,
1812                 &spr_read_generic, &spr_write_generic,
1813                 0x00000000);
1814    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1815                 SPR_NOACCESS, SPR_NOACCESS,
1816                 &spr_read_generic, &spr_write_generic,
1817                 0x00000000);
1818    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1819                 SPR_NOACCESS, SPR_NOACCESS,
1820                 &spr_read_generic, &spr_write_generic,
1821                 0x00000000);
1822    /* XXX : not implemented */
1823    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1824                 SPR_NOACCESS, SPR_NOACCESS,
1825                 &spr_read_generic, &spr_write_clear,
1826                 0x00000000);
1827    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1828                 SPR_NOACCESS, SPR_NOACCESS,
1829                 &spr_read_generic, &spr_write_generic,
1830                 0x00000000);
1831    spr_register(env, SPR_BOOKE_ESR, "ESR",
1832                 SPR_NOACCESS, SPR_NOACCESS,
1833                 &spr_read_generic, &spr_write_generic,
1834                 0x00000000);
1835    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1836                 SPR_NOACCESS, SPR_NOACCESS,
1837                 &spr_read_generic, &spr_write_excp_prefix,
1838                 0x00000000);
1839    /* Exception vectors */
1840    for (i = 0; i < 64; i++) {
1841        if (ivor_mask & (1ULL << i)) {
1842            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1843                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1844                exit(1);
1845            }
1846            spr_register(env, ivor_sprn[i], ivor_names[i],
1847                         SPR_NOACCESS, SPR_NOACCESS,
1848                         &spr_read_generic, &spr_write_excp_vector,
1849                         0x00000000);
1850        }
1851    }
1852    spr_register(env, SPR_BOOKE_PID, "PID",
1853                 SPR_NOACCESS, SPR_NOACCESS,
1854                 &spr_read_generic, &spr_write_booke_pid,
1855                 0x00000000);
1856    spr_register(env, SPR_BOOKE_TCR, "TCR",
1857                 SPR_NOACCESS, SPR_NOACCESS,
1858                 &spr_read_generic, &spr_write_booke_tcr,
1859                 0x00000000);
1860    spr_register(env, SPR_BOOKE_TSR, "TSR",
1861                 SPR_NOACCESS, SPR_NOACCESS,
1862                 &spr_read_generic, &spr_write_booke_tsr,
1863                 0x00000000);
1864    /* Timer */
1865    spr_register(env, SPR_DECR, "DECR",
1866                 SPR_NOACCESS, SPR_NOACCESS,
1867                 &spr_read_decr, &spr_write_decr,
1868                 0x00000000);
1869    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1870                 SPR_NOACCESS, SPR_NOACCESS,
1871                 SPR_NOACCESS, &spr_write_generic,
1872                 0x00000000);
1873    /* SPRGs */
1874    spr_register(env, SPR_USPRG0, "USPRG0",
1875                 &spr_read_generic, &spr_write_generic,
1876                 &spr_read_generic, &spr_write_generic,
1877                 0x00000000);
1878    spr_register(env, SPR_SPRG4, "SPRG4",
1879                 SPR_NOACCESS, SPR_NOACCESS,
1880                 &spr_read_generic, &spr_write_generic,
1881                 0x00000000);
1882    spr_register(env, SPR_SPRG5, "SPRG5",
1883                 SPR_NOACCESS, SPR_NOACCESS,
1884                 &spr_read_generic, &spr_write_generic,
1885                 0x00000000);
1886    spr_register(env, SPR_SPRG6, "SPRG6",
1887                 SPR_NOACCESS, SPR_NOACCESS,
1888                 &spr_read_generic, &spr_write_generic,
1889                 0x00000000);
1890    spr_register(env, SPR_SPRG7, "SPRG7",
1891                 SPR_NOACCESS, SPR_NOACCESS,
1892                 &spr_read_generic, &spr_write_generic,
1893                 0x00000000);
1894    spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1895                 SPR_NOACCESS, SPR_NOACCESS,
1896                 &spr_read_generic, &spr_write_generic,
1897                 0x00000000);
1898    spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1899                 SPR_NOACCESS, SPR_NOACCESS,
1900                 &spr_read_generic, &spr_write_generic,
1901                 0x00000000);
1902}
1903
1904static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1905                                   uint32_t maxsize, uint32_t flags,
1906                                   uint32_t nentries)
1907{
1908    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1909           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1910           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1911           flags | nentries;
1912}
1913
1914/* BookE 2.06 storage control registers */
1915static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1916                             uint32_t *tlbncfg, uint32_t mmucfg)
1917{
1918#if !defined(CONFIG_USER_ONLY)
1919    const char *mas_names[8] = {
1920        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1921    };
1922    int mas_sprn[8] = {
1923        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1924        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1925    };
1926    int i;
1927
1928    /* TLB assist registers */
1929    /* XXX : not implemented */
1930    for (i = 0; i < 8; i++) {
1931        void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1932            &spr_write_generic32;
1933        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1934            uea_write = &spr_write_generic;
1935        }
1936        if (mas_mask & (1 << i)) {
1937            spr_register(env, mas_sprn[i], mas_names[i],
1938                         SPR_NOACCESS, SPR_NOACCESS,
1939                         &spr_read_generic, uea_write,
1940                         0x00000000);
1941        }
1942    }
1943    if (env->nb_pids > 1) {
1944        /* XXX : not implemented */
1945        spr_register(env, SPR_BOOKE_PID1, "PID1",
1946                     SPR_NOACCESS, SPR_NOACCESS,
1947                     &spr_read_generic, &spr_write_booke_pid,
1948                     0x00000000);
1949    }
1950    if (env->nb_pids > 2) {
1951        /* XXX : not implemented */
1952        spr_register(env, SPR_BOOKE_PID2, "PID2",
1953                     SPR_NOACCESS, SPR_NOACCESS,
1954                     &spr_read_generic, &spr_write_booke_pid,
1955                     0x00000000);
1956    }
1957
1958    spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1959                 SPR_NOACCESS, SPR_NOACCESS,
1960                 &spr_read_generic, &spr_write_eplc,
1961                 0x00000000);
1962    spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1963                 SPR_NOACCESS, SPR_NOACCESS,
1964                 &spr_read_generic, &spr_write_epsc,
1965                 0x00000000);
1966
1967    /* XXX : not implemented */
1968    spr_register(env, SPR_MMUCFG, "MMUCFG",
1969                 SPR_NOACCESS, SPR_NOACCESS,
1970                 &spr_read_generic, SPR_NOACCESS,
1971                 mmucfg);
1972    switch (env->nb_ways) {
1973    case 4:
1974        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1975                     SPR_NOACCESS, SPR_NOACCESS,
1976                     &spr_read_generic, SPR_NOACCESS,
1977                     tlbncfg[3]);
1978        /* Fallthru */
1979    case 3:
1980        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1981                     SPR_NOACCESS, SPR_NOACCESS,
1982                     &spr_read_generic, SPR_NOACCESS,
1983                     tlbncfg[2]);
1984        /* Fallthru */
1985    case 2:
1986        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1987                     SPR_NOACCESS, SPR_NOACCESS,
1988                     &spr_read_generic, SPR_NOACCESS,
1989                     tlbncfg[1]);
1990        /* Fallthru */
1991    case 1:
1992        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1993                     SPR_NOACCESS, SPR_NOACCESS,
1994                     &spr_read_generic, SPR_NOACCESS,
1995                     tlbncfg[0]);
1996        /* Fallthru */
1997    case 0:
1998    default:
1999        break;
2000    }
2001#endif
2002
2003    gen_spr_usprgh(env);
2004}
2005
2006/* SPR specific to PowerPC 440 implementation */
2007static void gen_spr_440(CPUPPCState *env)
2008{
2009    /* Cache control */
2010    /* XXX : not implemented */
2011    spr_register(env, SPR_440_DNV0, "DNV0",
2012                 SPR_NOACCESS, SPR_NOACCESS,
2013                 &spr_read_generic, &spr_write_generic,
2014                 0x00000000);
2015    /* XXX : not implemented */
2016    spr_register(env, SPR_440_DNV1, "DNV1",
2017                 SPR_NOACCESS, SPR_NOACCESS,
2018                 &spr_read_generic, &spr_write_generic,
2019                 0x00000000);
2020    /* XXX : not implemented */
2021    spr_register(env, SPR_440_DNV2, "DNV2",
2022                 SPR_NOACCESS, SPR_NOACCESS,
2023                 &spr_read_generic, &spr_write_generic,
2024                 0x00000000);
2025    /* XXX : not implemented */
2026    spr_register(env, SPR_440_DNV3, "DNV3",
2027                 SPR_NOACCESS, SPR_NOACCESS,
2028                 &spr_read_generic, &spr_write_generic,
2029                 0x00000000);
2030    /* XXX : not implemented */
2031    spr_register(env, SPR_440_DTV0, "DTV0",
2032                 SPR_NOACCESS, SPR_NOACCESS,
2033                 &spr_read_generic, &spr_write_generic,
2034                 0x00000000);
2035    /* XXX : not implemented */
2036    spr_register(env, SPR_440_DTV1, "DTV1",
2037                 SPR_NOACCESS, SPR_NOACCESS,
2038                 &spr_read_generic, &spr_write_generic,
2039                 0x00000000);
2040    /* XXX : not implemented */
2041    spr_register(env, SPR_440_DTV2, "DTV2",
2042                 SPR_NOACCESS, SPR_NOACCESS,
2043                 &spr_read_generic, &spr_write_generic,
2044                 0x00000000);
2045    /* XXX : not implemented */
2046    spr_register(env, SPR_440_DTV3, "DTV3",
2047                 SPR_NOACCESS, SPR_NOACCESS,
2048                 &spr_read_generic, &spr_write_generic,
2049                 0x00000000);
2050    /* XXX : not implemented */
2051    spr_register(env, SPR_440_DVLIM, "DVLIM",
2052                 SPR_NOACCESS, SPR_NOACCESS,
2053                 &spr_read_generic, &spr_write_generic,
2054                 0x00000000);
2055    /* XXX : not implemented */
2056    spr_register(env, SPR_440_INV0, "INV0",
2057                 SPR_NOACCESS, SPR_NOACCESS,
2058                 &spr_read_generic, &spr_write_generic,
2059                 0x00000000);
2060    /* XXX : not implemented */
2061    spr_register(env, SPR_440_INV1, "INV1",
2062                 SPR_NOACCESS, SPR_NOACCESS,
2063                 &spr_read_generic, &spr_write_generic,
2064                 0x00000000);
2065    /* XXX : not implemented */
2066    spr_register(env, SPR_440_INV2, "INV2",
2067                 SPR_NOACCESS, SPR_NOACCESS,
2068                 &spr_read_generic, &spr_write_generic,
2069                 0x00000000);
2070    /* XXX : not implemented */
2071    spr_register(env, SPR_440_INV3, "INV3",
2072                 SPR_NOACCESS, SPR_NOACCESS,
2073                 &spr_read_generic, &spr_write_generic,
2074                 0x00000000);
2075    /* XXX : not implemented */
2076    spr_register(env, SPR_440_ITV0, "ITV0",
2077                 SPR_NOACCESS, SPR_NOACCESS,
2078                 &spr_read_generic, &spr_write_generic,
2079                 0x00000000);
2080    /* XXX : not implemented */
2081    spr_register(env, SPR_440_ITV1, "ITV1",
2082                 SPR_NOACCESS, SPR_NOACCESS,
2083                 &spr_read_generic, &spr_write_generic,
2084                 0x00000000);
2085    /* XXX : not implemented */
2086    spr_register(env, SPR_440_ITV2, "ITV2",
2087                 SPR_NOACCESS, SPR_NOACCESS,
2088                 &spr_read_generic, &spr_write_generic,
2089                 0x00000000);
2090    /* XXX : not implemented */
2091    spr_register(env, SPR_440_ITV3, "ITV3",
2092                 SPR_NOACCESS, SPR_NOACCESS,
2093                 &spr_read_generic, &spr_write_generic,
2094                 0x00000000);
2095    /* XXX : not implemented */
2096    spr_register(env, SPR_440_IVLIM, "IVLIM",
2097                 SPR_NOACCESS, SPR_NOACCESS,
2098                 &spr_read_generic, &spr_write_generic,
2099                 0x00000000);
2100    /* Cache debug */
2101    /* XXX : not implemented */
2102    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2103                 SPR_NOACCESS, SPR_NOACCESS,
2104                 &spr_read_generic, SPR_NOACCESS,
2105                 0x00000000);
2106    /* XXX : not implemented */
2107    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2108                 SPR_NOACCESS, SPR_NOACCESS,
2109                 &spr_read_generic, SPR_NOACCESS,
2110                 0x00000000);
2111    /* XXX : not implemented */
2112    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2113                 SPR_NOACCESS, SPR_NOACCESS,
2114                 &spr_read_generic, SPR_NOACCESS,
2115                 0x00000000);
2116    /* XXX : not implemented */
2117    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2118                 SPR_NOACCESS, SPR_NOACCESS,
2119                 &spr_read_generic, SPR_NOACCESS,
2120                 0x00000000);
2121    /* XXX : not implemented */
2122    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2123                 SPR_NOACCESS, SPR_NOACCESS,
2124                 &spr_read_generic, SPR_NOACCESS,
2125                 0x00000000);
2126    /* XXX : not implemented */
2127    spr_register(env, SPR_440_DBDR, "DBDR",
2128                 SPR_NOACCESS, SPR_NOACCESS,
2129                 &spr_read_generic, &spr_write_generic,
2130                 0x00000000);
2131    /* Processor control */
2132    spr_register(env, SPR_4xx_CCR0, "CCR0",
2133                 SPR_NOACCESS, SPR_NOACCESS,
2134                 &spr_read_generic, &spr_write_generic,
2135                 0x00000000);
2136    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2137                 SPR_NOACCESS, SPR_NOACCESS,
2138                 &spr_read_generic, SPR_NOACCESS,
2139                 0x00000000);
2140    /* Storage control */
2141    spr_register(env, SPR_440_MMUCR, "MMUCR",
2142                 SPR_NOACCESS, SPR_NOACCESS,
2143                 &spr_read_generic, &spr_write_generic,
2144                 0x00000000);
2145}
2146
2147/* SPR shared between PowerPC 40x implementations */
2148static void gen_spr_40x(CPUPPCState *env)
2149{
2150    /* Cache */
2151    /* not emulated, as QEMU do not emulate caches */
2152    spr_register(env, SPR_40x_DCCR, "DCCR",
2153                 SPR_NOACCESS, SPR_NOACCESS,
2154                 &spr_read_generic, &spr_write_generic,
2155                 0x00000000);
2156    /* not emulated, as QEMU do not emulate caches */
2157    spr_register(env, SPR_40x_ICCR, "ICCR",
2158                 SPR_NOACCESS, SPR_NOACCESS,
2159                 &spr_read_generic, &spr_write_generic,
2160                 0x00000000);
2161    /* not emulated, as QEMU do not emulate caches */
2162    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2163                 SPR_NOACCESS, SPR_NOACCESS,
2164                 &spr_read_generic, SPR_NOACCESS,
2165                 0x00000000);
2166    /* Exception */
2167    spr_register(env, SPR_40x_DEAR, "DEAR",
2168                 SPR_NOACCESS, SPR_NOACCESS,
2169                 &spr_read_generic, &spr_write_generic,
2170                 0x00000000);
2171    spr_register(env, SPR_40x_ESR, "ESR",
2172                 SPR_NOACCESS, SPR_NOACCESS,
2173                 &spr_read_generic, &spr_write_generic,
2174                 0x00000000);
2175    spr_register(env, SPR_40x_EVPR, "EVPR",
2176                 SPR_NOACCESS, SPR_NOACCESS,
2177                 &spr_read_generic, &spr_write_excp_prefix,
2178                 0x00000000);
2179    spr_register(env, SPR_40x_SRR2, "SRR2",
2180                 &spr_read_generic, &spr_write_generic,
2181                 &spr_read_generic, &spr_write_generic,
2182                 0x00000000);
2183    spr_register(env, SPR_40x_SRR3, "SRR3",
2184                 &spr_read_generic, &spr_write_generic,
2185                 &spr_read_generic, &spr_write_generic,
2186                 0x00000000);
2187    /* Timers */
2188    spr_register(env, SPR_40x_PIT, "PIT",
2189                 SPR_NOACCESS, SPR_NOACCESS,
2190                 &spr_read_40x_pit, &spr_write_40x_pit,
2191                 0x00000000);
2192    spr_register(env, SPR_40x_TCR, "TCR",
2193                 SPR_NOACCESS, SPR_NOACCESS,
2194                 &spr_read_generic, &spr_write_booke_tcr,
2195                 0x00000000);
2196    spr_register(env, SPR_40x_TSR, "TSR",
2197                 SPR_NOACCESS, SPR_NOACCESS,
2198                 &spr_read_generic, &spr_write_booke_tsr,
2199                 0x00000000);
2200}
2201
2202/* SPR specific to PowerPC 405 implementation */
2203static void gen_spr_405(CPUPPCState *env)
2204{
2205    /* MMU */
2206    spr_register(env, SPR_40x_PID, "PID",
2207                 SPR_NOACCESS, SPR_NOACCESS,
2208                 &spr_read_generic, &spr_write_generic,
2209                 0x00000000);
2210    spr_register(env, SPR_4xx_CCR0, "CCR0",
2211                 SPR_NOACCESS, SPR_NOACCESS,
2212                 &spr_read_generic, &spr_write_generic,
2213                 0x00700000);
2214    /* Debug interface */
2215    /* XXX : not implemented */
2216    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2217                 SPR_NOACCESS, SPR_NOACCESS,
2218                 &spr_read_generic, &spr_write_40x_dbcr0,
2219                 0x00000000);
2220    /* XXX : not implemented */
2221    spr_register(env, SPR_405_DBCR1, "DBCR1",
2222                 SPR_NOACCESS, SPR_NOACCESS,
2223                 &spr_read_generic, &spr_write_generic,
2224                 0x00000000);
2225    /* XXX : not implemented */
2226    spr_register(env, SPR_40x_DBSR, "DBSR",
2227                 SPR_NOACCESS, SPR_NOACCESS,
2228                 &spr_read_generic, &spr_write_clear,
2229                 /* Last reset was system reset */
2230                 0x00000300);
2231    /* XXX : not implemented */
2232    spr_register(env, SPR_40x_DAC1, "DAC1",
2233                 SPR_NOACCESS, SPR_NOACCESS,
2234                 &spr_read_generic, &spr_write_generic,
2235                 0x00000000);
2236    spr_register(env, SPR_40x_DAC2, "DAC2",
2237                 SPR_NOACCESS, SPR_NOACCESS,
2238                 &spr_read_generic, &spr_write_generic,
2239                 0x00000000);
2240    /* XXX : not implemented */
2241    spr_register(env, SPR_405_DVC1, "DVC1",
2242                 SPR_NOACCESS, SPR_NOACCESS,
2243                 &spr_read_generic, &spr_write_generic,
2244                 0x00000000);
2245    /* XXX : not implemented */
2246    spr_register(env, SPR_405_DVC2, "DVC2",
2247                 SPR_NOACCESS, SPR_NOACCESS,
2248                 &spr_read_generic, &spr_write_generic,
2249                 0x00000000);
2250    /* XXX : not implemented */
2251    spr_register(env, SPR_40x_IAC1, "IAC1",
2252                 SPR_NOACCESS, SPR_NOACCESS,
2253                 &spr_read_generic, &spr_write_generic,
2254                 0x00000000);
2255    spr_register(env, SPR_40x_IAC2, "IAC2",
2256                 SPR_NOACCESS, SPR_NOACCESS,
2257                 &spr_read_generic, &spr_write_generic,
2258                 0x00000000);
2259    /* XXX : not implemented */
2260    spr_register(env, SPR_405_IAC3, "IAC3",
2261                 SPR_NOACCESS, SPR_NOACCESS,
2262                 &spr_read_generic, &spr_write_generic,
2263                 0x00000000);
2264    /* XXX : not implemented */
2265    spr_register(env, SPR_405_IAC4, "IAC4",
2266                 SPR_NOACCESS, SPR_NOACCESS,
2267                 &spr_read_generic, &spr_write_generic,
2268                 0x00000000);
2269    /* Storage control */
2270    /* XXX: TODO: not implemented */
2271    spr_register(env, SPR_405_SLER, "SLER",
2272                 SPR_NOACCESS, SPR_NOACCESS,
2273                 &spr_read_generic, &spr_write_40x_sler,
2274                 0x00000000);
2275    spr_register(env, SPR_40x_ZPR, "ZPR",
2276                 SPR_NOACCESS, SPR_NOACCESS,
2277                 &spr_read_generic, &spr_write_generic,
2278                 0x00000000);
2279    /* XXX : not implemented */
2280    spr_register(env, SPR_405_SU0R, "SU0R",
2281                 SPR_NOACCESS, SPR_NOACCESS,
2282                 &spr_read_generic, &spr_write_generic,
2283                 0x00000000);
2284    /* SPRG */
2285    spr_register(env, SPR_USPRG0, "USPRG0",
2286                 &spr_read_ureg, SPR_NOACCESS,
2287                 &spr_read_ureg, SPR_NOACCESS,
2288                 0x00000000);
2289    spr_register(env, SPR_SPRG4, "SPRG4",
2290                 SPR_NOACCESS, SPR_NOACCESS,
2291                 &spr_read_generic, &spr_write_generic,
2292                 0x00000000);
2293    spr_register(env, SPR_SPRG5, "SPRG5",
2294                 SPR_NOACCESS, SPR_NOACCESS,
2295                 spr_read_generic, &spr_write_generic,
2296                 0x00000000);
2297    spr_register(env, SPR_SPRG6, "SPRG6",
2298                 SPR_NOACCESS, SPR_NOACCESS,
2299                 spr_read_generic, &spr_write_generic,
2300                 0x00000000);
2301    spr_register(env, SPR_SPRG7, "SPRG7",
2302                 SPR_NOACCESS, SPR_NOACCESS,
2303                 spr_read_generic, &spr_write_generic,
2304                 0x00000000);
2305    gen_spr_usprgh(env);
2306}
2307
2308/* SPR shared between PowerPC 401 & 403 implementations */
2309static void gen_spr_401_403(CPUPPCState *env)
2310{
2311    /* Time base */
2312    spr_register(env, SPR_403_VTBL,  "TBL",
2313                 &spr_read_tbl, SPR_NOACCESS,
2314                 &spr_read_tbl, SPR_NOACCESS,
2315                 0x00000000);
2316    spr_register(env, SPR_403_TBL,   "TBL",
2317                 SPR_NOACCESS, SPR_NOACCESS,
2318                 SPR_NOACCESS, &spr_write_tbl,
2319                 0x00000000);
2320    spr_register(env, SPR_403_VTBU,  "TBU",
2321                 &spr_read_tbu, SPR_NOACCESS,
2322                 &spr_read_tbu, SPR_NOACCESS,
2323                 0x00000000);
2324    spr_register(env, SPR_403_TBU,   "TBU",
2325                 SPR_NOACCESS, SPR_NOACCESS,
2326                 SPR_NOACCESS, &spr_write_tbu,
2327                 0x00000000);
2328    /* Debug */
2329    /* not emulated, as QEMU do not emulate caches */
2330    spr_register(env, SPR_403_CDBCR, "CDBCR",
2331                 SPR_NOACCESS, SPR_NOACCESS,
2332                 &spr_read_generic, &spr_write_generic,
2333                 0x00000000);
2334}
2335
2336/* SPR specific to PowerPC 401 implementation */
2337static void gen_spr_401(CPUPPCState *env)
2338{
2339    /* Debug interface */
2340    /* XXX : not implemented */
2341    spr_register(env, SPR_40x_DBCR0, "DBCR",
2342                 SPR_NOACCESS, SPR_NOACCESS,
2343                 &spr_read_generic, &spr_write_40x_dbcr0,
2344                 0x00000000);
2345    /* XXX : not implemented */
2346    spr_register(env, SPR_40x_DBSR, "DBSR",
2347                 SPR_NOACCESS, SPR_NOACCESS,
2348                 &spr_read_generic, &spr_write_clear,
2349                 /* Last reset was system reset */
2350                 0x00000300);
2351    /* XXX : not implemented */
2352    spr_register(env, SPR_40x_DAC1, "DAC",
2353                 SPR_NOACCESS, SPR_NOACCESS,
2354                 &spr_read_generic, &spr_write_generic,
2355                 0x00000000);
2356    /* XXX : not implemented */
2357    spr_register(env, SPR_40x_IAC1, "IAC",
2358                 SPR_NOACCESS, SPR_NOACCESS,
2359                 &spr_read_generic, &spr_write_generic,
2360                 0x00000000);
2361    /* Storage control */
2362    /* XXX: TODO: not implemented */
2363    spr_register(env, SPR_405_SLER, "SLER",
2364                 SPR_NOACCESS, SPR_NOACCESS,
2365                 &spr_read_generic, &spr_write_40x_sler,
2366                 0x00000000);
2367    /* not emulated, as QEMU never does speculative access */
2368    spr_register(env, SPR_40x_SGR, "SGR",
2369                 SPR_NOACCESS, SPR_NOACCESS,
2370                 &spr_read_generic, &spr_write_generic,
2371                 0xFFFFFFFF);
2372    /* not emulated, as QEMU do not emulate caches */
2373    spr_register(env, SPR_40x_DCWR, "DCWR",
2374                 SPR_NOACCESS, SPR_NOACCESS,
2375                 &spr_read_generic, &spr_write_generic,
2376                 0x00000000);
2377}
2378
2379static void gen_spr_401x2(CPUPPCState *env)
2380{
2381    gen_spr_401(env);
2382    spr_register(env, SPR_40x_PID, "PID",
2383                 SPR_NOACCESS, SPR_NOACCESS,
2384                 &spr_read_generic, &spr_write_generic,
2385                 0x00000000);
2386    spr_register(env, SPR_40x_ZPR, "ZPR",
2387                 SPR_NOACCESS, SPR_NOACCESS,
2388                 &spr_read_generic, &spr_write_generic,
2389                 0x00000000);
2390}
2391
2392/* SPR specific to PowerPC 403 implementation */
2393static void gen_spr_403(CPUPPCState *env)
2394{
2395    /* Debug interface */
2396    /* XXX : not implemented */
2397    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2398                 SPR_NOACCESS, SPR_NOACCESS,
2399                 &spr_read_generic, &spr_write_40x_dbcr0,
2400                 0x00000000);
2401    /* XXX : not implemented */
2402    spr_register(env, SPR_40x_DBSR, "DBSR",
2403                 SPR_NOACCESS, SPR_NOACCESS,
2404                 &spr_read_generic, &spr_write_clear,
2405                 /* Last reset was system reset */
2406                 0x00000300);
2407    /* XXX : not implemented */
2408    spr_register(env, SPR_40x_DAC1, "DAC1",
2409                 SPR_NOACCESS, SPR_NOACCESS,
2410                 &spr_read_generic, &spr_write_generic,
2411                 0x00000000);
2412    /* XXX : not implemented */
2413    spr_register(env, SPR_40x_DAC2, "DAC2",
2414                 SPR_NOACCESS, SPR_NOACCESS,
2415                 &spr_read_generic, &spr_write_generic,
2416                 0x00000000);
2417    /* XXX : not implemented */
2418    spr_register(env, SPR_40x_IAC1, "IAC1",
2419                 SPR_NOACCESS, SPR_NOACCESS,
2420                 &spr_read_generic, &spr_write_generic,
2421                 0x00000000);
2422    /* XXX : not implemented */
2423    spr_register(env, SPR_40x_IAC2, "IAC2",
2424                 SPR_NOACCESS, SPR_NOACCESS,
2425                 &spr_read_generic, &spr_write_generic,
2426                 0x00000000);
2427}
2428
2429static void gen_spr_403_real(CPUPPCState *env)
2430{
2431    spr_register(env, SPR_403_PBL1,  "PBL1",
2432                 SPR_NOACCESS, SPR_NOACCESS,
2433                 &spr_read_403_pbr, &spr_write_403_pbr,
2434                 0x00000000);
2435    spr_register(env, SPR_403_PBU1,  "PBU1",
2436                 SPR_NOACCESS, SPR_NOACCESS,
2437                 &spr_read_403_pbr, &spr_write_403_pbr,
2438                 0x00000000);
2439    spr_register(env, SPR_403_PBL2,  "PBL2",
2440                 SPR_NOACCESS, SPR_NOACCESS,
2441                 &spr_read_403_pbr, &spr_write_403_pbr,
2442                 0x00000000);
2443    spr_register(env, SPR_403_PBU2,  "PBU2",
2444                 SPR_NOACCESS, SPR_NOACCESS,
2445                 &spr_read_403_pbr, &spr_write_403_pbr,
2446                 0x00000000);
2447}
2448
2449static void gen_spr_403_mmu(CPUPPCState *env)
2450{
2451    /* MMU */
2452    spr_register(env, SPR_40x_PID, "PID",
2453                 SPR_NOACCESS, SPR_NOACCESS,
2454                 &spr_read_generic, &spr_write_generic,
2455                 0x00000000);
2456    spr_register(env, SPR_40x_ZPR, "ZPR",
2457                 SPR_NOACCESS, SPR_NOACCESS,
2458                 &spr_read_generic, &spr_write_generic,
2459                 0x00000000);
2460}
2461
2462/* SPR specific to PowerPC compression coprocessor extension */
2463static void gen_spr_compress(CPUPPCState *env)
2464{
2465    /* XXX : not implemented */
2466    spr_register(env, SPR_401_SKR, "SKR",
2467                 SPR_NOACCESS, SPR_NOACCESS,
2468                 &spr_read_generic, &spr_write_generic,
2469                 0x00000000);
2470}
2471
2472static void gen_spr_5xx_8xx(CPUPPCState *env)
2473{
2474    /* Exception processing */
2475    spr_register_kvm(env, SPR_DSISR, "DSISR",
2476                     SPR_NOACCESS, SPR_NOACCESS,
2477                     &spr_read_generic, &spr_write_generic,
2478                     KVM_REG_PPC_DSISR, 0x00000000);
2479    spr_register_kvm(env, SPR_DAR, "DAR",
2480                     SPR_NOACCESS, SPR_NOACCESS,
2481                     &spr_read_generic, &spr_write_generic,
2482                     KVM_REG_PPC_DAR, 0x00000000);
2483    /* Timer */
2484    spr_register(env, SPR_DECR, "DECR",
2485                 SPR_NOACCESS, SPR_NOACCESS,
2486                 &spr_read_decr, &spr_write_decr,
2487                 0x00000000);
2488    /* XXX : not implemented */
2489    spr_register(env, SPR_MPC_EIE, "EIE",
2490                 SPR_NOACCESS, SPR_NOACCESS,
2491                 &spr_read_generic, &spr_write_generic,
2492                 0x00000000);
2493    /* XXX : not implemented */
2494    spr_register(env, SPR_MPC_EID, "EID",
2495                 SPR_NOACCESS, SPR_NOACCESS,
2496                 &spr_read_generic, &spr_write_generic,
2497                 0x00000000);
2498    /* XXX : not implemented */
2499    spr_register(env, SPR_MPC_NRI, "NRI",
2500                 SPR_NOACCESS, SPR_NOACCESS,
2501                 &spr_read_generic, &spr_write_generic,
2502                 0x00000000);
2503    /* XXX : not implemented */
2504    spr_register(env, SPR_MPC_CMPA, "CMPA",
2505                 SPR_NOACCESS, SPR_NOACCESS,
2506                 &spr_read_generic, &spr_write_generic,
2507                 0x00000000);
2508    /* XXX : not implemented */
2509    spr_register(env, SPR_MPC_CMPB, "CMPB",
2510                 SPR_NOACCESS, SPR_NOACCESS,
2511                 &spr_read_generic, &spr_write_generic,
2512                 0x00000000);
2513    /* XXX : not implemented */
2514    spr_register(env, SPR_MPC_CMPC, "CMPC",
2515                 SPR_NOACCESS, SPR_NOACCESS,
2516                 &spr_read_generic, &spr_write_generic,
2517                 0x00000000);
2518    /* XXX : not implemented */
2519    spr_register(env, SPR_MPC_CMPD, "CMPD",
2520                 SPR_NOACCESS, SPR_NOACCESS,
2521                 &spr_read_generic, &spr_write_generic,
2522                 0x00000000);
2523    /* XXX : not implemented */
2524    spr_register(env, SPR_MPC_ECR, "ECR",
2525                 SPR_NOACCESS, SPR_NOACCESS,
2526                 &spr_read_generic, &spr_write_generic,
2527                 0x00000000);
2528    /* XXX : not implemented */
2529    spr_register(env, SPR_MPC_DER, "DER",
2530                 SPR_NOACCESS, SPR_NOACCESS,
2531                 &spr_read_generic, &spr_write_generic,
2532                 0x00000000);
2533    /* XXX : not implemented */
2534    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2535                 SPR_NOACCESS, SPR_NOACCESS,
2536                 &spr_read_generic, &spr_write_generic,
2537                 0x00000000);
2538    /* XXX : not implemented */
2539    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2540                 SPR_NOACCESS, SPR_NOACCESS,
2541                 &spr_read_generic, &spr_write_generic,
2542                 0x00000000);
2543    /* XXX : not implemented */
2544    spr_register(env, SPR_MPC_CMPE, "CMPE",
2545                 SPR_NOACCESS, SPR_NOACCESS,
2546                 &spr_read_generic, &spr_write_generic,
2547                 0x00000000);
2548    /* XXX : not implemented */
2549    spr_register(env, SPR_MPC_CMPF, "CMPF",
2550                 SPR_NOACCESS, SPR_NOACCESS,
2551                 &spr_read_generic, &spr_write_generic,
2552                 0x00000000);
2553    /* XXX : not implemented */
2554    spr_register(env, SPR_MPC_CMPG, "CMPG",
2555                 SPR_NOACCESS, SPR_NOACCESS,
2556                 &spr_read_generic, &spr_write_generic,
2557                 0x00000000);
2558    /* XXX : not implemented */
2559    spr_register(env, SPR_MPC_CMPH, "CMPH",
2560                 SPR_NOACCESS, SPR_NOACCESS,
2561                 &spr_read_generic, &spr_write_generic,
2562                 0x00000000);
2563    /* XXX : not implemented */
2564    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2565                 SPR_NOACCESS, SPR_NOACCESS,
2566                 &spr_read_generic, &spr_write_generic,
2567                 0x00000000);
2568    /* XXX : not implemented */
2569    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2570                 SPR_NOACCESS, SPR_NOACCESS,
2571                 &spr_read_generic, &spr_write_generic,
2572                 0x00000000);
2573    /* XXX : not implemented */
2574    spr_register(env, SPR_MPC_BAR, "BAR",
2575                 SPR_NOACCESS, SPR_NOACCESS,
2576                 &spr_read_generic, &spr_write_generic,
2577                 0x00000000);
2578    /* XXX : not implemented */
2579    spr_register(env, SPR_MPC_DPDR, "DPDR",
2580                 SPR_NOACCESS, SPR_NOACCESS,
2581                 &spr_read_generic, &spr_write_generic,
2582                 0x00000000);
2583    /* XXX : not implemented */
2584    spr_register(env, SPR_MPC_IMMR, "IMMR",
2585                 SPR_NOACCESS, SPR_NOACCESS,
2586                 &spr_read_generic, &spr_write_generic,
2587                 0x00000000);
2588}
2589
2590static void gen_spr_5xx(CPUPPCState *env)
2591{
2592    /* XXX : not implemented */
2593    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2594                 SPR_NOACCESS, SPR_NOACCESS,
2595                 &spr_read_generic, &spr_write_generic,
2596                 0x00000000);
2597    /* XXX : not implemented */
2598    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2599                 SPR_NOACCESS, SPR_NOACCESS,
2600                 &spr_read_generic, &spr_write_generic,
2601                 0x00000000);
2602    /* XXX : not implemented */
2603    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2604                 SPR_NOACCESS, SPR_NOACCESS,
2605                 &spr_read_generic, &spr_write_generic,
2606                 0x00000000);
2607    /* XXX : not implemented */
2608    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2609                 SPR_NOACCESS, SPR_NOACCESS,
2610                 &spr_read_generic, &spr_write_generic,
2611                 0x00000000);
2612    /* XXX : not implemented */
2613    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2614                 SPR_NOACCESS, SPR_NOACCESS,
2615                 &spr_read_generic, &spr_write_generic,
2616                 0x00000000);
2617    /* XXX : not implemented */
2618    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2619                 SPR_NOACCESS, SPR_NOACCESS,
2620                 &spr_read_generic, &spr_write_generic,
2621                 0x00000000);
2622    /* XXX : not implemented */
2623    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2624                 SPR_NOACCESS, SPR_NOACCESS,
2625                 &spr_read_generic, &spr_write_generic,
2626                 0x00000000);
2627    /* XXX : not implemented */
2628    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2629                 SPR_NOACCESS, SPR_NOACCESS,
2630                 &spr_read_generic, &spr_write_generic,
2631                 0x00000000);
2632    /* XXX : not implemented */
2633    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2634                 SPR_NOACCESS, SPR_NOACCESS,
2635                 &spr_read_generic, &spr_write_generic,
2636                 0x00000000);
2637    /* XXX : not implemented */
2638    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2639                 SPR_NOACCESS, SPR_NOACCESS,
2640                 &spr_read_generic, &spr_write_generic,
2641                 0x00000000);
2642    /* XXX : not implemented */
2643    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2644                 SPR_NOACCESS, SPR_NOACCESS,
2645                 &spr_read_generic, &spr_write_generic,
2646                 0x00000000);
2647    /* XXX : not implemented */
2648    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2649                 SPR_NOACCESS, SPR_NOACCESS,
2650                 &spr_read_generic, &spr_write_generic,
2651                 0x00000000);
2652    /* XXX : not implemented */
2653    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2654                 SPR_NOACCESS, SPR_NOACCESS,
2655                 &spr_read_generic, &spr_write_generic,
2656                 0x00000000);
2657    /* XXX : not implemented */
2658    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2659                 SPR_NOACCESS, SPR_NOACCESS,
2660                 &spr_read_generic, &spr_write_generic,
2661                 0x00000000);
2662    /* XXX : not implemented */
2663    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2664                 SPR_NOACCESS, SPR_NOACCESS,
2665                 &spr_read_generic, &spr_write_generic,
2666                 0x00000000);
2667    /* XXX : not implemented */
2668    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2669                 SPR_NOACCESS, SPR_NOACCESS,
2670                 &spr_read_generic, &spr_write_generic,
2671                 0x00000000);
2672    /* XXX : not implemented */
2673    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2674                 SPR_NOACCESS, SPR_NOACCESS,
2675                 &spr_read_generic, &spr_write_generic,
2676                 0x00000000);
2677    /* XXX : not implemented */
2678    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2679                 SPR_NOACCESS, SPR_NOACCESS,
2680                 &spr_read_generic, &spr_write_generic,
2681                 0x00000000);
2682    /* XXX : not implemented */
2683    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2684                 SPR_NOACCESS, SPR_NOACCESS,
2685                 &spr_read_generic, &spr_write_generic,
2686                 0x00000000);
2687    /* XXX : not implemented */
2688    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2689                 SPR_NOACCESS, SPR_NOACCESS,
2690                 &spr_read_generic, &spr_write_generic,
2691                 0x00000000);
2692    /* XXX : not implemented */
2693    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2694                 SPR_NOACCESS, SPR_NOACCESS,
2695                 &spr_read_generic, &spr_write_generic,
2696                 0x00000000);
2697}
2698
2699static void gen_spr_8xx(CPUPPCState *env)
2700{
2701    /* XXX : not implemented */
2702    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2703                 SPR_NOACCESS, SPR_NOACCESS,
2704                 &spr_read_generic, &spr_write_generic,
2705                 0x00000000);
2706    /* XXX : not implemented */
2707    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2708                 SPR_NOACCESS, SPR_NOACCESS,
2709                 &spr_read_generic, &spr_write_generic,
2710                 0x00000000);
2711    /* XXX : not implemented */
2712    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2713                 SPR_NOACCESS, SPR_NOACCESS,
2714                 &spr_read_generic, &spr_write_generic,
2715                 0x00000000);
2716    /* XXX : not implemented */
2717    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2718                 SPR_NOACCESS, SPR_NOACCESS,
2719                 &spr_read_generic, &spr_write_generic,
2720                 0x00000000);
2721    /* XXX : not implemented */
2722    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2723                 SPR_NOACCESS, SPR_NOACCESS,
2724                 &spr_read_generic, &spr_write_generic,
2725                 0x00000000);
2726    /* XXX : not implemented */
2727    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2728                 SPR_NOACCESS, SPR_NOACCESS,
2729                 &spr_read_generic, &spr_write_generic,
2730                 0x00000000);
2731    /* XXX : not implemented */
2732    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2733                 SPR_NOACCESS, SPR_NOACCESS,
2734                 &spr_read_generic, &spr_write_generic,
2735                 0x00000000);
2736    /* XXX : not implemented */
2737    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2738                 SPR_NOACCESS, SPR_NOACCESS,
2739                 &spr_read_generic, &spr_write_generic,
2740                 0x00000000);
2741    /* XXX : not implemented */
2742    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2743                 SPR_NOACCESS, SPR_NOACCESS,
2744                 &spr_read_generic, &spr_write_generic,
2745                 0x00000000);
2746    /* XXX : not implemented */
2747    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2748                 SPR_NOACCESS, SPR_NOACCESS,
2749                 &spr_read_generic, &spr_write_generic,
2750                 0x00000000);
2751    /* XXX : not implemented */
2752    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2753                 SPR_NOACCESS, SPR_NOACCESS,
2754                 &spr_read_generic, &spr_write_generic,
2755                 0x00000000);
2756    /* XXX : not implemented */
2757    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2758                 SPR_NOACCESS, SPR_NOACCESS,
2759                 &spr_read_generic, &spr_write_generic,
2760                 0x00000000);
2761    /* XXX : not implemented */
2762    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2763                 SPR_NOACCESS, SPR_NOACCESS,
2764                 &spr_read_generic, &spr_write_generic,
2765                 0x00000000);
2766    /* XXX : not implemented */
2767    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2768                 SPR_NOACCESS, SPR_NOACCESS,
2769                 &spr_read_generic, &spr_write_generic,
2770                 0x00000000);
2771    /* XXX : not implemented */
2772    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2773                 SPR_NOACCESS, SPR_NOACCESS,
2774                 &spr_read_generic, &spr_write_generic,
2775                 0x00000000);
2776    /* XXX : not implemented */
2777    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2778                 SPR_NOACCESS, SPR_NOACCESS,
2779                 &spr_read_generic, &spr_write_generic,
2780                 0x00000000);
2781    /* XXX : not implemented */
2782    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2783                 SPR_NOACCESS, SPR_NOACCESS,
2784                 &spr_read_generic, &spr_write_generic,
2785                 0x00000000);
2786    /* XXX : not implemented */
2787    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2788                 SPR_NOACCESS, SPR_NOACCESS,
2789                 &spr_read_generic, &spr_write_generic,
2790                 0x00000000);
2791    /* XXX : not implemented */
2792    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2793                 SPR_NOACCESS, SPR_NOACCESS,
2794                 &spr_read_generic, &spr_write_generic,
2795                 0x00000000);
2796    /* XXX : not implemented */
2797    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2798                 SPR_NOACCESS, SPR_NOACCESS,
2799                 &spr_read_generic, &spr_write_generic,
2800                 0x00000000);
2801    /* XXX : not implemented */
2802    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2803                 SPR_NOACCESS, SPR_NOACCESS,
2804                 &spr_read_generic, &spr_write_generic,
2805                 0x00000000);
2806    /* XXX : not implemented */
2807    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2808                 SPR_NOACCESS, SPR_NOACCESS,
2809                 &spr_read_generic, &spr_write_generic,
2810                 0x00000000);
2811    /* XXX : not implemented */
2812    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2813                 SPR_NOACCESS, SPR_NOACCESS,
2814                 &spr_read_generic, &spr_write_generic,
2815                 0x00000000);
2816    /* XXX : not implemented */
2817    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2818                 SPR_NOACCESS, SPR_NOACCESS,
2819                 &spr_read_generic, &spr_write_generic,
2820                 0x00000000);
2821    /* XXX : not implemented */
2822    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2823                 SPR_NOACCESS, SPR_NOACCESS,
2824                 &spr_read_generic, &spr_write_generic,
2825                 0x00000000);
2826}
2827
2828/*
2829 * AMR     => SPR 29 (Power 2.04)
2830 * CTRL    => SPR 136 (Power 2.04)
2831 * CTRL    => SPR 152 (Power 2.04)
2832 * SCOMC   => SPR 276 (64 bits ?)
2833 * SCOMD   => SPR 277 (64 bits ?)
2834 * TBU40   => SPR 286 (Power 2.04 hypv)
2835 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2836 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2837 * HDSISR  => SPR 306 (Power 2.04 hypv)
2838 * HDAR    => SPR 307 (Power 2.04 hypv)
2839 * PURR    => SPR 309 (Power 2.04 hypv)
2840 * HDEC    => SPR 310 (Power 2.04 hypv)
2841 * HIOR    => SPR 311 (hypv)
2842 * RMOR    => SPR 312 (970)
2843 * HRMOR   => SPR 313 (Power 2.04 hypv)
2844 * HSRR0   => SPR 314 (Power 2.04 hypv)
2845 * HSRR1   => SPR 315 (Power 2.04 hypv)
2846 * LPIDR   => SPR 317 (970)
2847 * EPR     => SPR 702 (Power 2.04 emb)
2848 * perf    => 768-783 (Power 2.04)
2849 * perf    => 784-799 (Power 2.04)
2850 * PPR     => SPR 896 (Power 2.04)
2851 * DABRX   => 1015    (Power 2.04 hypv)
2852 * FPECR   => SPR 1022 (?)
2853 * ... and more (thermal management, performance counters, ...)
2854 */
2855
2856/*****************************************************************************/
2857/* Exception vectors models                                                  */
2858static void init_excp_4xx_real(CPUPPCState *env)
2859{
2860#if !defined(CONFIG_USER_ONLY)
2861    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2862    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2863    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2864    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2865    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2866    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2867    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2868    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2869    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2870    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2871    env->ivor_mask = 0x0000FFF0UL;
2872    env->ivpr_mask = 0xFFFF0000UL;
2873    /* Hardware reset vector */
2874    env->hreset_vector = 0xFFFFFFFCUL;
2875#endif
2876}
2877
2878static void init_excp_4xx_softmmu(CPUPPCState *env)
2879{
2880#if !defined(CONFIG_USER_ONLY)
2881    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2882    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2883    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2884    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2885    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2886    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2887    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2888    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2889    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2890    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2891    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2892    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2893    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2894    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2895    env->ivor_mask = 0x0000FFF0UL;
2896    env->ivpr_mask = 0xFFFF0000UL;
2897    /* Hardware reset vector */
2898    env->hreset_vector = 0xFFFFFFFCUL;
2899#endif
2900}
2901
2902static void init_excp_MPC5xx(CPUPPCState *env)
2903{
2904#if !defined(CONFIG_USER_ONLY)
2905    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2906    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2907    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2908    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2909    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2910    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2911    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2912    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2913    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2914    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2915    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2916    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2917    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2918    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2919    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2920    env->ivor_mask = 0x0000FFF0UL;
2921    env->ivpr_mask = 0xFFFF0000UL;
2922    /* Hardware reset vector */
2923    env->hreset_vector = 0x00000100UL;
2924#endif
2925}
2926
2927static void init_excp_MPC8xx(CPUPPCState *env)
2928{
2929#if !defined(CONFIG_USER_ONLY)
2930    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2931    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2932    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2933    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2934    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2935    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2936    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2937    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2938    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2939    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2940    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2941    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2942    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2943    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2944    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2945    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2946    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2947    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2948    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2949    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2950    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2951    env->ivor_mask = 0x0000FFF0UL;
2952    env->ivpr_mask = 0xFFFF0000UL;
2953    /* Hardware reset vector */
2954    env->hreset_vector = 0x00000100UL;
2955#endif
2956}
2957
2958static void init_excp_G2(CPUPPCState *env)
2959{
2960#if !defined(CONFIG_USER_ONLY)
2961    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2962    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2963    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2964    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2965    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2967    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2968    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2969    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2970    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2971    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2972    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2973    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2974    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2975    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2976    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2977    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2978    /* Hardware reset vector */
2979    env->hreset_vector = 0x00000100UL;
2980#endif
2981}
2982
2983static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2984{
2985#if !defined(CONFIG_USER_ONLY)
2986    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2987    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2988    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2989    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2990    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2991    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2992    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2993    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2994    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2995    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2996    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2997    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2998    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2999    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3000    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3001    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3002    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3003    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
3004    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
3005    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
3006    env->ivor_mask = 0x0000FFF7UL;
3007    env->ivpr_mask = ivpr_mask;
3008    /* Hardware reset vector */
3009    env->hreset_vector = 0xFFFFFFFCUL;
3010#endif
3011}
3012
3013static void init_excp_BookE(CPUPPCState *env)
3014{
3015#if !defined(CONFIG_USER_ONLY)
3016    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3017    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
3018    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
3019    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
3020    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3021    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
3022    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
3023    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
3024    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
3025    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
3026    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
3027    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
3028    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3029    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3030    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3031    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3032    env->ivor_mask = 0x0000FFF0UL;
3033    env->ivpr_mask = 0xFFFF0000UL;
3034    /* Hardware reset vector */
3035    env->hreset_vector = 0xFFFFFFFCUL;
3036#endif
3037}
3038
3039static void init_excp_601(CPUPPCState *env)
3040{
3041#if !defined(CONFIG_USER_ONLY)
3042    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3043    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3044    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3045    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3046    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3047    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3048    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3049    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3050    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3051    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
3052    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3053    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
3054    /* Hardware reset vector */
3055    env->hreset_vector = 0x00000100UL;
3056#endif
3057}
3058
3059static void init_excp_602(CPUPPCState *env)
3060{
3061#if !defined(CONFIG_USER_ONLY)
3062    /* XXX: exception prefix has a special behavior on 602 */
3063    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3064    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3065    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3066    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3067    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3068    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3069    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3070    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3071    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3072    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3073    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3074    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3075    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3076    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3077    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3078    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3079    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
3080    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
3081    /* Hardware reset vector */
3082    env->hreset_vector = 0x00000100UL;
3083#endif
3084}
3085
3086static void init_excp_603(CPUPPCState *env)
3087{
3088#if !defined(CONFIG_USER_ONLY)
3089    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3090    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3091    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3092    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3093    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3094    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3095    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3096    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3097    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3098    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3099    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3100    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3101    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3102    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3103    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3104    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3105    /* Hardware reset vector */
3106    env->hreset_vector = 0x00000100UL;
3107#endif
3108}
3109
3110static void init_excp_604(CPUPPCState *env)
3111{
3112#if !defined(CONFIG_USER_ONLY)
3113    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3114    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3115    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3116    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3117    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3119    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3120    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3121    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3122    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3123    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3124    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3125    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3126    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3127    /* Hardware reset vector */
3128    env->hreset_vector = 0x00000100UL;
3129#endif
3130}
3131
3132static void init_excp_7x0(CPUPPCState *env)
3133{
3134#if !defined(CONFIG_USER_ONLY)
3135    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3136    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3137    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3138    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3139    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3140    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3141    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3142    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3143    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3144    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3145    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3146    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3147    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3148    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3149    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3150    /* Hardware reset vector */
3151    env->hreset_vector = 0x00000100UL;
3152#endif
3153}
3154
3155static void init_excp_750cl(CPUPPCState *env)
3156{
3157#if !defined(CONFIG_USER_ONLY)
3158    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3159    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3160    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3161    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3162    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3163    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3164    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3165    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3166    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3167    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3168    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3169    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3170    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3171    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3172    /* Hardware reset vector */
3173    env->hreset_vector = 0x00000100UL;
3174#endif
3175}
3176
3177static void init_excp_750cx(CPUPPCState *env)
3178{
3179#if !defined(CONFIG_USER_ONLY)
3180    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3181    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3182    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3183    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3184    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3185    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3186    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3187    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3188    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3189    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3190    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3191    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3192    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3193    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3194    /* Hardware reset vector */
3195    env->hreset_vector = 0x00000100UL;
3196#endif
3197}
3198
3199/* XXX: Check if this is correct */
3200static void init_excp_7x5(CPUPPCState *env)
3201{
3202#if !defined(CONFIG_USER_ONLY)
3203    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3204    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3205    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3206    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3207    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3208    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3209    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3210    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3211    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3212    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3213    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3214    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3215    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3216    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3217    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3218    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3219    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3220    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3221    /* Hardware reset vector */
3222    env->hreset_vector = 0x00000100UL;
3223#endif
3224}
3225
3226static void init_excp_7400(CPUPPCState *env)
3227{
3228#if !defined(CONFIG_USER_ONLY)
3229    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3230    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3231    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3232    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3233    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3234    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3235    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3236    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3237    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3238    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3239    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3240    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3241    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3242    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3243    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3244    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3245    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3246    /* Hardware reset vector */
3247    env->hreset_vector = 0x00000100UL;
3248#endif
3249}
3250
3251static void init_excp_7450(CPUPPCState *env)
3252{
3253#if !defined(CONFIG_USER_ONLY)
3254    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3255    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3256    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3257    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3258    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3259    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3260    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3261    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3262    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3263    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3264    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3265    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3266    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3267    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3268    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3269    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3270    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3271    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3272    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3273    /* Hardware reset vector */
3274    env->hreset_vector = 0x00000100UL;
3275#endif
3276}
3277
3278#if defined(TARGET_PPC64)
3279static void init_excp_970(CPUPPCState *env)
3280{
3281#if !defined(CONFIG_USER_ONLY)
3282    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3283    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3284    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3285    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3286    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3287    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3288    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3289    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3290    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3291    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3292    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3293    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3294    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3295    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3296    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3297    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3298    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3299    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3300    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3301    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3302    /* Hardware reset vector */
3303    env->hreset_vector = 0x0000000000000100ULL;
3304#endif
3305}
3306
3307static void init_excp_POWER7(CPUPPCState *env)
3308{
3309#if !defined(CONFIG_USER_ONLY)
3310    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3311    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3312    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3313    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3314    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3315    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3316    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3317    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3318    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3319    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3320    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3321    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3322    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3323    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3324    env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
3325    env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
3326    env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
3327    env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3328    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3329    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3330    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
3331    /* Hardware reset vector */
3332    env->hreset_vector = 0x0000000000000100ULL;
3333#endif
3334}
3335
3336static void init_excp_POWER8(CPUPPCState *env)
3337{
3338    init_excp_POWER7(env);
3339
3340#if !defined(CONFIG_USER_ONLY)
3341    env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
3342    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
3343    env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
3344    env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3345#endif
3346}
3347
3348static void init_excp_POWER9(CPUPPCState *env)
3349{
3350    init_excp_POWER8(env);
3351
3352#if !defined(CONFIG_USER_ONLY)
3353    env->excp_vectors[POWERPC_EXCP_HVIRT]    = 0x00000EA0;
3354#endif
3355}
3356
3357#endif
3358
3359/*****************************************************************************/
3360/* Power management enable checks                                            */
3361static int check_pow_none(CPUPPCState *env)
3362{
3363    return 0;
3364}
3365
3366static int check_pow_nocheck(CPUPPCState *env)
3367{
3368    return 1;
3369}
3370
3371static int check_pow_hid0(CPUPPCState *env)
3372{
3373    if (env->spr[SPR_HID0] & 0x00E00000) {
3374        return 1;
3375    }
3376
3377    return 0;
3378}
3379
3380static int check_pow_hid0_74xx(CPUPPCState *env)
3381{
3382    if (env->spr[SPR_HID0] & 0x00600000) {
3383        return 1;
3384    }
3385
3386    return 0;
3387}
3388
3389static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3390{
3391    return true;
3392}
3393
3394#ifdef TARGET_PPC64
3395static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3396{
3397    return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3398}
3399#endif
3400
3401/*****************************************************************************/
3402/* PowerPC implementations definitions                                       */
3403
3404#define POWERPC_FAMILY(_name)                                               \
3405    static void                                                             \
3406    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3407                                                                            \
3408    static const TypeInfo                                                   \
3409    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3410        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3411        .parent = TYPE_POWERPC_CPU,                                         \
3412        .abstract = true,                                                   \
3413        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3414    };                                                                      \
3415                                                                            \
3416    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3417    {                                                                       \
3418        type_register_static(                                               \
3419            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3420    }                                                                       \
3421                                                                            \
3422    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3423                                                                            \
3424    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3425
3426static void init_proc_401(CPUPPCState *env)
3427{
3428    gen_spr_40x(env);
3429    gen_spr_401_403(env);
3430    gen_spr_401(env);
3431    init_excp_4xx_real(env);
3432    env->dcache_line_size = 32;
3433    env->icache_line_size = 32;
3434    /* Allocate hardware IRQ controller */
3435    ppc40x_irq_init(env_archcpu(env));
3436
3437    SET_FIT_PERIOD(12, 16, 20, 24);
3438    SET_WDT_PERIOD(16, 20, 24, 28);
3439}
3440
3441POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3442{
3443    DeviceClass *dc = DEVICE_CLASS(oc);
3444    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3445
3446    dc->desc = "PowerPC 401";
3447    pcc->init_proc = init_proc_401;
3448    pcc->check_pow = check_pow_nocheck;
3449    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3450                       PPC_WRTEE | PPC_DCR |
3451                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3452                       PPC_CACHE_DCBZ |
3453                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3454                       PPC_4xx_COMMON | PPC_40x_EXCP;
3455    pcc->msr_mask = (1ull << MSR_KEY) |
3456                    (1ull << MSR_POW) |
3457                    (1ull << MSR_CE) |
3458                    (1ull << MSR_ILE) |
3459                    (1ull << MSR_EE) |
3460                    (1ull << MSR_PR) |
3461                    (1ull << MSR_ME) |
3462                    (1ull << MSR_DE) |
3463                    (1ull << MSR_LE);
3464    pcc->mmu_model = POWERPC_MMU_REAL;
3465    pcc->excp_model = POWERPC_EXCP_40x;
3466    pcc->bus_model = PPC_FLAGS_INPUT_401;
3467    pcc->bfd_mach = bfd_mach_ppc_403;
3468    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3469                 POWERPC_FLAG_BUS_CLK;
3470}
3471
3472static void init_proc_401x2(CPUPPCState *env)
3473{
3474    gen_spr_40x(env);
3475    gen_spr_401_403(env);
3476    gen_spr_401x2(env);
3477    gen_spr_compress(env);
3478    /* Memory management */
3479#if !defined(CONFIG_USER_ONLY)
3480    env->nb_tlb = 64;
3481    env->nb_ways = 1;
3482    env->id_tlbs = 0;
3483    env->tlb_type = TLB_EMB;
3484#endif
3485    init_excp_4xx_softmmu(env);
3486    env->dcache_line_size = 32;
3487    env->icache_line_size = 32;
3488    /* Allocate hardware IRQ controller */
3489    ppc40x_irq_init(env_archcpu(env));
3490
3491    SET_FIT_PERIOD(12, 16, 20, 24);
3492    SET_WDT_PERIOD(16, 20, 24, 28);
3493}
3494
3495POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3496{
3497    DeviceClass *dc = DEVICE_CLASS(oc);
3498    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3499
3500    dc->desc = "PowerPC 401x2";
3501    pcc->init_proc = init_proc_401x2;
3502    pcc->check_pow = check_pow_nocheck;
3503    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3504                       PPC_DCR | PPC_WRTEE |
3505                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3506                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3507                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3508                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3509                       PPC_4xx_COMMON | PPC_40x_EXCP;
3510    pcc->msr_mask = (1ull << 20) |
3511                    (1ull << MSR_KEY) |
3512                    (1ull << MSR_POW) |
3513                    (1ull << MSR_CE) |
3514                    (1ull << MSR_ILE) |
3515                    (1ull << MSR_EE) |
3516                    (1ull << MSR_PR) |
3517                    (1ull << MSR_ME) |
3518                    (1ull << MSR_DE) |
3519                    (1ull << MSR_IR) |
3520                    (1ull << MSR_DR) |
3521                    (1ull << MSR_LE);
3522    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3523    pcc->excp_model = POWERPC_EXCP_40x;
3524    pcc->bus_model = PPC_FLAGS_INPUT_401;
3525    pcc->bfd_mach = bfd_mach_ppc_403;
3526    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3527                 POWERPC_FLAG_BUS_CLK;
3528}
3529
3530static void init_proc_401x3(CPUPPCState *env)
3531{
3532    gen_spr_40x(env);
3533    gen_spr_401_403(env);
3534    gen_spr_401(env);
3535    gen_spr_401x2(env);
3536    gen_spr_compress(env);
3537    init_excp_4xx_softmmu(env);
3538    env->dcache_line_size = 32;
3539    env->icache_line_size = 32;
3540    /* Allocate hardware IRQ controller */
3541    ppc40x_irq_init(env_archcpu(env));
3542
3543    SET_FIT_PERIOD(12, 16, 20, 24);
3544    SET_WDT_PERIOD(16, 20, 24, 28);
3545}
3546
3547POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3548{
3549    DeviceClass *dc = DEVICE_CLASS(oc);
3550    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3551
3552    dc->desc = "PowerPC 401x3";
3553    pcc->init_proc = init_proc_401x3;
3554    pcc->check_pow = check_pow_nocheck;
3555    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3556                       PPC_DCR | PPC_WRTEE |
3557                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3558                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3559                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3560                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3561                       PPC_4xx_COMMON | PPC_40x_EXCP;
3562    pcc->msr_mask = (1ull << 20) |
3563                    (1ull << MSR_KEY) |
3564                    (1ull << MSR_POW) |
3565                    (1ull << MSR_CE) |
3566                    (1ull << MSR_ILE) |
3567                    (1ull << MSR_EE) |
3568                    (1ull << MSR_PR) |
3569                    (1ull << MSR_ME) |
3570                    (1ull << MSR_DWE) |
3571                    (1ull << MSR_DE) |
3572                    (1ull << MSR_IR) |
3573                    (1ull << MSR_DR) |
3574                    (1ull << MSR_LE);
3575    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3576    pcc->excp_model = POWERPC_EXCP_40x;
3577    pcc->bus_model = PPC_FLAGS_INPUT_401;
3578    pcc->bfd_mach = bfd_mach_ppc_403;
3579    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3580                 POWERPC_FLAG_BUS_CLK;
3581}
3582
3583static void init_proc_IOP480(CPUPPCState *env)
3584{
3585    gen_spr_40x(env);
3586    gen_spr_401_403(env);
3587    gen_spr_401x2(env);
3588    gen_spr_compress(env);
3589    /* Memory management */
3590#if !defined(CONFIG_USER_ONLY)
3591    env->nb_tlb = 64;
3592    env->nb_ways = 1;
3593    env->id_tlbs = 0;
3594    env->tlb_type = TLB_EMB;
3595#endif
3596    init_excp_4xx_softmmu(env);
3597    env->dcache_line_size = 32;
3598    env->icache_line_size = 32;
3599    /* Allocate hardware IRQ controller */
3600    ppc40x_irq_init(env_archcpu(env));
3601
3602    SET_FIT_PERIOD(8, 12, 16, 20);
3603    SET_WDT_PERIOD(16, 20, 24, 28);
3604}
3605
3606POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3607{
3608    DeviceClass *dc = DEVICE_CLASS(oc);
3609    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3610
3611    dc->desc = "IOP480";
3612    pcc->init_proc = init_proc_IOP480;
3613    pcc->check_pow = check_pow_nocheck;
3614    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3615                       PPC_DCR | PPC_WRTEE |
3616                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3617                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3618                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3619                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3620                       PPC_4xx_COMMON | PPC_40x_EXCP;
3621    pcc->msr_mask = (1ull << 20) |
3622                    (1ull << MSR_KEY) |
3623                    (1ull << MSR_POW) |
3624                    (1ull << MSR_CE) |
3625                    (1ull << MSR_ILE) |
3626                    (1ull << MSR_EE) |
3627                    (1ull << MSR_PR) |
3628                    (1ull << MSR_ME) |
3629                    (1ull << MSR_DE) |
3630                    (1ull << MSR_IR) |
3631                    (1ull << MSR_DR) |
3632                    (1ull << MSR_LE);
3633    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3634    pcc->excp_model = POWERPC_EXCP_40x;
3635    pcc->bus_model = PPC_FLAGS_INPUT_401;
3636    pcc->bfd_mach = bfd_mach_ppc_403;
3637    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3638                 POWERPC_FLAG_BUS_CLK;
3639}
3640
3641static void init_proc_403(CPUPPCState *env)
3642{
3643    gen_spr_40x(env);
3644    gen_spr_401_403(env);
3645    gen_spr_403(env);
3646    gen_spr_403_real(env);
3647    init_excp_4xx_real(env);
3648    env->dcache_line_size = 32;
3649    env->icache_line_size = 32;
3650    /* Allocate hardware IRQ controller */
3651    ppc40x_irq_init(env_archcpu(env));
3652
3653    SET_FIT_PERIOD(8, 12, 16, 20);
3654    SET_WDT_PERIOD(16, 20, 24, 28);
3655}
3656
3657POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3658{
3659    DeviceClass *dc = DEVICE_CLASS(oc);
3660    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3661
3662    dc->desc = "PowerPC 403";
3663    pcc->init_proc = init_proc_403;
3664    pcc->check_pow = check_pow_nocheck;
3665    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3666                       PPC_DCR | PPC_WRTEE |
3667                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3668                       PPC_CACHE_DCBZ |
3669                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3670                       PPC_4xx_COMMON | PPC_40x_EXCP;
3671    pcc->msr_mask = (1ull << MSR_POW) |
3672                    (1ull << MSR_CE) |
3673                    (1ull << MSR_ILE) |
3674                    (1ull << MSR_EE) |
3675                    (1ull << MSR_PR) |
3676                    (1ull << MSR_ME) |
3677                    (1ull << MSR_PE) |
3678                    (1ull << MSR_PX) |
3679                    (1ull << MSR_LE);
3680    pcc->mmu_model = POWERPC_MMU_REAL;
3681    pcc->excp_model = POWERPC_EXCP_40x;
3682    pcc->bus_model = PPC_FLAGS_INPUT_401;
3683    pcc->bfd_mach = bfd_mach_ppc_403;
3684    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3685                 POWERPC_FLAG_BUS_CLK;
3686}
3687
3688static void init_proc_403GCX(CPUPPCState *env)
3689{
3690    gen_spr_40x(env);
3691    gen_spr_401_403(env);
3692    gen_spr_403(env);
3693    gen_spr_403_real(env);
3694    gen_spr_403_mmu(env);
3695    /* Bus access control */
3696    /* not emulated, as QEMU never does speculative access */
3697    spr_register(env, SPR_40x_SGR, "SGR",
3698                 SPR_NOACCESS, SPR_NOACCESS,
3699                 &spr_read_generic, &spr_write_generic,
3700                 0xFFFFFFFF);
3701    /* not emulated, as QEMU do not emulate caches */
3702    spr_register(env, SPR_40x_DCWR, "DCWR",
3703                 SPR_NOACCESS, SPR_NOACCESS,
3704                 &spr_read_generic, &spr_write_generic,
3705                 0x00000000);
3706    /* Memory management */
3707#if !defined(CONFIG_USER_ONLY)
3708    env->nb_tlb = 64;
3709    env->nb_ways = 1;
3710    env->id_tlbs = 0;
3711    env->tlb_type = TLB_EMB;
3712#endif
3713    init_excp_4xx_softmmu(env);
3714    env->dcache_line_size = 32;
3715    env->icache_line_size = 32;
3716    /* Allocate hardware IRQ controller */
3717    ppc40x_irq_init(env_archcpu(env));
3718
3719    SET_FIT_PERIOD(8, 12, 16, 20);
3720    SET_WDT_PERIOD(16, 20, 24, 28);
3721}
3722
3723POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3724{
3725    DeviceClass *dc = DEVICE_CLASS(oc);
3726    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3727
3728    dc->desc = "PowerPC 403 GCX";
3729    pcc->init_proc = init_proc_403GCX;
3730    pcc->check_pow = check_pow_nocheck;
3731    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3732                       PPC_DCR | PPC_WRTEE |
3733                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3734                       PPC_CACHE_DCBZ |
3735                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3736                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3737                       PPC_4xx_COMMON | PPC_40x_EXCP;
3738    pcc->msr_mask = (1ull << MSR_POW) |
3739                    (1ull << MSR_CE) |
3740                    (1ull << MSR_ILE) |
3741                    (1ull << MSR_EE) |
3742                    (1ull << MSR_PR) |
3743                    (1ull << MSR_ME) |
3744                    (1ull << MSR_PE) |
3745                    (1ull << MSR_PX) |
3746                    (1ull << MSR_LE);
3747    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3748    pcc->excp_model = POWERPC_EXCP_40x;
3749    pcc->bus_model = PPC_FLAGS_INPUT_401;
3750    pcc->bfd_mach = bfd_mach_ppc_403;
3751    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3752                 POWERPC_FLAG_BUS_CLK;
3753}
3754
3755static void init_proc_405(CPUPPCState *env)
3756{
3757    /* Time base */
3758    gen_tbl(env);
3759    gen_spr_40x(env);
3760    gen_spr_405(env);
3761    /* Bus access control */
3762    /* not emulated, as QEMU never does speculative access */
3763    spr_register(env, SPR_40x_SGR, "SGR",
3764                 SPR_NOACCESS, SPR_NOACCESS,
3765                 &spr_read_generic, &spr_write_generic,
3766                 0xFFFFFFFF);
3767    /* not emulated, as QEMU do not emulate caches */
3768    spr_register(env, SPR_40x_DCWR, "DCWR",
3769                 SPR_NOACCESS, SPR_NOACCESS,
3770                 &spr_read_generic, &spr_write_generic,
3771                 0x00000000);
3772    /* Memory management */
3773#if !defined(CONFIG_USER_ONLY)
3774    env->nb_tlb = 64;
3775    env->nb_ways = 1;
3776    env->id_tlbs = 0;
3777    env->tlb_type = TLB_EMB;
3778#endif
3779    init_excp_4xx_softmmu(env);
3780    env->dcache_line_size = 32;
3781    env->icache_line_size = 32;
3782    /* Allocate hardware IRQ controller */
3783    ppc40x_irq_init(env_archcpu(env));
3784
3785    SET_FIT_PERIOD(8, 12, 16, 20);
3786    SET_WDT_PERIOD(16, 20, 24, 28);
3787}
3788
3789POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3790{
3791    DeviceClass *dc = DEVICE_CLASS(oc);
3792    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3793
3794    dc->desc = "PowerPC 405";
3795    pcc->init_proc = init_proc_405;
3796    pcc->check_pow = check_pow_nocheck;
3797    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3798                       PPC_DCR | PPC_WRTEE |
3799                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3800                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3801                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3802                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3803                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3804    pcc->msr_mask = (1ull << MSR_POW) |
3805                    (1ull << MSR_CE) |
3806                    (1ull << MSR_EE) |
3807                    (1ull << MSR_PR) |
3808                    (1ull << MSR_FP) |
3809                    (1ull << MSR_DWE) |
3810                    (1ull << MSR_DE) |
3811                    (1ull << MSR_IR) |
3812                    (1ull << MSR_DR);
3813    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3814    pcc->excp_model = POWERPC_EXCP_40x;
3815    pcc->bus_model = PPC_FLAGS_INPUT_405;
3816    pcc->bfd_mach = bfd_mach_ppc_403;
3817    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3818                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3819}
3820
3821static void init_proc_440EP(CPUPPCState *env)
3822{
3823    /* Time base */
3824    gen_tbl(env);
3825    gen_spr_BookE(env, 0x000000000000FFFFULL);
3826    gen_spr_440(env);
3827    gen_spr_usprgh(env);
3828    /* Processor identification */
3829    spr_register(env, SPR_BOOKE_PIR, "PIR",
3830                 SPR_NOACCESS, SPR_NOACCESS,
3831                 &spr_read_generic, &spr_write_pir,
3832                 0x00000000);
3833    /* XXX : not implemented */
3834    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3835                 SPR_NOACCESS, SPR_NOACCESS,
3836                 &spr_read_generic, &spr_write_generic,
3837                 0x00000000);
3838    /* XXX : not implemented */
3839    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3840                 SPR_NOACCESS, SPR_NOACCESS,
3841                 &spr_read_generic, &spr_write_generic,
3842                 0x00000000);
3843    /* XXX : not implemented */
3844    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3845                 SPR_NOACCESS, SPR_NOACCESS,
3846                 &spr_read_generic, &spr_write_generic,
3847                 0x00000000);
3848    /* XXX : not implemented */
3849    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3850                 SPR_NOACCESS, SPR_NOACCESS,
3851                 &spr_read_generic, &spr_write_generic,
3852                 0x00000000);
3853    /* XXX : not implemented */
3854    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3855                 SPR_NOACCESS, SPR_NOACCESS,
3856                 &spr_read_generic, &spr_write_generic,
3857                 0x00000000);
3858    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3859                 SPR_NOACCESS, SPR_NOACCESS,
3860                 &spr_read_generic, &spr_write_generic,
3861                 0x00000000);
3862    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3863                 SPR_NOACCESS, SPR_NOACCESS,
3864                 &spr_read_generic, &spr_write_generic,
3865                 0x00000000);
3866    /* XXX : not implemented */
3867    spr_register(env, SPR_440_CCR1, "CCR1",
3868                 SPR_NOACCESS, SPR_NOACCESS,
3869                 &spr_read_generic, &spr_write_generic,
3870                 0x00000000);
3871    /* Memory management */
3872#if !defined(CONFIG_USER_ONLY)
3873    env->nb_tlb = 64;
3874    env->nb_ways = 1;
3875    env->id_tlbs = 0;
3876    env->tlb_type = TLB_EMB;
3877#endif
3878    init_excp_BookE(env);
3879    env->dcache_line_size = 32;
3880    env->icache_line_size = 32;
3881    ppc40x_irq_init(env_archcpu(env));
3882
3883    SET_FIT_PERIOD(12, 16, 20, 24);
3884    SET_WDT_PERIOD(20, 24, 28, 32);
3885}
3886
3887POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3888{
3889    DeviceClass *dc = DEVICE_CLASS(oc);
3890    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3891
3892    dc->desc = "PowerPC 440 EP";
3893    pcc->init_proc = init_proc_440EP;
3894    pcc->check_pow = check_pow_nocheck;
3895    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3896                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3897                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3898                       PPC_FLOAT_STFIWX |
3899                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3900                       PPC_CACHE | PPC_CACHE_ICBI |
3901                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3902                       PPC_MEM_TLBSYNC | PPC_MFTB |
3903                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3904                       PPC_440_SPEC;
3905    pcc->msr_mask = (1ull << MSR_POW) |
3906                    (1ull << MSR_CE) |
3907                    (1ull << MSR_EE) |
3908                    (1ull << MSR_PR) |
3909                    (1ull << MSR_FP) |
3910                    (1ull << MSR_ME) |
3911                    (1ull << MSR_FE0) |
3912                    (1ull << MSR_DWE) |
3913                    (1ull << MSR_DE) |
3914                    (1ull << MSR_FE1) |
3915                    (1ull << MSR_IR) |
3916                    (1ull << MSR_DR);
3917    pcc->mmu_model = POWERPC_MMU_BOOKE;
3918    pcc->excp_model = POWERPC_EXCP_BOOKE;
3919    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3920    pcc->bfd_mach = bfd_mach_ppc_403;
3921    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3922                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3923}
3924
3925POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3926{
3927    DeviceClass *dc = DEVICE_CLASS(oc);
3928    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3929
3930    dc->desc = "PowerPC 460 EX";
3931    pcc->init_proc = init_proc_440EP;
3932    pcc->check_pow = check_pow_nocheck;
3933    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3934                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3935                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3936                       PPC_FLOAT_STFIWX |
3937                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3938                       PPC_CACHE | PPC_CACHE_ICBI |
3939                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3940                       PPC_MEM_TLBSYNC | PPC_MFTB |
3941                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3942                       PPC_440_SPEC;
3943    pcc->msr_mask = (1ull << MSR_POW) |
3944                    (1ull << MSR_CE) |
3945                    (1ull << MSR_EE) |
3946                    (1ull << MSR_PR) |
3947                    (1ull << MSR_FP) |
3948                    (1ull << MSR_ME) |
3949                    (1ull << MSR_FE0) |
3950                    (1ull << MSR_DWE) |
3951                    (1ull << MSR_DE) |
3952                    (1ull << MSR_FE1) |
3953                    (1ull << MSR_IR) |
3954                    (1ull << MSR_DR);
3955    pcc->mmu_model = POWERPC_MMU_BOOKE;
3956    pcc->excp_model = POWERPC_EXCP_BOOKE;
3957    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3958    pcc->bfd_mach = bfd_mach_ppc_403;
3959    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3960                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3961}
3962
3963static void init_proc_440GP(CPUPPCState *env)
3964{
3965    /* Time base */
3966    gen_tbl(env);
3967    gen_spr_BookE(env, 0x000000000000FFFFULL);
3968    gen_spr_440(env);
3969    gen_spr_usprgh(env);
3970    /* Processor identification */
3971    spr_register(env, SPR_BOOKE_PIR, "PIR",
3972                 SPR_NOACCESS, SPR_NOACCESS,
3973                 &spr_read_generic, &spr_write_pir,
3974                 0x00000000);
3975    /* XXX : not implemented */
3976    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3977                 SPR_NOACCESS, SPR_NOACCESS,
3978                 &spr_read_generic, &spr_write_generic,
3979                 0x00000000);
3980    /* XXX : not implemented */
3981    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3982                 SPR_NOACCESS, SPR_NOACCESS,
3983                 &spr_read_generic, &spr_write_generic,
3984                 0x00000000);
3985    /* XXX : not implemented */
3986    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3987                 SPR_NOACCESS, SPR_NOACCESS,
3988                 &spr_read_generic, &spr_write_generic,
3989                 0x00000000);
3990    /* XXX : not implemented */
3991    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3992                 SPR_NOACCESS, SPR_NOACCESS,
3993                 &spr_read_generic, &spr_write_generic,
3994                 0x00000000);
3995    /* Memory management */
3996#if !defined(CONFIG_USER_ONLY)
3997    env->nb_tlb = 64;
3998    env->nb_ways = 1;
3999    env->id_tlbs = 0;
4000    env->tlb_type = TLB_EMB;
4001#endif
4002    init_excp_BookE(env);
4003    env->dcache_line_size = 32;
4004    env->icache_line_size = 32;
4005    /* XXX: TODO: allocate internal IRQ controller */
4006
4007    SET_FIT_PERIOD(12, 16, 20, 24);
4008    SET_WDT_PERIOD(20, 24, 28, 32);
4009}
4010
4011POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
4012{
4013    DeviceClass *dc = DEVICE_CLASS(oc);
4014    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4015
4016    dc->desc = "PowerPC 440 GP";
4017    pcc->init_proc = init_proc_440GP;
4018    pcc->check_pow = check_pow_nocheck;
4019    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4020                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
4021                       PPC_CACHE | PPC_CACHE_ICBI |
4022                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4023                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
4024                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4025                       PPC_440_SPEC;
4026    pcc->msr_mask = (1ull << MSR_POW) |
4027                    (1ull << MSR_CE) |
4028                    (1ull << MSR_EE) |
4029                    (1ull << MSR_PR) |
4030                    (1ull << MSR_FP) |
4031                    (1ull << MSR_ME) |
4032                    (1ull << MSR_FE0) |
4033                    (1ull << MSR_DWE) |
4034                    (1ull << MSR_DE) |
4035                    (1ull << MSR_FE1) |
4036                    (1ull << MSR_IR) |
4037                    (1ull << MSR_DR);
4038    pcc->mmu_model = POWERPC_MMU_BOOKE;
4039    pcc->excp_model = POWERPC_EXCP_BOOKE;
4040    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4041    pcc->bfd_mach = bfd_mach_ppc_403;
4042    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4043                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4044}
4045
4046static void init_proc_440x4(CPUPPCState *env)
4047{
4048    /* Time base */
4049    gen_tbl(env);
4050    gen_spr_BookE(env, 0x000000000000FFFFULL);
4051    gen_spr_440(env);
4052    gen_spr_usprgh(env);
4053    /* Processor identification */
4054    spr_register(env, SPR_BOOKE_PIR, "PIR",
4055                 SPR_NOACCESS, SPR_NOACCESS,
4056                 &spr_read_generic, &spr_write_pir,
4057                 0x00000000);
4058    /* XXX : not implemented */
4059    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4060                 SPR_NOACCESS, SPR_NOACCESS,
4061                 &spr_read_generic, &spr_write_generic,
4062                 0x00000000);
4063    /* XXX : not implemented */
4064    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4065                 SPR_NOACCESS, SPR_NOACCESS,
4066                 &spr_read_generic, &spr_write_generic,
4067                 0x00000000);
4068    /* XXX : not implemented */
4069    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4070                 SPR_NOACCESS, SPR_NOACCESS,
4071                 &spr_read_generic, &spr_write_generic,
4072                 0x00000000);
4073    /* XXX : not implemented */
4074    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4075                 SPR_NOACCESS, SPR_NOACCESS,
4076                 &spr_read_generic, &spr_write_generic,
4077                 0x00000000);
4078    /* Memory management */
4079#if !defined(CONFIG_USER_ONLY)
4080    env->nb_tlb = 64;
4081    env->nb_ways = 1;
4082    env->id_tlbs = 0;
4083    env->tlb_type = TLB_EMB;
4084#endif
4085    init_excp_BookE(env);
4086    env->dcache_line_size = 32;
4087    env->icache_line_size = 32;
4088    /* XXX: TODO: allocate internal IRQ controller */
4089
4090    SET_FIT_PERIOD(12, 16, 20, 24);
4091    SET_WDT_PERIOD(20, 24, 28, 32);
4092}
4093
4094POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4095{
4096    DeviceClass *dc = DEVICE_CLASS(oc);
4097    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4098
4099    dc->desc = "PowerPC 440x4";
4100    pcc->init_proc = init_proc_440x4;
4101    pcc->check_pow = check_pow_nocheck;
4102    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4103                       PPC_DCR | PPC_WRTEE |
4104                       PPC_CACHE | PPC_CACHE_ICBI |
4105                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4106                       PPC_MEM_TLBSYNC | PPC_MFTB |
4107                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4108                       PPC_440_SPEC;
4109    pcc->msr_mask = (1ull << MSR_POW) |
4110                    (1ull << MSR_CE) |
4111                    (1ull << MSR_EE) |
4112                    (1ull << MSR_PR) |
4113                    (1ull << MSR_FP) |
4114                    (1ull << MSR_ME) |
4115                    (1ull << MSR_FE0) |
4116                    (1ull << MSR_DWE) |
4117                    (1ull << MSR_DE) |
4118                    (1ull << MSR_FE1) |
4119                    (1ull << MSR_IR) |
4120                    (1ull << MSR_DR);
4121    pcc->mmu_model = POWERPC_MMU_BOOKE;
4122    pcc->excp_model = POWERPC_EXCP_BOOKE;
4123    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4124    pcc->bfd_mach = bfd_mach_ppc_403;
4125    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4126                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4127}
4128
4129static void init_proc_440x5(CPUPPCState *env)
4130{
4131    /* Time base */
4132    gen_tbl(env);
4133    gen_spr_BookE(env, 0x000000000000FFFFULL);
4134    gen_spr_440(env);
4135    gen_spr_usprgh(env);
4136    /* Processor identification */
4137    spr_register(env, SPR_BOOKE_PIR, "PIR",
4138                 SPR_NOACCESS, SPR_NOACCESS,
4139                 &spr_read_generic, &spr_write_pir,
4140                 0x00000000);
4141    /* XXX : not implemented */
4142    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4143                 SPR_NOACCESS, SPR_NOACCESS,
4144                 &spr_read_generic, &spr_write_generic,
4145                 0x00000000);
4146    /* XXX : not implemented */
4147    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4148                 SPR_NOACCESS, SPR_NOACCESS,
4149                 &spr_read_generic, &spr_write_generic,
4150                 0x00000000);
4151    /* XXX : not implemented */
4152    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4153                 SPR_NOACCESS, SPR_NOACCESS,
4154                 &spr_read_generic, &spr_write_generic,
4155                 0x00000000);
4156    /* XXX : not implemented */
4157    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4158                 SPR_NOACCESS, SPR_NOACCESS,
4159                 &spr_read_generic, &spr_write_generic,
4160                 0x00000000);
4161    /* XXX : not implemented */
4162    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4163                 SPR_NOACCESS, SPR_NOACCESS,
4164                 &spr_read_generic, &spr_write_generic,
4165                 0x00000000);
4166    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4167                 SPR_NOACCESS, SPR_NOACCESS,
4168                 &spr_read_generic, &spr_write_generic,
4169                 0x00000000);
4170    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4171                 SPR_NOACCESS, SPR_NOACCESS,
4172                 &spr_read_generic, &spr_write_generic,
4173                 0x00000000);
4174    /* XXX : not implemented */
4175    spr_register(env, SPR_440_CCR1, "CCR1",
4176                 SPR_NOACCESS, SPR_NOACCESS,
4177                 &spr_read_generic, &spr_write_generic,
4178                 0x00000000);
4179    /* Memory management */
4180#if !defined(CONFIG_USER_ONLY)
4181    env->nb_tlb = 64;
4182    env->nb_ways = 1;
4183    env->id_tlbs = 0;
4184    env->tlb_type = TLB_EMB;
4185#endif
4186    init_excp_BookE(env);
4187    env->dcache_line_size = 32;
4188    env->icache_line_size = 32;
4189    ppc40x_irq_init(env_archcpu(env));
4190
4191    SET_FIT_PERIOD(12, 16, 20, 24);
4192    SET_WDT_PERIOD(20, 24, 28, 32);
4193}
4194
4195POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4196{
4197    DeviceClass *dc = DEVICE_CLASS(oc);
4198    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4199
4200    dc->desc = "PowerPC 440x5";
4201    pcc->init_proc = init_proc_440x5;
4202    pcc->check_pow = check_pow_nocheck;
4203    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4204                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4205                       PPC_CACHE | PPC_CACHE_ICBI |
4206                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4207                       PPC_MEM_TLBSYNC | PPC_MFTB |
4208                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4209                       PPC_440_SPEC;
4210    pcc->msr_mask = (1ull << MSR_POW) |
4211                    (1ull << MSR_CE) |
4212                    (1ull << MSR_EE) |
4213                    (1ull << MSR_PR) |
4214                    (1ull << MSR_FP) |
4215                    (1ull << MSR_ME) |
4216                    (1ull << MSR_FE0) |
4217                    (1ull << MSR_DWE) |
4218                    (1ull << MSR_DE) |
4219                    (1ull << MSR_FE1) |
4220                    (1ull << MSR_IR) |
4221                    (1ull << MSR_DR);
4222    pcc->mmu_model = POWERPC_MMU_BOOKE;
4223    pcc->excp_model = POWERPC_EXCP_BOOKE;
4224    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4225    pcc->bfd_mach = bfd_mach_ppc_403;
4226    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4227                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4228}
4229
4230POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4231{
4232    DeviceClass *dc = DEVICE_CLASS(oc);
4233    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4234
4235    dc->desc = "PowerPC 440x5 with double precision FPU";
4236    pcc->init_proc = init_proc_440x5;
4237    pcc->check_pow = check_pow_nocheck;
4238    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4239                       PPC_FLOAT | PPC_FLOAT_FSQRT |
4240                       PPC_FLOAT_STFIWX |
4241                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4242                       PPC_CACHE | PPC_CACHE_ICBI |
4243                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4244                       PPC_MEM_TLBSYNC | PPC_MFTB |
4245                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4246                       PPC_440_SPEC;
4247    pcc->insns_flags2 = PPC2_FP_CVT_S64;
4248    pcc->msr_mask = (1ull << MSR_POW) |
4249                    (1ull << MSR_CE) |
4250                    (1ull << MSR_EE) |
4251                    (1ull << MSR_PR) |
4252                    (1ull << MSR_FP) |
4253                    (1ull << MSR_ME) |
4254                    (1ull << MSR_FE0) |
4255                    (1ull << MSR_DWE) |
4256                    (1ull << MSR_DE) |
4257                    (1ull << MSR_FE1) |
4258                    (1ull << MSR_IR) |
4259                    (1ull << MSR_DR);
4260    pcc->mmu_model = POWERPC_MMU_BOOKE;
4261    pcc->excp_model = POWERPC_EXCP_BOOKE;
4262    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4263    pcc->bfd_mach = bfd_mach_ppc_403;
4264    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4265                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4266}
4267
4268static void init_proc_MPC5xx(CPUPPCState *env)
4269{
4270    /* Time base */
4271    gen_tbl(env);
4272    gen_spr_5xx_8xx(env);
4273    gen_spr_5xx(env);
4274    init_excp_MPC5xx(env);
4275    env->dcache_line_size = 32;
4276    env->icache_line_size = 32;
4277    /* XXX: TODO: allocate internal IRQ controller */
4278}
4279
4280POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4281{
4282    DeviceClass *dc = DEVICE_CLASS(oc);
4283    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4284
4285    dc->desc = "Freescale 5xx cores (aka RCPU)";
4286    pcc->init_proc = init_proc_MPC5xx;
4287    pcc->check_pow = check_pow_none;
4288    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4289                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4290                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4291                       PPC_MFTB;
4292    pcc->msr_mask = (1ull << MSR_ILE) |
4293                    (1ull << MSR_EE) |
4294                    (1ull << MSR_PR) |
4295                    (1ull << MSR_FP) |
4296                    (1ull << MSR_ME) |
4297                    (1ull << MSR_FE0) |
4298                    (1ull << MSR_SE) |
4299                    (1ull << MSR_DE) |
4300                    (1ull << MSR_FE1) |
4301                    (1ull << MSR_EP) |
4302                    (1ull << MSR_RI) |
4303                    (1ull << MSR_LE);
4304    pcc->mmu_model = POWERPC_MMU_REAL;
4305    pcc->excp_model = POWERPC_EXCP_603;
4306    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4307    pcc->bfd_mach = bfd_mach_ppc_505;
4308    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4309                 POWERPC_FLAG_BUS_CLK;
4310}
4311
4312static void init_proc_MPC8xx(CPUPPCState *env)
4313{
4314    /* Time base */
4315    gen_tbl(env);
4316    gen_spr_5xx_8xx(env);
4317    gen_spr_8xx(env);
4318    init_excp_MPC8xx(env);
4319    env->dcache_line_size = 32;
4320    env->icache_line_size = 32;
4321    /* XXX: TODO: allocate internal IRQ controller */
4322}
4323
4324POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4325{
4326    DeviceClass *dc = DEVICE_CLASS(oc);
4327    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4328
4329    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4330    pcc->init_proc = init_proc_MPC8xx;
4331    pcc->check_pow = check_pow_none;
4332    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4333                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4334                       PPC_CACHE_ICBI | PPC_MFTB;
4335    pcc->msr_mask = (1ull << MSR_ILE) |
4336                    (1ull << MSR_EE) |
4337                    (1ull << MSR_PR) |
4338                    (1ull << MSR_FP) |
4339                    (1ull << MSR_ME) |
4340                    (1ull << MSR_SE) |
4341                    (1ull << MSR_DE) |
4342                    (1ull << MSR_EP) |
4343                    (1ull << MSR_IR) |
4344                    (1ull << MSR_DR) |
4345                    (1ull << MSR_RI) |
4346                    (1ull << MSR_LE);
4347    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4348    pcc->excp_model = POWERPC_EXCP_603;
4349    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4350    pcc->bfd_mach = bfd_mach_ppc_860;
4351    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4352                 POWERPC_FLAG_BUS_CLK;
4353}
4354
4355/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4356
4357static void init_proc_G2(CPUPPCState *env)
4358{
4359    gen_spr_ne_601(env);
4360    gen_spr_sdr1(env);
4361    gen_spr_G2_755(env);
4362    gen_spr_G2(env);
4363    /* Time base */
4364    gen_tbl(env);
4365    /* External access control */
4366    /* XXX : not implemented */
4367    spr_register(env, SPR_EAR, "EAR",
4368                 SPR_NOACCESS, SPR_NOACCESS,
4369                 &spr_read_generic, &spr_write_generic,
4370                 0x00000000);
4371    /* Hardware implementation register */
4372    /* XXX : not implemented */
4373    spr_register(env, SPR_HID0, "HID0",
4374                 SPR_NOACCESS, SPR_NOACCESS,
4375                 &spr_read_generic, &spr_write_generic,
4376                 0x00000000);
4377    /* XXX : not implemented */
4378    spr_register(env, SPR_HID1, "HID1",
4379                 SPR_NOACCESS, SPR_NOACCESS,
4380                 &spr_read_generic, &spr_write_generic,
4381                 0x00000000);
4382    /* XXX : not implemented */
4383    spr_register(env, SPR_HID2, "HID2",
4384                 SPR_NOACCESS, SPR_NOACCESS,
4385                 &spr_read_generic, &spr_write_generic,
4386                 0x00000000);
4387    /* Memory management */
4388    gen_low_BATs(env);
4389    gen_high_BATs(env);
4390    gen_6xx_7xx_soft_tlb(env, 64, 2);
4391    init_excp_G2(env);
4392    env->dcache_line_size = 32;
4393    env->icache_line_size = 32;
4394    /* Allocate hardware IRQ controller */
4395    ppc6xx_irq_init(env_archcpu(env));
4396}
4397
4398POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4399{
4400    DeviceClass *dc = DEVICE_CLASS(oc);
4401    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4402
4403    dc->desc = "PowerPC G2";
4404    pcc->init_proc = init_proc_G2;
4405    pcc->check_pow = check_pow_hid0;
4406    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4407                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4408                       PPC_FLOAT_STFIWX |
4409                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4410                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4411                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4412                       PPC_SEGMENT | PPC_EXTERN;
4413    pcc->msr_mask = (1ull << MSR_POW) |
4414                    (1ull << MSR_TGPR) |
4415                    (1ull << MSR_EE) |
4416                    (1ull << MSR_PR) |
4417                    (1ull << MSR_FP) |
4418                    (1ull << MSR_ME) |
4419                    (1ull << MSR_FE0) |
4420                    (1ull << MSR_SE) |
4421                    (1ull << MSR_DE) |
4422                    (1ull << MSR_FE1) |
4423                    (1ull << MSR_AL) |
4424                    (1ull << MSR_EP) |
4425                    (1ull << MSR_IR) |
4426                    (1ull << MSR_DR) |
4427                    (1ull << MSR_RI);
4428    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4429    pcc->excp_model = POWERPC_EXCP_G2;
4430    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4431    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4432    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4433                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4434}
4435
4436static void init_proc_G2LE(CPUPPCState *env)
4437{
4438    gen_spr_ne_601(env);
4439    gen_spr_sdr1(env);
4440    gen_spr_G2_755(env);
4441    gen_spr_G2(env);
4442    /* Time base */
4443    gen_tbl(env);
4444    /* External access control */
4445    /* XXX : not implemented */
4446    spr_register(env, SPR_EAR, "EAR",
4447                 SPR_NOACCESS, SPR_NOACCESS,
4448                 &spr_read_generic, &spr_write_generic,
4449                 0x00000000);
4450    /* Hardware implementation register */
4451    /* XXX : not implemented */
4452    spr_register(env, SPR_HID0, "HID0",
4453                 SPR_NOACCESS, SPR_NOACCESS,
4454                 &spr_read_generic, &spr_write_generic,
4455                 0x00000000);
4456    /* XXX : not implemented */
4457    spr_register(env, SPR_HID1, "HID1",
4458                 SPR_NOACCESS, SPR_NOACCESS,
4459                 &spr_read_generic, &spr_write_generic,
4460                 0x00000000);
4461    /* XXX : not implemented */
4462    spr_register(env, SPR_HID2, "HID2",
4463                 SPR_NOACCESS, SPR_NOACCESS,
4464                 &spr_read_generic, &spr_write_generic,
4465                 0x00000000);
4466
4467    /* Memory management */
4468    gen_low_BATs(env);
4469    gen_high_BATs(env);
4470    gen_6xx_7xx_soft_tlb(env, 64, 2);
4471    init_excp_G2(env);
4472    env->dcache_line_size = 32;
4473    env->icache_line_size = 32;
4474    /* Allocate hardware IRQ controller */
4475    ppc6xx_irq_init(env_archcpu(env));
4476}
4477
4478POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4479{
4480    DeviceClass *dc = DEVICE_CLASS(oc);
4481    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4482
4483    dc->desc = "PowerPC G2LE";
4484    pcc->init_proc = init_proc_G2LE;
4485    pcc->check_pow = check_pow_hid0;
4486    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4487                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4488                       PPC_FLOAT_STFIWX |
4489                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4490                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4491                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4492                       PPC_SEGMENT | PPC_EXTERN;
4493    pcc->msr_mask = (1ull << MSR_POW) |
4494                    (1ull << MSR_TGPR) |
4495                    (1ull << MSR_ILE) |
4496                    (1ull << MSR_EE) |
4497                    (1ull << MSR_PR) |
4498                    (1ull << MSR_FP) |
4499                    (1ull << MSR_ME) |
4500                    (1ull << MSR_FE0) |
4501                    (1ull << MSR_SE) |
4502                    (1ull << MSR_DE) |
4503                    (1ull << MSR_FE1) |
4504                    (1ull << MSR_AL) |
4505                    (1ull << MSR_EP) |
4506                    (1ull << MSR_IR) |
4507                    (1ull << MSR_DR) |
4508                    (1ull << MSR_RI) |
4509                    (1ull << MSR_LE);
4510    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4511    pcc->excp_model = POWERPC_EXCP_G2;
4512    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4513    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4514    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4515                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4516}
4517
4518static void init_proc_e200(CPUPPCState *env)
4519{
4520    /* Time base */
4521    gen_tbl(env);
4522    gen_spr_BookE(env, 0x000000070000FFFFULL);
4523    /* XXX : not implemented */
4524    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4525                 &spr_read_spefscr, &spr_write_spefscr,
4526                 &spr_read_spefscr, &spr_write_spefscr,
4527                 0x00000000);
4528    /* Memory management */
4529    gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4530    /* XXX : not implemented */
4531    spr_register(env, SPR_HID0, "HID0",
4532                 SPR_NOACCESS, SPR_NOACCESS,
4533                 &spr_read_generic, &spr_write_generic,
4534                 0x00000000);
4535    /* XXX : not implemented */
4536    spr_register(env, SPR_HID1, "HID1",
4537                 SPR_NOACCESS, SPR_NOACCESS,
4538                 &spr_read_generic, &spr_write_generic,
4539                 0x00000000);
4540    /* XXX : not implemented */
4541    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4542                 SPR_NOACCESS, SPR_NOACCESS,
4543                 &spr_read_generic, &spr_write_generic,
4544                 0x00000000);
4545    /* XXX : not implemented */
4546    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4547                 SPR_NOACCESS, SPR_NOACCESS,
4548                 &spr_read_generic, &spr_write_generic,
4549                 0x00000000);
4550    /* XXX : not implemented */
4551    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4552                 SPR_NOACCESS, SPR_NOACCESS,
4553                 &spr_read_generic, &spr_write_generic,
4554                 0x00000000);
4555    /* XXX : not implemented */
4556    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4557                 SPR_NOACCESS, SPR_NOACCESS,
4558                 &spr_read_generic, &spr_write_generic,
4559                 0x00000000);
4560    /* XXX : not implemented */
4561    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4562                 SPR_NOACCESS, SPR_NOACCESS,
4563                 &spr_read_generic, &spr_write_generic,
4564                 0x00000000);
4565    /* XXX : not implemented */
4566    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4567                 &spr_read_generic, SPR_NOACCESS,
4568                 &spr_read_generic, SPR_NOACCESS,
4569                 0x00000000);
4570    /* XXX : not implemented */
4571    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4572                 SPR_NOACCESS, SPR_NOACCESS,
4573                 &spr_read_generic, &spr_write_generic,
4574                 0x00000000);
4575    /* XXX : not implemented */
4576    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4577                 SPR_NOACCESS, SPR_NOACCESS,
4578                 &spr_read_generic, &spr_write_generic,
4579                 0x00000000);
4580    /* XXX : not implemented */
4581    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4582                 SPR_NOACCESS, SPR_NOACCESS,
4583                 &spr_read_generic, &spr_write_generic,
4584                 0x00000000);
4585    /* XXX : not implemented */
4586    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4587                 SPR_NOACCESS, SPR_NOACCESS,
4588                 &spr_read_generic, &spr_write_generic,
4589                 0x00000000);
4590    /* XXX : not implemented */
4591    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4592                 SPR_NOACCESS, SPR_NOACCESS,
4593                 &spr_read_generic, &spr_write_generic,
4594                 0x00000000);
4595    /* XXX : not implemented */
4596    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4597                 SPR_NOACCESS, SPR_NOACCESS,
4598                 &spr_read_generic, &spr_write_generic,
4599                 0x00000000);
4600    /* XXX : not implemented */
4601    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4602                 SPR_NOACCESS, SPR_NOACCESS,
4603                 &spr_read_generic, &spr_write_generic,
4604                 0x00000000); /* TOFIX */
4605    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4606                 SPR_NOACCESS, SPR_NOACCESS,
4607                 &spr_read_generic, &spr_write_generic,
4608                 0x00000000);
4609    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4610                 SPR_NOACCESS, SPR_NOACCESS,
4611                 &spr_read_generic, &spr_write_generic,
4612                 0x00000000);
4613#if !defined(CONFIG_USER_ONLY)
4614    env->nb_tlb = 64;
4615    env->nb_ways = 1;
4616    env->id_tlbs = 0;
4617    env->tlb_type = TLB_EMB;
4618#endif
4619    init_excp_e200(env, 0xFFFF0000UL);
4620    env->dcache_line_size = 32;
4621    env->icache_line_size = 32;
4622    /* XXX: TODO: allocate internal IRQ controller */
4623}
4624
4625POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4626{
4627    DeviceClass *dc = DEVICE_CLASS(oc);
4628    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4629
4630    dc->desc = "e200 core";
4631    pcc->init_proc = init_proc_e200;
4632    pcc->check_pow = check_pow_hid0;
4633    /*
4634     * XXX: unimplemented instructions:
4635     * dcblc
4636     * dcbtlst
4637     * dcbtstls
4638     * icblc
4639     * icbtls
4640     * tlbivax
4641     * all SPE multiply-accumulate instructions
4642     */
4643    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4644                       PPC_SPE | PPC_SPE_SINGLE |
4645                       PPC_WRTEE | PPC_RFDI |
4646                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4647                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4648                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4649                       PPC_BOOKE;
4650    pcc->msr_mask = (1ull << MSR_UCLE) |
4651                    (1ull << MSR_SPE) |
4652                    (1ull << MSR_POW) |
4653                    (1ull << MSR_CE) |
4654                    (1ull << MSR_EE) |
4655                    (1ull << MSR_PR) |
4656                    (1ull << MSR_FP) |
4657                    (1ull << MSR_ME) |
4658                    (1ull << MSR_FE0) |
4659                    (1ull << MSR_DWE) |
4660                    (1ull << MSR_DE) |
4661                    (1ull << MSR_FE1) |
4662                    (1ull << MSR_IR) |
4663                    (1ull << MSR_DR);
4664    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4665    pcc->excp_model = POWERPC_EXCP_BOOKE;
4666    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4667    pcc->bfd_mach = bfd_mach_ppc_860;
4668    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4669                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4670                 POWERPC_FLAG_BUS_CLK;
4671}
4672
4673static void init_proc_e300(CPUPPCState *env)
4674{
4675    gen_spr_ne_601(env);
4676    gen_spr_sdr1(env);
4677    gen_spr_603(env);
4678    /* Time base */
4679    gen_tbl(env);
4680    /* hardware implementation registers */
4681    /* XXX : not implemented */
4682    spr_register(env, SPR_HID0, "HID0",
4683                 SPR_NOACCESS, SPR_NOACCESS,
4684                 &spr_read_generic, &spr_write_generic,
4685                 0x00000000);
4686    /* XXX : not implemented */
4687    spr_register(env, SPR_HID1, "HID1",
4688                 SPR_NOACCESS, SPR_NOACCESS,
4689                 &spr_read_generic, &spr_write_generic,
4690                 0x00000000);
4691    /* XXX : not implemented */
4692    spr_register(env, SPR_HID2, "HID2",
4693                 SPR_NOACCESS, SPR_NOACCESS,
4694                 &spr_read_generic, &spr_write_generic,
4695                 0x00000000);
4696    /* Breakpoints */
4697    /* XXX : not implemented */
4698    spr_register(env, SPR_DABR, "DABR",
4699                 SPR_NOACCESS, SPR_NOACCESS,
4700                 &spr_read_generic, &spr_write_generic,
4701                 0x00000000);
4702    /* XXX : not implemented */
4703    spr_register(env, SPR_DABR2, "DABR2",
4704                 SPR_NOACCESS, SPR_NOACCESS,
4705                 &spr_read_generic, &spr_write_generic,
4706                 0x00000000);
4707    /* XXX : not implemented */
4708    spr_register(env, SPR_IABR2, "IABR2",
4709                 SPR_NOACCESS, SPR_NOACCESS,
4710                 &spr_read_generic, &spr_write_generic,
4711                 0x00000000);
4712    /* XXX : not implemented */
4713    spr_register(env, SPR_IBCR, "IBCR",
4714                 SPR_NOACCESS, SPR_NOACCESS,
4715                 &spr_read_generic, &spr_write_generic,
4716                 0x00000000);
4717    /* XXX : not implemented */
4718    spr_register(env, SPR_DBCR, "DBCR",
4719                 SPR_NOACCESS, SPR_NOACCESS,
4720                 &spr_read_generic, &spr_write_generic,
4721                 0x00000000);
4722    /* Memory management */
4723    gen_low_BATs(env);
4724    gen_high_BATs(env);
4725    gen_6xx_7xx_soft_tlb(env, 64, 2);
4726    init_excp_603(env);
4727    env->dcache_line_size = 32;
4728    env->icache_line_size = 32;
4729    /* Allocate hardware IRQ controller */
4730    ppc6xx_irq_init(env_archcpu(env));
4731}
4732
4733POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4734{
4735    DeviceClass *dc = DEVICE_CLASS(oc);
4736    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4737
4738    dc->desc = "e300 core";
4739    pcc->init_proc = init_proc_e300;
4740    pcc->check_pow = check_pow_hid0;
4741    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4742                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4743                       PPC_FLOAT_STFIWX |
4744                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4745                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4746                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4747                       PPC_SEGMENT | PPC_EXTERN;
4748    pcc->msr_mask = (1ull << MSR_POW) |
4749                    (1ull << MSR_TGPR) |
4750                    (1ull << MSR_ILE) |
4751                    (1ull << MSR_EE) |
4752                    (1ull << MSR_PR) |
4753                    (1ull << MSR_FP) |
4754                    (1ull << MSR_ME) |
4755                    (1ull << MSR_FE0) |
4756                    (1ull << MSR_SE) |
4757                    (1ull << MSR_DE) |
4758                    (1ull << MSR_FE1) |
4759                    (1ull << MSR_AL) |
4760                    (1ull << MSR_EP) |
4761                    (1ull << MSR_IR) |
4762                    (1ull << MSR_DR) |
4763                    (1ull << MSR_RI) |
4764                    (1ull << MSR_LE);
4765    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4766    pcc->excp_model = POWERPC_EXCP_603;
4767    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4768    pcc->bfd_mach = bfd_mach_ppc_603;
4769    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4770                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4771}
4772
4773#if !defined(CONFIG_USER_ONLY)
4774static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4775{
4776    TCGv val = tcg_temp_new();
4777    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4778    gen_store_spr(SPR_BOOKE_MAS3, val);
4779    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4780    gen_store_spr(SPR_BOOKE_MAS7, val);
4781    tcg_temp_free(val);
4782}
4783
4784static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4785{
4786    TCGv mas7 = tcg_temp_new();
4787    TCGv mas3 = tcg_temp_new();
4788    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4789    tcg_gen_shli_tl(mas7, mas7, 32);
4790    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4791    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4792    tcg_temp_free(mas3);
4793    tcg_temp_free(mas7);
4794}
4795
4796#endif
4797
4798enum fsl_e500_version {
4799    fsl_e500v1,
4800    fsl_e500v2,
4801    fsl_e500mc,
4802    fsl_e5500,
4803    fsl_e6500,
4804};
4805
4806static void init_proc_e500(CPUPPCState *env, int version)
4807{
4808    uint32_t tlbncfg[2];
4809    uint64_t ivor_mask;
4810    uint64_t ivpr_mask = 0xFFFF0000ULL;
4811    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4812                    | 0x0020; /* 32 kb */
4813    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4814                    | 0x0020; /* 32 kb */
4815    uint32_t mmucfg = 0;
4816#if !defined(CONFIG_USER_ONLY)
4817    int i;
4818#endif
4819
4820    /* Time base */
4821    gen_tbl(env);
4822    /*
4823     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4824     *     complain when accessing them.
4825     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4826     */
4827    switch (version) {
4828    case fsl_e500v1:
4829    case fsl_e500v2:
4830    default:
4831        ivor_mask = 0x0000000F0000FFFFULL;
4832        break;
4833    case fsl_e500mc:
4834    case fsl_e5500:
4835        ivor_mask = 0x000003FE0000FFFFULL;
4836        break;
4837    case fsl_e6500:
4838        ivor_mask = 0x000003FF0000FFFFULL;
4839        break;
4840    }
4841    gen_spr_BookE(env, ivor_mask);
4842    gen_spr_usprg3(env);
4843    /* Processor identification */
4844    spr_register(env, SPR_BOOKE_PIR, "PIR",
4845                 SPR_NOACCESS, SPR_NOACCESS,
4846                 &spr_read_generic, &spr_write_pir,
4847                 0x00000000);
4848    /* XXX : not implemented */
4849    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4850                 &spr_read_spefscr, &spr_write_spefscr,
4851                 &spr_read_spefscr, &spr_write_spefscr,
4852                 0x00000000);
4853#if !defined(CONFIG_USER_ONLY)
4854    /* Memory management */
4855    env->nb_pids = 3;
4856    env->nb_ways = 2;
4857    env->id_tlbs = 0;
4858    switch (version) {
4859    case fsl_e500v1:
4860        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4861        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4862        break;
4863    case fsl_e500v2:
4864        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4865        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4866        break;
4867    case fsl_e500mc:
4868    case fsl_e5500:
4869        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4870        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4871        break;
4872    case fsl_e6500:
4873        mmucfg = 0x6510B45;
4874        env->nb_pids = 1;
4875        tlbncfg[0] = 0x08052400;
4876        tlbncfg[1] = 0x40028040;
4877        break;
4878    default:
4879        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4880                  env->spr[SPR_PVR]);
4881    }
4882#endif
4883    /* Cache sizes */
4884    switch (version) {
4885    case fsl_e500v1:
4886    case fsl_e500v2:
4887        env->dcache_line_size = 32;
4888        env->icache_line_size = 32;
4889        break;
4890    case fsl_e500mc:
4891    case fsl_e5500:
4892        env->dcache_line_size = 64;
4893        env->icache_line_size = 64;
4894        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4895        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4896        break;
4897    case fsl_e6500:
4898        env->dcache_line_size = 32;
4899        env->icache_line_size = 32;
4900        l1cfg0 |= 0x0F83820;
4901        l1cfg1 |= 0x0B83820;
4902        break;
4903    default:
4904        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4905                  env->spr[SPR_PVR]);
4906    }
4907    gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4908    /* XXX : not implemented */
4909    spr_register(env, SPR_HID0, "HID0",
4910                 SPR_NOACCESS, SPR_NOACCESS,
4911                 &spr_read_generic, &spr_write_generic,
4912                 0x00000000);
4913    /* XXX : not implemented */
4914    spr_register(env, SPR_HID1, "HID1",
4915                 SPR_NOACCESS, SPR_NOACCESS,
4916                 &spr_read_generic, &spr_write_generic,
4917                 0x00000000);
4918    /* XXX : not implemented */
4919    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4920                 SPR_NOACCESS, SPR_NOACCESS,
4921                 &spr_read_generic, &spr_write_generic,
4922                 0x00000000);
4923    /* XXX : not implemented */
4924    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4925                 SPR_NOACCESS, SPR_NOACCESS,
4926                 &spr_read_generic, &spr_write_generic,
4927                 0x00000000);