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20#include "qemu/osdep.h"
21#include "qemu/log.h"
22#include "cpu.h"
23#include "qemu/main-loop.h"
24#include "exec/exec-all.h"
25
26
27void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28{
29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30}
31
32void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33{
34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35}
36
37
38static RISCVException fs(CPURISCVState *env, int csrno)
39{
40#if !defined(CONFIG_USER_ONLY)
41
42 if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
43 return RISCV_EXCP_NONE;
44 }
45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
46 return RISCV_EXCP_ILLEGAL_INST;
47 }
48#endif
49 return RISCV_EXCP_NONE;
50}
51
52static RISCVException vs(CPURISCVState *env, int csrno)
53{
54 if (env->misa_ext & RVV) {
55 return RISCV_EXCP_NONE;
56 }
57 return RISCV_EXCP_ILLEGAL_INST;
58}
59
60static RISCVException ctr(CPURISCVState *env, int csrno)
61{
62#if !defined(CONFIG_USER_ONLY)
63 CPUState *cs = env_cpu(env);
64 RISCVCPU *cpu = RISCV_CPU(cs);
65
66 if (!cpu->cfg.ext_counters) {
67
68 return RISCV_EXCP_ILLEGAL_INST;
69 }
70
71 if (riscv_cpu_virt_enabled(env)) {
72 switch (csrno) {
73 case CSR_CYCLE:
74 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
75 get_field(env->mcounteren, COUNTEREN_CY)) {
76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
77 }
78 break;
79 case CSR_TIME:
80 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
81 get_field(env->mcounteren, COUNTEREN_TM)) {
82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
83 }
84 break;
85 case CSR_INSTRET:
86 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
87 get_field(env->mcounteren, COUNTEREN_IR)) {
88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
89 }
90 break;
91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
95 }
96 break;
97 }
98 if (riscv_cpu_mxl(env) == MXL_RV32) {
99 switch (csrno) {
100 case CSR_CYCLEH:
101 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
102 get_field(env->mcounteren, COUNTEREN_CY)) {
103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
104 }
105 break;
106 case CSR_TIMEH:
107 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
108 get_field(env->mcounteren, COUNTEREN_TM)) {
109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
110 }
111 break;
112 case CSR_INSTRETH:
113 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
114 get_field(env->mcounteren, COUNTEREN_IR)) {
115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
116 }
117 break;
118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
122 }
123 break;
124 }
125 }
126 }
127#endif
128 return RISCV_EXCP_NONE;
129}
130
131static RISCVException ctr32(CPURISCVState *env, int csrno)
132{
133 if (riscv_cpu_mxl(env) != MXL_RV32) {
134 return RISCV_EXCP_ILLEGAL_INST;
135 }
136
137 return ctr(env, csrno);
138}
139
140#if !defined(CONFIG_USER_ONLY)
141static RISCVException any(CPURISCVState *env, int csrno)
142{
143 return RISCV_EXCP_NONE;
144}
145
146static RISCVException any32(CPURISCVState *env, int csrno)
147{
148 if (riscv_cpu_mxl(env) != MXL_RV32) {
149 return RISCV_EXCP_ILLEGAL_INST;
150 }
151
152 return any(env, csrno);
153
154}
155
156static RISCVException smode(CPURISCVState *env, int csrno)
157{
158 if (riscv_has_ext(env, RVS)) {
159 return RISCV_EXCP_NONE;
160 }
161
162 return RISCV_EXCP_ILLEGAL_INST;
163}
164
165static RISCVException hmode(CPURISCVState *env, int csrno)
166{
167 if (riscv_has_ext(env, RVS) &&
168 riscv_has_ext(env, RVH)) {
169
170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
171 env->priv == PRV_M) {
172 return RISCV_EXCP_NONE;
173 } else {
174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
175 }
176 }
177
178 return RISCV_EXCP_ILLEGAL_INST;
179}
180
181static RISCVException hmode32(CPURISCVState *env, int csrno)
182{
183 if (riscv_cpu_mxl(env) != MXL_RV32) {
184 if (riscv_cpu_virt_enabled(env)) {
185 return RISCV_EXCP_ILLEGAL_INST;
186 } else {
187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
188 }
189 }
190
191 return hmode(env, csrno);
192
193}
194
195
196static RISCVException pointer_masking(CPURISCVState *env, int csrno)
197{
198
199 if (riscv_has_ext(env, RVJ)) {
200 return RISCV_EXCP_NONE;
201 }
202 return RISCV_EXCP_ILLEGAL_INST;
203}
204
205static RISCVException pmp(CPURISCVState *env, int csrno)
206{
207 if (riscv_feature(env, RISCV_FEATURE_PMP)) {
208 return RISCV_EXCP_NONE;
209 }
210
211 return RISCV_EXCP_ILLEGAL_INST;
212}
213
214static RISCVException epmp(CPURISCVState *env, int csrno)
215{
216 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
217 return RISCV_EXCP_NONE;
218 }
219
220 return RISCV_EXCP_ILLEGAL_INST;
221}
222#endif
223
224
225static RISCVException read_fflags(CPURISCVState *env, int csrno,
226 target_ulong *val)
227{
228 *val = riscv_cpu_get_fflags(env);
229 return RISCV_EXCP_NONE;
230}
231
232static RISCVException write_fflags(CPURISCVState *env, int csrno,
233 target_ulong val)
234{
235#if !defined(CONFIG_USER_ONLY)
236 env->mstatus |= MSTATUS_FS;
237#endif
238 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
239 return RISCV_EXCP_NONE;
240}
241
242static RISCVException read_frm(CPURISCVState *env, int csrno,
243 target_ulong *val)
244{
245 *val = env->frm;
246 return RISCV_EXCP_NONE;
247}
248
249static RISCVException write_frm(CPURISCVState *env, int csrno,
250 target_ulong val)
251{
252#if !defined(CONFIG_USER_ONLY)
253 env->mstatus |= MSTATUS_FS;
254#endif
255 env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
256 return RISCV_EXCP_NONE;
257}
258
259static RISCVException read_fcsr(CPURISCVState *env, int csrno,
260 target_ulong *val)
261{
262 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
263 | (env->frm << FSR_RD_SHIFT);
264 if (vs(env, csrno) >= 0) {
265 *val |= (env->vxrm << FSR_VXRM_SHIFT)
266 | (env->vxsat << FSR_VXSAT_SHIFT);
267 }
268 return RISCV_EXCP_NONE;
269}
270
271static RISCVException write_fcsr(CPURISCVState *env, int csrno,
272 target_ulong val)
273{
274#if !defined(CONFIG_USER_ONLY)
275 env->mstatus |= MSTATUS_FS;
276#endif
277 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
278 if (vs(env, csrno) >= 0) {
279 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
280 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
281 }
282 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
283 return RISCV_EXCP_NONE;
284}
285
286static RISCVException read_vtype(CPURISCVState *env, int csrno,
287 target_ulong *val)
288{
289 *val = env->vtype;
290 return RISCV_EXCP_NONE;
291}
292
293static RISCVException read_vl(CPURISCVState *env, int csrno,
294 target_ulong *val)
295{
296 *val = env->vl;
297 return RISCV_EXCP_NONE;
298}
299
300static RISCVException read_vxrm(CPURISCVState *env, int csrno,
301 target_ulong *val)
302{
303 *val = env->vxrm;
304 return RISCV_EXCP_NONE;
305}
306
307static RISCVException write_vxrm(CPURISCVState *env, int csrno,
308 target_ulong val)
309{
310 env->vxrm = val;
311 return RISCV_EXCP_NONE;
312}
313
314static RISCVException read_vxsat(CPURISCVState *env, int csrno,
315 target_ulong *val)
316{
317 *val = env->vxsat;
318 return RISCV_EXCP_NONE;
319}
320
321static RISCVException write_vxsat(CPURISCVState *env, int csrno,
322 target_ulong val)
323{
324 env->vxsat = val;
325 return RISCV_EXCP_NONE;
326}
327
328static RISCVException read_vstart(CPURISCVState *env, int csrno,
329 target_ulong *val)
330{
331 *val = env->vstart;
332 return RISCV_EXCP_NONE;
333}
334
335static RISCVException write_vstart(CPURISCVState *env, int csrno,
336 target_ulong val)
337{
338 env->vstart = val;
339 return RISCV_EXCP_NONE;
340}
341
342
343static RISCVException read_instret(CPURISCVState *env, int csrno,
344 target_ulong *val)
345{
346#if !defined(CONFIG_USER_ONLY)
347 if (icount_enabled()) {
348 *val = icount_get();
349 } else {
350 *val = cpu_get_host_ticks();
351 }
352#else
353 *val = cpu_get_host_ticks();
354#endif
355 return RISCV_EXCP_NONE;
356}
357
358static RISCVException read_instreth(CPURISCVState *env, int csrno,
359 target_ulong *val)
360{
361#if !defined(CONFIG_USER_ONLY)
362 if (icount_enabled()) {
363 *val = icount_get() >> 32;
364 } else {
365 *val = cpu_get_host_ticks() >> 32;
366 }
367#else
368 *val = cpu_get_host_ticks() >> 32;
369#endif
370 return RISCV_EXCP_NONE;
371}
372
373#if defined(CONFIG_USER_ONLY)
374static RISCVException read_time(CPURISCVState *env, int csrno,
375 target_ulong *val)
376{
377 *val = cpu_get_host_ticks();
378 return RISCV_EXCP_NONE;
379}
380
381static RISCVException read_timeh(CPURISCVState *env, int csrno,
382 target_ulong *val)
383{
384 *val = cpu_get_host_ticks() >> 32;
385 return RISCV_EXCP_NONE;
386}
387
388#else
389
390static RISCVException read_time(CPURISCVState *env, int csrno,
391 target_ulong *val)
392{
393 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
394
395 if (!env->rdtime_fn) {
396 return RISCV_EXCP_ILLEGAL_INST;
397 }
398
399 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
400 return RISCV_EXCP_NONE;
401}
402
403static RISCVException read_timeh(CPURISCVState *env, int csrno,
404 target_ulong *val)
405{
406 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
407
408 if (!env->rdtime_fn) {
409 return RISCV_EXCP_ILLEGAL_INST;
410 }
411
412 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
413 return RISCV_EXCP_NONE;
414}
415
416
417
418#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
419#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
420#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
421
422static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
423 VS_MODE_INTERRUPTS;
424static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
425static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
426 VS_MODE_INTERRUPTS;
427#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
428 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
429 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
430 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
431 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
432 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
433 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
434 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
435 (1ULL << (RISCV_EXCP_U_ECALL)) | \
436 (1ULL << (RISCV_EXCP_S_ECALL)) | \
437 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
438 (1ULL << (RISCV_EXCP_M_ECALL)) | \
439 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
440 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
441 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
442 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
443 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
444 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
445 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
446static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
447 ~((1ULL << (RISCV_EXCP_S_ECALL)) |
448 (1ULL << (RISCV_EXCP_VS_ECALL)) |
449 (1ULL << (RISCV_EXCP_M_ECALL)) |
450 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
451 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
452 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
453 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
454static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
455 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
456 SSTATUS_SUM | SSTATUS_MXR;
457static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
458static const target_ulong hip_writable_mask = MIP_VSSIP;
459static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
460static const target_ulong vsip_writable_mask = MIP_VSSIP;
461
462static const char valid_vm_1_10_32[16] = {
463 [VM_1_10_MBARE] = 1,
464 [VM_1_10_SV32] = 1
465};
466
467static const char valid_vm_1_10_64[16] = {
468 [VM_1_10_MBARE] = 1,
469 [VM_1_10_SV39] = 1,
470 [VM_1_10_SV48] = 1,
471 [VM_1_10_SV57] = 1
472};
473
474
475static RISCVException read_zero(CPURISCVState *env, int csrno,
476 target_ulong *val)
477{
478 *val = 0;
479 return RISCV_EXCP_NONE;
480}
481
482static RISCVException read_mhartid(CPURISCVState *env, int csrno,
483 target_ulong *val)
484{
485 *val = env->mhartid;
486 return RISCV_EXCP_NONE;
487}
488
489
490
491
492static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
493{
494 if ((status & MSTATUS_FS) == MSTATUS_FS ||
495 (status & MSTATUS_XS) == MSTATUS_XS) {
496 switch (xl) {
497 case MXL_RV32:
498 return status | MSTATUS32_SD;
499 case MXL_RV64:
500 return status | MSTATUS64_SD;
501 default:
502 g_assert_not_reached();
503 }
504 }
505 return status;
506}
507
508static RISCVException read_mstatus(CPURISCVState *env, int csrno,
509 target_ulong *val)
510{
511 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
512 return RISCV_EXCP_NONE;
513}
514
515static int validate_vm(CPURISCVState *env, target_ulong vm)
516{
517 if (riscv_cpu_mxl(env) == MXL_RV32) {
518 return valid_vm_1_10_32[vm & 0xf];
519 } else {
520 return valid_vm_1_10_64[vm & 0xf];
521 }
522}
523
524static RISCVException write_mstatus(CPURISCVState *env, int csrno,
525 target_ulong val)
526{
527 uint64_t mstatus = env->mstatus;
528 uint64_t mask = 0;
529
530
531 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
532 MSTATUS_MPRV | MSTATUS_SUM)) {
533 tlb_flush(env_cpu(env));
534 }
535 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
536 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
537 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
538 MSTATUS_TW;
539
540 if (riscv_cpu_mxl(env) != MXL_RV32) {
541
542
543
544
545 mask |= MSTATUS_MPV | MSTATUS_GVA;
546 }
547
548 mstatus = (mstatus & ~mask) | (val & mask);
549
550 if (riscv_cpu_mxl(env) == MXL_RV64) {
551
552 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
553 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
554 }
555 env->mstatus = mstatus;
556
557 return RISCV_EXCP_NONE;
558}
559
560static RISCVException read_mstatush(CPURISCVState *env, int csrno,
561 target_ulong *val)
562{
563 *val = env->mstatus >> 32;
564 return RISCV_EXCP_NONE;
565}
566
567static RISCVException write_mstatush(CPURISCVState *env, int csrno,
568 target_ulong val)
569{
570 uint64_t valh = (uint64_t)val << 32;
571 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
572
573 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
574 tlb_flush(env_cpu(env));
575 }
576
577 env->mstatus = (env->mstatus & ~mask) | (valh & mask);
578
579 return RISCV_EXCP_NONE;
580}
581
582static RISCVException read_misa(CPURISCVState *env, int csrno,
583 target_ulong *val)
584{
585 target_ulong misa;
586
587 switch (env->misa_mxl) {
588 case MXL_RV32:
589 misa = (target_ulong)MXL_RV32 << 30;
590 break;
591#ifdef TARGET_RISCV64
592 case MXL_RV64:
593 misa = (target_ulong)MXL_RV64 << 62;
594 break;
595#endif
596 default:
597 g_assert_not_reached();
598 }
599
600 *val = misa | env->misa_ext;
601 return RISCV_EXCP_NONE;
602}
603
604static RISCVException write_misa(CPURISCVState *env, int csrno,
605 target_ulong val)
606{
607 if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
608
609 return RISCV_EXCP_NONE;
610 }
611
612
613 if (!(val & (RVI | RVE))) {
614
615 return RISCV_EXCP_NONE;
616 }
617
618
619 if (val & RVE) {
620
621
622
623 return RISCV_EXCP_NONE;
624 }
625
626
627
628
629
630
631
632 val &= env->misa_ext_mask;
633
634
635 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
636
637
638 if ((val & RVD) && !(val & RVF)) {
639 val &= ~RVD;
640 }
641
642
643
644
645 if ((val & RVC) && (GETPC() & ~3) != 0) {
646 val &= ~RVC;
647 }
648
649
650 if (val == env->misa_ext) {
651 return RISCV_EXCP_NONE;
652 }
653
654
655 tb_flush(env_cpu(env));
656 env->misa_ext = val;
657 return RISCV_EXCP_NONE;
658}
659
660static RISCVException read_medeleg(CPURISCVState *env, int csrno,
661 target_ulong *val)
662{
663 *val = env->medeleg;
664 return RISCV_EXCP_NONE;
665}
666
667static RISCVException write_medeleg(CPURISCVState *env, int csrno,
668 target_ulong val)
669{
670 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
671 return RISCV_EXCP_NONE;
672}
673
674static RISCVException read_mideleg(CPURISCVState *env, int csrno,
675 target_ulong *val)
676{
677 *val = env->mideleg;
678 return RISCV_EXCP_NONE;
679}
680
681static RISCVException write_mideleg(CPURISCVState *env, int csrno,
682 target_ulong val)
683{
684 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
685 if (riscv_has_ext(env, RVH)) {
686 env->mideleg |= VS_MODE_INTERRUPTS;
687 }
688 return RISCV_EXCP_NONE;
689}
690
691static RISCVException read_mie(CPURISCVState *env, int csrno,
692 target_ulong *val)
693{
694 *val = env->mie;
695 return RISCV_EXCP_NONE;
696}
697
698static RISCVException write_mie(CPURISCVState *env, int csrno,
699 target_ulong val)
700{
701 env->mie = (env->mie & ~all_ints) | (val & all_ints);
702 return RISCV_EXCP_NONE;
703}
704
705static RISCVException read_mtvec(CPURISCVState *env, int csrno,
706 target_ulong *val)
707{
708 *val = env->mtvec;
709 return RISCV_EXCP_NONE;
710}
711
712static RISCVException write_mtvec(CPURISCVState *env, int csrno,
713 target_ulong val)
714{
715
716 if ((val & 3) < 2) {
717 env->mtvec = val;
718 } else {
719 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
720 }
721 return RISCV_EXCP_NONE;
722}
723
724static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
725 target_ulong *val)
726{
727 *val = env->mcounteren;
728 return RISCV_EXCP_NONE;
729}
730
731static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
732 target_ulong val)
733{
734 env->mcounteren = val;
735 return RISCV_EXCP_NONE;
736}
737
738
739static RISCVException read_mscratch(CPURISCVState *env, int csrno,
740 target_ulong *val)
741{
742 *val = env->mscratch;
743 return RISCV_EXCP_NONE;
744}
745
746static RISCVException write_mscratch(CPURISCVState *env, int csrno,
747 target_ulong val)
748{
749 env->mscratch = val;
750 return RISCV_EXCP_NONE;
751}
752
753static RISCVException read_mepc(CPURISCVState *env, int csrno,
754 target_ulong *val)
755{
756 *val = env->mepc;
757 return RISCV_EXCP_NONE;
758}
759
760static RISCVException write_mepc(CPURISCVState *env, int csrno,
761 target_ulong val)
762{
763 env->mepc = val;
764 return RISCV_EXCP_NONE;
765}
766
767static RISCVException read_mcause(CPURISCVState *env, int csrno,
768 target_ulong *val)
769{
770 *val = env->mcause;
771 return RISCV_EXCP_NONE;
772}
773
774static RISCVException write_mcause(CPURISCVState *env, int csrno,
775 target_ulong val)
776{
777 env->mcause = val;
778 return RISCV_EXCP_NONE;
779}
780
781static RISCVException read_mtval(CPURISCVState *env, int csrno,
782 target_ulong *val)
783{
784 *val = env->mtval;
785 return RISCV_EXCP_NONE;
786}
787
788static RISCVException write_mtval(CPURISCVState *env, int csrno,
789 target_ulong val)
790{
791 env->mtval = val;
792 return RISCV_EXCP_NONE;
793}
794
795static RISCVException rmw_mip(CPURISCVState *env, int csrno,
796 target_ulong *ret_value,
797 target_ulong new_value, target_ulong write_mask)
798{
799 RISCVCPU *cpu = env_archcpu(env);
800
801 target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
802 uint32_t old_mip;
803
804 if (mask) {
805 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
806 } else {
807 old_mip = env->mip;
808 }
809
810 if (ret_value) {
811 *ret_value = old_mip;
812 }
813
814 return RISCV_EXCP_NONE;
815}
816
817
818static RISCVException read_sstatus(CPURISCVState *env, int csrno,
819 target_ulong *val)
820{
821 target_ulong mask = (sstatus_v1_10_mask);
822
823
824 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
825 return RISCV_EXCP_NONE;
826}
827
828static RISCVException write_sstatus(CPURISCVState *env, int csrno,
829 target_ulong val)
830{
831 target_ulong mask = (sstatus_v1_10_mask);
832 target_ulong newval = (env->mstatus & ~mask) | (val & mask);
833 return write_mstatus(env, CSR_MSTATUS, newval);
834}
835
836static RISCVException read_vsie(CPURISCVState *env, int csrno,
837 target_ulong *val)
838{
839
840 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
841 return RISCV_EXCP_NONE;
842}
843
844static RISCVException read_sie(CPURISCVState *env, int csrno,
845 target_ulong *val)
846{
847 if (riscv_cpu_virt_enabled(env)) {
848 read_vsie(env, CSR_VSIE, val);
849 } else {
850 *val = env->mie & env->mideleg;
851 }
852 return RISCV_EXCP_NONE;
853}
854
855static RISCVException write_vsie(CPURISCVState *env, int csrno,
856 target_ulong val)
857{
858
859 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
860 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
861 return write_mie(env, CSR_MIE, newval);
862}
863
864static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
865{
866 if (riscv_cpu_virt_enabled(env)) {
867 write_vsie(env, CSR_VSIE, val);
868 } else {
869 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
870 (val & S_MODE_INTERRUPTS);
871 write_mie(env, CSR_MIE, newval);
872 }
873
874 return RISCV_EXCP_NONE;
875}
876
877static RISCVException read_stvec(CPURISCVState *env, int csrno,
878 target_ulong *val)
879{
880 *val = env->stvec;
881 return RISCV_EXCP_NONE;
882}
883
884static RISCVException write_stvec(CPURISCVState *env, int csrno,
885 target_ulong val)
886{
887
888 if ((val & 3) < 2) {
889 env->stvec = val;
890 } else {
891 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
892 }
893 return RISCV_EXCP_NONE;
894}
895
896static RISCVException read_scounteren(CPURISCVState *env, int csrno,
897 target_ulong *val)
898{
899 *val = env->scounteren;
900 return RISCV_EXCP_NONE;
901}
902
903static RISCVException write_scounteren(CPURISCVState *env, int csrno,
904 target_ulong val)
905{
906 env->scounteren = val;
907 return RISCV_EXCP_NONE;
908}
909
910
911static RISCVException read_sscratch(CPURISCVState *env, int csrno,
912 target_ulong *val)
913{
914 *val = env->sscratch;
915 return RISCV_EXCP_NONE;
916}
917
918static RISCVException write_sscratch(CPURISCVState *env, int csrno,
919 target_ulong val)
920{
921 env->sscratch = val;
922 return RISCV_EXCP_NONE;
923}
924
925static RISCVException read_sepc(CPURISCVState *env, int csrno,
926 target_ulong *val)
927{
928 *val = env->sepc;
929 return RISCV_EXCP_NONE;
930}
931
932static RISCVException write_sepc(CPURISCVState *env, int csrno,
933 target_ulong val)
934{
935 env->sepc = val;
936 return RISCV_EXCP_NONE;
937}
938
939static RISCVException read_scause(CPURISCVState *env, int csrno,
940 target_ulong *val)
941{
942 *val = env->scause;
943 return RISCV_EXCP_NONE;
944}
945
946static RISCVException write_scause(CPURISCVState *env, int csrno,
947 target_ulong val)
948{
949 env->scause = val;
950 return RISCV_EXCP_NONE;
951}
952
953static RISCVException read_stval(CPURISCVState *env, int csrno,
954 target_ulong *val)
955{
956 *val = env->stval;
957 return RISCV_EXCP_NONE;
958}
959
960static RISCVException write_stval(CPURISCVState *env, int csrno,
961 target_ulong val)
962{
963 env->stval = val;
964 return RISCV_EXCP_NONE;
965}
966
967static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
968 target_ulong *ret_value,
969 target_ulong new_value, target_ulong write_mask)
970{
971
972 int ret = rmw_mip(env, 0, ret_value, new_value << 1,
973 (write_mask << 1) & vsip_writable_mask & env->hideleg);
974
975 if (ret_value) {
976 *ret_value &= VS_MODE_INTERRUPTS;
977
978 *ret_value >>= 1;
979 }
980 return ret;
981}
982
983static RISCVException rmw_sip(CPURISCVState *env, int csrno,
984 target_ulong *ret_value,
985 target_ulong new_value, target_ulong write_mask)
986{
987 int ret;
988
989 if (riscv_cpu_virt_enabled(env)) {
990 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
991 } else {
992 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
993 write_mask & env->mideleg & sip_writable_mask);
994 }
995
996 if (ret_value) {
997 *ret_value &= env->mideleg;
998 }
999 return ret;
1000}
1001
1002
1003static RISCVException read_satp(CPURISCVState *env, int csrno,
1004 target_ulong *val)
1005{
1006 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1007 *val = 0;
1008 return RISCV_EXCP_NONE;
1009 }
1010
1011 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1012 return RISCV_EXCP_ILLEGAL_INST;
1013 } else {
1014 *val = env->satp;
1015 }
1016
1017 return RISCV_EXCP_NONE;
1018}
1019
1020static RISCVException write_satp(CPURISCVState *env, int csrno,
1021 target_ulong val)
1022{
1023 target_ulong vm, mask, asid;
1024
1025 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1026 return RISCV_EXCP_NONE;
1027 }
1028
1029 if (riscv_cpu_mxl(env) == MXL_RV32) {
1030 vm = validate_vm(env, get_field(val, SATP32_MODE));
1031 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1032 asid = (val ^ env->satp) & SATP32_ASID;
1033 } else {
1034 vm = validate_vm(env, get_field(val, SATP64_MODE));
1035 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1036 asid = (val ^ env->satp) & SATP64_ASID;
1037 }
1038
1039 if (vm && mask) {
1040 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1041 return RISCV_EXCP_ILLEGAL_INST;
1042 } else {
1043 if (asid) {
1044 tlb_flush(env_cpu(env));
1045 }
1046 env->satp = val;
1047 }
1048 }
1049 return RISCV_EXCP_NONE;
1050}
1051
1052
1053static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1054 target_ulong *val)
1055{
1056 *val = env->hstatus;
1057 if (riscv_cpu_mxl(env) != MXL_RV32) {
1058
1059 *val = set_field(*val, HSTATUS_VSXL, 2);
1060 }
1061
1062 *val = set_field(*val, HSTATUS_VSBE, 0);
1063 return RISCV_EXCP_NONE;
1064}
1065
1066static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1067 target_ulong val)
1068{
1069 env->hstatus = val;
1070 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1071 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1072 }
1073 if (get_field(val, HSTATUS_VSBE) != 0) {
1074 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1075 }
1076 return RISCV_EXCP_NONE;
1077}
1078
1079static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1080 target_ulong *val)
1081{
1082 *val = env->hedeleg;
1083 return RISCV_EXCP_NONE;
1084}
1085
1086static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1087 target_ulong val)
1088{
1089 env->hedeleg = val & vs_delegable_excps;
1090 return RISCV_EXCP_NONE;
1091}
1092
1093static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1094 target_ulong *val)
1095{
1096 *val = env->hideleg;
1097 return RISCV_EXCP_NONE;
1098}
1099
1100static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1101 target_ulong val)
1102{
1103 env->hideleg = val & vs_delegable_ints;
1104 return RISCV_EXCP_NONE;
1105}
1106
1107static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1108 target_ulong *ret_value,
1109 target_ulong new_value, target_ulong write_mask)
1110{
1111 int ret = rmw_mip(env, 0, ret_value, new_value,
1112 write_mask & hvip_writable_mask);
1113
1114 if (ret_value) {
1115 *ret_value &= hvip_writable_mask;
1116 }
1117 return ret;
1118}
1119
1120static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1121 target_ulong *ret_value,
1122 target_ulong new_value, target_ulong write_mask)
1123{
1124 int ret = rmw_mip(env, 0, ret_value, new_value,
1125 write_mask & hip_writable_mask);
1126
1127 if (ret_value) {
1128 *ret_value &= hip_writable_mask;
1129 }
1130 return ret;
1131}
1132
1133static RISCVException read_hie(CPURISCVState *env, int csrno,
1134 target_ulong *val)
1135{
1136 *val = env->mie & VS_MODE_INTERRUPTS;
1137 return RISCV_EXCP_NONE;
1138}
1139
1140static RISCVException write_hie(CPURISCVState *env, int csrno,
1141 target_ulong val)
1142{
1143 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1144 return write_mie(env, CSR_MIE, newval);
1145}
1146
1147static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1148 target_ulong *val)
1149{
1150 *val = env->hcounteren;
1151 return RISCV_EXCP_NONE;
1152}
1153
1154static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1155 target_ulong val)
1156{
1157 env->hcounteren = val;
1158 return RISCV_EXCP_NONE;
1159}
1160
1161static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1162 target_ulong val)
1163{
1164 if (val) {
1165 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1166 }
1167 return RISCV_EXCP_NONE;
1168}
1169
1170static RISCVException read_htval(CPURISCVState *env, int csrno,
1171 target_ulong *val)
1172{
1173 *val = env->htval;
1174 return RISCV_EXCP_NONE;
1175}
1176
1177static RISCVException write_htval(CPURISCVState *env, int csrno,
1178 target_ulong val)
1179{
1180 env->htval = val;
1181 return RISCV_EXCP_NONE;
1182}
1183
1184static RISCVException read_htinst(CPURISCVState *env, int csrno,
1185 target_ulong *val)
1186{
1187 *val = env->htinst;
1188 return RISCV_EXCP_NONE;
1189}
1190
1191static RISCVException write_htinst(CPURISCVState *env, int csrno,
1192 target_ulong val)
1193{
1194 return RISCV_EXCP_NONE;
1195}
1196
1197static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1198 target_ulong val)
1199{
1200 if (val) {
1201 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1202 }
1203 return RISCV_EXCP_NONE;
1204}
1205
1206static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1207 target_ulong *val)
1208{
1209 *val = env->hgatp;
1210 return RISCV_EXCP_NONE;
1211}
1212
1213static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1214 target_ulong val)
1215{
1216 env->hgatp = val;
1217 return RISCV_EXCP_NONE;
1218}
1219
1220static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1221 target_ulong *val)
1222{
1223 if (!env->rdtime_fn) {
1224 return RISCV_EXCP_ILLEGAL_INST;
1225 }
1226
1227 *val = env->htimedelta;
1228 return RISCV_EXCP_NONE;
1229}
1230
1231static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1232 target_ulong val)
1233{
1234 if (!env->rdtime_fn) {
1235 return RISCV_EXCP_ILLEGAL_INST;
1236 }
1237
1238 if (riscv_cpu_mxl(env) == MXL_RV32) {
1239 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1240 } else {
1241 env->htimedelta = val;
1242 }
1243 return RISCV_EXCP_NONE;
1244}
1245
1246static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1247 target_ulong *val)
1248{
1249 if (!env->rdtime_fn) {
1250 return RISCV_EXCP_ILLEGAL_INST;
1251 }
1252
1253 *val = env->htimedelta >> 32;
1254 return RISCV_EXCP_NONE;
1255}
1256
1257static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1258 target_ulong val)
1259{
1260 if (!env->rdtime_fn) {
1261 return RISCV_EXCP_ILLEGAL_INST;
1262 }
1263
1264 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1265 return RISCV_EXCP_NONE;
1266}
1267
1268
1269static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1270 target_ulong *val)
1271{
1272 *val = env->vsstatus;
1273 return RISCV_EXCP_NONE;
1274}
1275
1276static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1277 target_ulong val)
1278{
1279 uint64_t mask = (target_ulong)-1;
1280 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1281 return RISCV_EXCP_NONE;
1282}
1283
1284static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1285{
1286 *val = env->vstvec;
1287 return RISCV_EXCP_NONE;
1288}
1289
1290static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1291 target_ulong val)
1292{
1293 env->vstvec = val;
1294 return RISCV_EXCP_NONE;
1295}
1296
1297static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1298 target_ulong *val)
1299{
1300 *val = env->vsscratch;
1301 return RISCV_EXCP_NONE;
1302}
1303
1304static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1305 target_ulong val)
1306{
1307 env->vsscratch = val;
1308 return RISCV_EXCP_NONE;
1309}
1310
1311static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1312 target_ulong *val)
1313{
1314 *val = env->vsepc;
1315 return RISCV_EXCP_NONE;
1316}
1317
1318static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1319 target_ulong val)
1320{
1321 env->vsepc = val;
1322 return RISCV_EXCP_NONE;
1323}
1324
1325static RISCVException read_vscause(CPURISCVState *env, int csrno,
1326 target_ulong *val)
1327{
1328 *val = env->vscause;
1329 return RISCV_EXCP_NONE;
1330}
1331
1332static RISCVException write_vscause(CPURISCVState *env, int csrno,
1333 target_ulong val)
1334{
1335 env->vscause = val;
1336 return RISCV_EXCP_NONE;
1337}
1338
1339static RISCVException read_vstval(CPURISCVState *env, int csrno,
1340 target_ulong *val)
1341{
1342 *val = env->vstval;
1343 return RISCV_EXCP_NONE;
1344}
1345
1346static RISCVException write_vstval(CPURISCVState *env, int csrno,
1347 target_ulong val)
1348{
1349 env->vstval = val;
1350 return RISCV_EXCP_NONE;
1351}
1352
1353static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1354 target_ulong *val)
1355{
1356 *val = env->vsatp;
1357 return RISCV_EXCP_NONE;
1358}
1359
1360static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1361 target_ulong val)
1362{
1363 env->vsatp = val;
1364 return RISCV_EXCP_NONE;
1365}
1366
1367static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1368 target_ulong *val)
1369{
1370 *val = env->mtval2;
1371 return RISCV_EXCP_NONE;
1372}
1373
1374static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1375 target_ulong val)
1376{
1377 env->mtval2 = val;
1378 return RISCV_EXCP_NONE;
1379}
1380
1381static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1382 target_ulong *val)
1383{
1384 *val = env->mtinst;
1385 return RISCV_EXCP_NONE;
1386}
1387
1388static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1389 target_ulong val)
1390{
1391 env->mtinst = val;
1392 return RISCV_EXCP_NONE;
1393}
1394
1395
1396static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1397 target_ulong *val)
1398{
1399 *val = mseccfg_csr_read(env);
1400 return RISCV_EXCP_NONE;
1401}
1402
1403static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1404 target_ulong val)
1405{
1406 mseccfg_csr_write(env, val);
1407 return RISCV_EXCP_NONE;
1408}
1409
1410static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1411 target_ulong *val)
1412{
1413 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1414 return RISCV_EXCP_NONE;
1415}
1416
1417static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1418 target_ulong val)
1419{
1420 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1421 return RISCV_EXCP_NONE;
1422}
1423
1424static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1425 target_ulong *val)
1426{
1427 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1428 return RISCV_EXCP_NONE;
1429}
1430
1431static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1432 target_ulong val)
1433{
1434 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1435 return RISCV_EXCP_NONE;
1436}
1437
1438
1439
1440
1441
1442
1443static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1444{
1445 int csr_priv = get_field(csrno, 0x300);
1446 int pm_current;
1447
1448
1449
1450
1451
1452 if (env->priv != csr_priv) {
1453 return false;
1454 }
1455 switch (env->priv) {
1456 case PRV_M:
1457 pm_current = get_field(env->mmte, M_PM_CURRENT);
1458 break;
1459 case PRV_S:
1460 pm_current = get_field(env->mmte, S_PM_CURRENT);
1461 break;
1462 case PRV_U:
1463 pm_current = get_field(env->mmte, U_PM_CURRENT);
1464 break;
1465 default:
1466 g_assert_not_reached();
1467 }
1468
1469 return !pm_current;
1470}
1471
1472static RISCVException read_mmte(CPURISCVState *env, int csrno,
1473 target_ulong *val)
1474{
1475 *val = env->mmte & MMTE_MASK;
1476 return RISCV_EXCP_NONE;
1477}
1478
1479static RISCVException write_mmte(CPURISCVState *env, int csrno,
1480 target_ulong val)
1481{
1482 uint64_t mstatus;
1483 target_ulong wpri_val = val & MMTE_MASK;
1484
1485 if (val != wpri_val) {
1486 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1487 "MMTE: WPRI violation written 0x", val,
1488 "vs expected 0x", wpri_val);
1489 }
1490
1491 wpri_val |= MMTE_M_PM_CURRENT;
1492
1493
1494 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1495 env->mmte = wpri_val | PM_EXT_DIRTY;
1496
1497
1498 mstatus = env->mstatus | MSTATUS_XS;
1499 write_mstatus(env, csrno, mstatus);
1500 return RISCV_EXCP_NONE;
1501}
1502
1503static RISCVException read_smte(CPURISCVState *env, int csrno,
1504 target_ulong *val)
1505{
1506 *val = env->mmte & SMTE_MASK;
1507 return RISCV_EXCP_NONE;
1508}
1509
1510static RISCVException write_smte(CPURISCVState *env, int csrno,
1511 target_ulong val)
1512{
1513 target_ulong wpri_val = val & SMTE_MASK;
1514
1515 if (val != wpri_val) {
1516 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1517 "SMTE: WPRI violation written 0x", val,
1518 "vs expected 0x", wpri_val);
1519 }
1520
1521
1522 if (check_pm_current_disabled(env, csrno)) {
1523 return RISCV_EXCP_NONE;
1524 }
1525
1526 wpri_val |= (env->mmte & ~SMTE_MASK);
1527 write_mmte(env, csrno, wpri_val);
1528 return RISCV_EXCP_NONE;
1529}
1530
1531static RISCVException read_umte(CPURISCVState *env, int csrno,
1532 target_ulong *val)
1533{
1534 *val = env->mmte & UMTE_MASK;
1535 return RISCV_EXCP_NONE;
1536}
1537
1538static RISCVException write_umte(CPURISCVState *env, int csrno,
1539 target_ulong val)
1540{
1541 target_ulong wpri_val = val & UMTE_MASK;
1542
1543 if (val != wpri_val) {
1544 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1545 "UMTE: WPRI violation written 0x", val,
1546 "vs expected 0x", wpri_val);
1547 }
1548
1549 if (check_pm_current_disabled(env, csrno)) {
1550 return RISCV_EXCP_NONE;
1551 }
1552
1553 wpri_val |= (env->mmte & ~UMTE_MASK);
1554 write_mmte(env, csrno, wpri_val);
1555 return RISCV_EXCP_NONE;
1556}
1557
1558static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1559 target_ulong *val)
1560{
1561 *val = env->mpmmask;
1562 return RISCV_EXCP_NONE;
1563}
1564
1565static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1566 target_ulong val)
1567{
1568 uint64_t mstatus;
1569
1570 env->mpmmask = val;
1571 env->mmte |= PM_EXT_DIRTY;
1572
1573
1574 mstatus = env->mstatus | MSTATUS_XS;
1575 write_mstatus(env, csrno, mstatus);
1576 return RISCV_EXCP_NONE;
1577}
1578
1579static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1580 target_ulong *val)
1581{
1582 *val = env->spmmask;
1583 return RISCV_EXCP_NONE;
1584}
1585
1586static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1587 target_ulong val)
1588{
1589 uint64_t mstatus;
1590
1591
1592 if (check_pm_current_disabled(env, csrno)) {
1593 return RISCV_EXCP_NONE;
1594 }
1595 env->spmmask = val;
1596 env->mmte |= PM_EXT_DIRTY;
1597
1598
1599 mstatus = env->mstatus | MSTATUS_XS;
1600 write_mstatus(env, csrno, mstatus);
1601 return RISCV_EXCP_NONE;
1602}
1603
1604static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1605 target_ulong *val)
1606{
1607 *val = env->upmmask;
1608 return RISCV_EXCP_NONE;
1609}
1610
1611static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1612 target_ulong val)
1613{
1614 uint64_t mstatus;
1615
1616
1617 if (check_pm_current_disabled(env, csrno)) {
1618 return RISCV_EXCP_NONE;
1619 }
1620 env->upmmask = val;
1621 env->mmte |= PM_EXT_DIRTY;
1622
1623
1624 mstatus = env->mstatus | MSTATUS_XS;
1625 write_mstatus(env, csrno, mstatus);
1626 return RISCV_EXCP_NONE;
1627}
1628
1629static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1630 target_ulong *val)
1631{
1632 *val = env->mpmbase;
1633 return RISCV_EXCP_NONE;
1634}
1635
1636static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1637 target_ulong val)
1638{
1639 uint64_t mstatus;
1640
1641 env->mpmbase = val;
1642 env->mmte |= PM_EXT_DIRTY;
1643
1644
1645 mstatus = env->mstatus | MSTATUS_XS;
1646 write_mstatus(env, csrno, mstatus);
1647 return RISCV_EXCP_NONE;
1648}
1649
1650static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1651 target_ulong *val)
1652{
1653 *val = env->spmbase;
1654 return RISCV_EXCP_NONE;
1655}
1656
1657static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1658 target_ulong val)
1659{
1660 uint64_t mstatus;
1661
1662
1663 if (check_pm_current_disabled(env, csrno)) {
1664 return RISCV_EXCP_NONE;
1665 }
1666 env->spmbase = val;
1667 env->mmte |= PM_EXT_DIRTY;
1668
1669
1670 mstatus = env->mstatus | MSTATUS_XS;
1671 write_mstatus(env, csrno, mstatus);
1672 return RISCV_EXCP_NONE;
1673}
1674
1675static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1676 target_ulong *val)
1677{
1678 *val = env->upmbase;
1679 return RISCV_EXCP_NONE;
1680}
1681
1682static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1683 target_ulong val)
1684{
1685 uint64_t mstatus;
1686
1687
1688 if (check_pm_current_disabled(env, csrno)) {
1689 return RISCV_EXCP_NONE;
1690 }
1691 env->upmbase = val;
1692 env->mmte |= PM_EXT_DIRTY;
1693
1694
1695 mstatus = env->mstatus | MSTATUS_XS;
1696 write_mstatus(env, csrno, mstatus);
1697 return RISCV_EXCP_NONE;
1698}
1699
1700#endif
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1712 target_ulong *ret_value,
1713 target_ulong new_value, target_ulong write_mask)
1714{
1715 RISCVException ret;
1716 target_ulong old_value;
1717 RISCVCPU *cpu = env_archcpu(env);
1718 int read_only = get_field(csrno, 0xC00) == 3;
1719
1720
1721#if !defined(CONFIG_USER_ONLY)
1722 int effective_priv = env->priv;
1723
1724 if (riscv_has_ext(env, RVH) &&
1725 env->priv == PRV_S &&
1726 !riscv_cpu_virt_enabled(env)) {
1727
1728
1729
1730
1731
1732 effective_priv++;
1733 }
1734
1735 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1736 return RISCV_EXCP_ILLEGAL_INST;
1737 }
1738#endif
1739 if (write_mask && read_only) {
1740 return RISCV_EXCP_ILLEGAL_INST;
1741 }
1742
1743
1744 if (!cpu->cfg.ext_icsr) {
1745 return RISCV_EXCP_ILLEGAL_INST;
1746 }
1747
1748
1749 if (!csr_ops[csrno].predicate) {
1750 return RISCV_EXCP_ILLEGAL_INST;
1751 }
1752 ret = csr_ops[csrno].predicate(env, csrno);
1753 if (ret != RISCV_EXCP_NONE) {
1754 return ret;
1755 }
1756
1757
1758 if (csr_ops[csrno].op) {
1759 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1760 }
1761
1762
1763 if (!csr_ops[csrno].read) {
1764 return RISCV_EXCP_ILLEGAL_INST;
1765 }
1766
1767 ret = csr_ops[csrno].read(env, csrno, &old_value);
1768 if (ret != RISCV_EXCP_NONE) {
1769 return ret;
1770 }
1771
1772
1773 if (write_mask) {
1774 new_value = (old_value & ~write_mask) | (new_value & write_mask);
1775 if (csr_ops[csrno].write) {
1776 ret = csr_ops[csrno].write(env, csrno, new_value);
1777 if (ret != RISCV_EXCP_NONE) {
1778 return ret;
1779 }
1780 }
1781 }
1782
1783
1784 if (ret_value) {
1785 *ret_value = old_value;
1786 }
1787
1788 return RISCV_EXCP_NONE;
1789}
1790
1791
1792
1793
1794
1795RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
1796 target_ulong *ret_value,
1797 target_ulong new_value,
1798 target_ulong write_mask)
1799{
1800 RISCVException ret;
1801#if !defined(CONFIG_USER_ONLY)
1802 env->debugger = true;
1803#endif
1804 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1805#if !defined(CONFIG_USER_ONLY)
1806 env->debugger = false;
1807#endif
1808 return ret;
1809}
1810
1811
1812riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1813
1814 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
1815 [CSR_FRM] = { "frm", fs, read_frm, write_frm },
1816 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
1817
1818 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
1819 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
1820 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
1821 [CSR_VL] = { "vl", vs, read_vl },
1822 [CSR_VTYPE] = { "vtype", vs, read_vtype },
1823
1824 [CSR_CYCLE] = { "cycle", ctr, read_instret },
1825 [CSR_INSTRET] = { "instret", ctr, read_instret },
1826 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
1827 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
1828
1829
1830
1831
1832
1833 [CSR_TIME] = { "time", ctr, read_time },
1834 [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
1835
1836#if !defined(CONFIG_USER_ONLY)
1837
1838 [CSR_MCYCLE] = { "mcycle", any, read_instret },
1839 [CSR_MINSTRET] = { "minstret", any, read_instret },
1840 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
1841 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
1842
1843
1844 [CSR_MVENDORID] = { "mvendorid", any, read_zero },
1845 [CSR_MARCHID] = { "marchid", any, read_zero },
1846 [CSR_MIMPID] = { "mimpid", any, read_zero },
1847 [CSR_MHARTID] = { "mhartid", any, read_mhartid },
1848
1849
1850 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
1851 [CSR_MISA] = { "misa", any, read_misa, write_misa },
1852 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
1853 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
1854 [CSR_MIE] = { "mie", any, read_mie, write_mie },
1855 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
1856 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
1857
1858 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
1859
1860
1861 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
1862 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
1863 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
1864 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
1865 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
1866
1867
1868 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
1869 [CSR_SIE] = { "sie", smode, read_sie, write_sie },
1870 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
1871 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
1872
1873
1874 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
1875 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
1876 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
1877 [CSR_STVAL] = { "stval", smode, read_stval, write_stval },
1878 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
1879
1880
1881 [CSR_SATP] = { "satp", smode, read_satp, write_satp },
1882
1883 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
1884 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
1885 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
1886 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
1887 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
1888 [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
1889 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
1890 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie },
1891 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
1892 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
1893 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip },
1894 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
1895 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
1896 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
1897
1898 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
1899 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
1900 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
1901 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
1902 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
1903 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
1904 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
1905 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
1906 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
1907
1908 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
1909 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
1910
1911
1912 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
1913 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
1914 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
1915 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
1916 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
1917 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
1918 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
1919 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
1920 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr },
1921 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr },
1922 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },
1923 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr },
1924 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr },
1925 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr },
1926 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr },
1927 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
1928 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
1929 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
1930 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
1931 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
1932 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
1933
1934
1935 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
1936 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
1937 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
1938
1939 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
1940 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
1941 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
1942
1943 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
1944 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
1945 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
1946
1947
1948 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
1949 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
1950 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
1951 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
1952 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
1953 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
1954 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
1955 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
1956 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
1957 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
1958 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
1959 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
1960 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
1961 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
1962 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
1963 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
1964 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
1965 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
1966 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
1967 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
1968 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
1969 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
1970 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
1971 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
1972 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
1973 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
1974 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
1975 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
1976 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
1977
1978 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
1979 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
1980 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
1981 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
1982 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
1983 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
1984 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
1985 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
1986 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
1987 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
1988 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
1989 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
1990 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
1991 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
1992 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
1993 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
1994 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
1995 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
1996 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
1997 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
1998 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
1999 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
2000 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
2001 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
2002 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
2003 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
2004 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
2005 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
2006 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
2007
2008 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
2009 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
2010 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
2011 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
2012 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
2013 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
2014 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
2015 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
2016 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
2017 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
2018 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
2019 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
2020 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
2021 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
2022 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
2023 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
2024 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
2025 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
2026 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
2027 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
2028 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
2029 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
2030 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
2031 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
2032 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
2033 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
2034 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
2035 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
2036 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
2037
2038 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
2039 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
2040 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
2041 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
2042 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
2043 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
2044 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
2045 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
2046 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
2047 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
2048 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
2049 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
2050 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
2051 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
2052 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
2053 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
2054 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
2055 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
2056 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
2057 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
2058 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
2059 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
2060 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
2061 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
2062 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
2063 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
2064 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
2065 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
2066 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
2067
2068 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
2069 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
2070 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
2071 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
2072 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
2073 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
2074 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
2075 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
2076 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
2077 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
2078 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
2079 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
2080 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
2081 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
2082 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
2083 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
2084 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
2085 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
2086 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
2087 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
2088 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
2089 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
2090 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
2091 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
2092 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
2093 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
2094 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
2095 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
2096 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
2097#endif
2098};
2099
