qemu/target/xtensa/core-fsf/xtensa-modules.inc.c
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   1/* Xtensa configuration-specific ISA information.
   2   Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
   3
   4   This file is part of BFD, the Binary File Descriptor library.
   5
   6   This program is free software; you can redistribute it and/or
   7   modify it under the terms of the GNU General Public License as
   8   published by the Free Software Foundation; either version 2 of the
   9   License, or (at your option) any later version.
  10
  11   This program is distributed in the hope that it will be useful,
  12   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14   General Public License for more details.
  15
  16   You should have received a copy of the GNU General Public License
  17   along with this program; if not, write to the Free Software
  18   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  19   02110-1301, USA.  */
  20
  21#include "qemu/osdep.h"
  22#include "xtensa-isa.h"
  23#include "xtensa-isa-internal.h"
  24
  25
  26/* Sysregs.  */
  27
  28static xtensa_sysreg_internal sysregs[] = {
  29  { "LBEG", 0, 0 },
  30  { "LEND", 1, 0 },
  31  { "LCOUNT", 2, 0 },
  32  { "PTEVADDR", 83, 0 },
  33  { "DDR", 104, 0 },
  34  { "176", 176, 0 },
  35  { "208", 208, 0 },
  36  { "INTERRUPT", 226, 0 },
  37  { "INTCLEAR", 227, 0 },
  38  { "CCOUNT", 234, 0 },
  39  { "PRID", 235, 0 },
  40  { "ICOUNT", 236, 0 },
  41  { "CCOMPARE0", 240, 0 },
  42  { "CCOMPARE1", 241, 0 },
  43  { "CCOMPARE2", 242, 0 },
  44  { "EPC1", 177, 0 },
  45  { "EPC2", 178, 0 },
  46  { "EPC3", 179, 0 },
  47  { "EPC4", 180, 0 },
  48  { "EXCSAVE1", 209, 0 },
  49  { "EXCSAVE2", 210, 0 },
  50  { "EXCSAVE3", 211, 0 },
  51  { "EXCSAVE4", 212, 0 },
  52  { "EPS2", 194, 0 },
  53  { "EPS3", 195, 0 },
  54  { "EPS4", 196, 0 },
  55  { "EXCCAUSE", 232, 0 },
  56  { "DEPC", 192, 0 },
  57  { "EXCVADDR", 238, 0 },
  58  { "WINDOWBASE", 72, 0 },
  59  { "WINDOWSTART", 73, 0 },
  60  { "SAR", 3, 0 },
  61  { "LITBASE", 5, 0 },
  62  { "PS", 230, 0 },
  63  { "MISC0", 244, 0 },
  64  { "MISC1", 245, 0 },
  65  { "INTENABLE", 228, 0 },
  66  { "DBREAKA0", 144, 0 },
  67  { "DBREAKC0", 160, 0 },
  68  { "DBREAKA1", 145, 0 },
  69  { "DBREAKC1", 161, 0 },
  70  { "IBREAKA0", 128, 0 },
  71  { "IBREAKA1", 129, 0 },
  72  { "IBREAKENABLE", 96, 0 },
  73  { "ICOUNTLEVEL", 237, 0 },
  74  { "DEBUGCAUSE", 233, 0 },
  75  { "RASID", 90, 0 },
  76  { "ITLBCFG", 91, 0 },
  77  { "DTLBCFG", 92, 0 }
  78};
  79
  80#define NUM_SYSREGS 49
  81#define MAX_SPECIAL_REG 245
  82#define MAX_USER_REG 0
  83
  84
  85/* Processor states.  */
  86
  87static xtensa_state_internal states[] = {
  88  { "LCOUNT", 32, 0 },
  89  { "PC", 32, 0 },
  90  { "ICOUNT", 32, 0 },
  91  { "DDR", 32, 0 },
  92  { "INTERRUPT", 17, 0 },
  93  { "CCOUNT", 32, 0 },
  94  { "XTSYNC", 1, 0 },
  95  { "EPC1", 32, 0 },
  96  { "EPC2", 32, 0 },
  97  { "EPC3", 32, 0 },
  98  { "EPC4", 32, 0 },
  99  { "EXCSAVE1", 32, 0 },
 100  { "EXCSAVE2", 32, 0 },
 101  { "EXCSAVE3", 32, 0 },
 102  { "EXCSAVE4", 32, 0 },
 103  { "EPS2", 15, 0 },
 104  { "EPS3", 15, 0 },
 105  { "EPS4", 15, 0 },
 106  { "EXCCAUSE", 6, 0 },
 107  { "PSINTLEVEL", 4, 0 },
 108  { "PSUM", 1, 0 },
 109  { "PSWOE", 1, 0 },
 110  { "PSRING", 2, 0 },
 111  { "PSEXCM", 1, 0 },
 112  { "DEPC", 32, 0 },
 113  { "EXCVADDR", 32, 0 },
 114  { "WindowBase", 4, 0 },
 115  { "WindowStart", 16, 0 },
 116  { "PSCALLINC", 2, 0 },
 117  { "PSOWB", 4, 0 },
 118  { "LBEG", 32, 0 },
 119  { "LEND", 32, 0 },
 120  { "SAR", 6, 0 },
 121  { "LITBADDR", 20, 0 },
 122  { "LITBEN", 1, 0 },
 123  { "MISC0", 32, 0 },
 124  { "MISC1", 32, 0 },
 125  { "InOCDMode", 1, 0 },
 126  { "INTENABLE", 17, 0 },
 127  { "DBREAKA0", 32, 0 },
 128  { "DBREAKC0", 8, 0 },
 129  { "DBREAKA1", 32, 0 },
 130  { "DBREAKC1", 8, 0 },
 131  { "IBREAKA0", 32, 0 },
 132  { "IBREAKA1", 32, 0 },
 133  { "IBREAKENABLE", 2, 0 },
 134  { "ICOUNTLEVEL", 4, 0 },
 135  { "DEBUGCAUSE", 6, 0 },
 136  { "DBNUM", 4, 0 },
 137  { "CCOMPARE0", 32, 0 },
 138  { "CCOMPARE1", 32, 0 },
 139  { "CCOMPARE2", 32, 0 },
 140  { "ASID3", 8, 0 },
 141  { "ASID2", 8, 0 },
 142  { "ASID1", 8, 0 },
 143  { "INSTPGSZID4", 2, 0 },
 144  { "DATAPGSZID4", 2, 0 },
 145  { "PTBASE", 10, 0 }
 146};
 147
 148#define NUM_STATES 58
 149
 150/* Macros for xtensa_state numbers (for use in iclasses because the
 151   state numbers are not available when the iclass table is generated).  */
 152
 153#define STATE_LCOUNT 0
 154#define STATE_PC 1
 155#define STATE_ICOUNT 2
 156#define STATE_DDR 3
 157#define STATE_INTERRUPT 4
 158#define STATE_CCOUNT 5
 159#define STATE_XTSYNC 6
 160#define STATE_EPC1 7
 161#define STATE_EPC2 8
 162#define STATE_EPC3 9
 163#define STATE_EPC4 10
 164#define STATE_EXCSAVE1 11
 165#define STATE_EXCSAVE2 12
 166#define STATE_EXCSAVE3 13
 167#define STATE_EXCSAVE4 14
 168#define STATE_EPS2 15
 169#define STATE_EPS3 16
 170#define STATE_EPS4 17
 171#define STATE_EXCCAUSE 18
 172#define STATE_PSINTLEVEL 19
 173#define STATE_PSUM 20
 174#define STATE_PSWOE 21
 175#define STATE_PSRING 22
 176#define STATE_PSEXCM 23
 177#define STATE_DEPC 24
 178#define STATE_EXCVADDR 25
 179#define STATE_WindowBase 26
 180#define STATE_WindowStart 27
 181#define STATE_PSCALLINC 28
 182#define STATE_PSOWB 29
 183#define STATE_LBEG 30
 184#define STATE_LEND 31
 185#define STATE_SAR 32
 186#define STATE_LITBADDR 33
 187#define STATE_LITBEN 34
 188#define STATE_MISC0 35
 189#define STATE_MISC1 36
 190#define STATE_InOCDMode 37
 191#define STATE_INTENABLE 38
 192#define STATE_DBREAKA0 39
 193#define STATE_DBREAKC0 40
 194#define STATE_DBREAKA1 41
 195#define STATE_DBREAKC1 42
 196#define STATE_IBREAKA0 43
 197#define STATE_IBREAKA1 44
 198#define STATE_IBREAKENABLE 45
 199#define STATE_ICOUNTLEVEL 46
 200#define STATE_DEBUGCAUSE 47
 201#define STATE_DBNUM 48
 202#define STATE_CCOMPARE0 49
 203#define STATE_CCOMPARE1 50
 204#define STATE_CCOMPARE2 51
 205#define STATE_ASID3 52
 206#define STATE_ASID2 53
 207#define STATE_ASID1 54
 208#define STATE_INSTPGSZID4 55
 209#define STATE_DATAPGSZID4 56
 210#define STATE_PTBASE 57
 211
 212
 213/* Field definitions.  */
 214
 215static unsigned
 216Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 217{
 218  unsigned tie_t = 0;
 219  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 220  return tie_t;
 221}
 222
 223static void
 224Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 225{
 226  uint32 tie_t;
 227  tie_t = (val << 28) >> 28;
 228  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 229}
 230
 231static unsigned
 232Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 233{
 234  unsigned tie_t = 0;
 235  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 236  return tie_t;
 237}
 238
 239static void
 240Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 241{
 242  uint32 tie_t;
 243  tie_t = (val << 28) >> 28;
 244  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 245}
 246
 247static unsigned
 248Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 249{
 250  unsigned tie_t = 0;
 251  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 252  return tie_t;
 253}
 254
 255static void
 256Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 257{
 258  uint32 tie_t;
 259  tie_t = (val << 28) >> 28;
 260  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 261}
 262
 263static unsigned
 264Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 265{
 266  unsigned tie_t = 0;
 267  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 268  return tie_t;
 269}
 270
 271static void
 272Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 273{
 274  uint32 tie_t;
 275  tie_t = (val << 28) >> 28;
 276  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 277}
 278
 279static unsigned
 280Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 281{
 282  unsigned tie_t = 0;
 283  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 284  return tie_t;
 285}
 286
 287static void
 288Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 289{
 290  uint32 tie_t;
 291  tie_t = (val << 28) >> 28;
 292  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 293}
 294
 295static unsigned
 296Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 297{
 298  unsigned tie_t = 0;
 299  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 300  return tie_t;
 301}
 302
 303static void
 304Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 305{
 306  uint32 tie_t;
 307  tie_t = (val << 28) >> 28;
 308  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 309}
 310
 311static unsigned
 312Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 313{
 314  unsigned tie_t = 0;
 315  tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 316  return tie_t;
 317}
 318
 319static void
 320Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 321{
 322  uint32 tie_t;
 323  tie_t = (val << 30) >> 30;
 324  insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 325}
 326
 327static unsigned
 328Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 329{
 330  unsigned tie_t = 0;
 331  tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 332  return tie_t;
 333}
 334
 335static void
 336Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 337{
 338  uint32 tie_t;
 339  tie_t = (val << 30) >> 30;
 340  insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 341}
 342
 343static unsigned
 344Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 345{
 346  unsigned tie_t = 0;
 347  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 348  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 349  return tie_t;
 350}
 351
 352static void
 353Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 354{
 355  uint32 tie_t;
 356  tie_t = (val << 28) >> 28;
 357  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 358  tie_t = (val << 24) >> 28;
 359  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 360}
 361
 362static unsigned
 363Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 364{
 365  unsigned tie_t = 0;
 366  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
 367  return tie_t;
 368}
 369
 370static void
 371Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 372{
 373  uint32 tie_t;
 374  tie_t = (val << 29) >> 29;
 375  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
 376}
 377
 378static unsigned
 379Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 380{
 381  unsigned tie_t = 0;
 382  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 383  return tie_t;
 384}
 385
 386static void
 387Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 388{
 389  uint32 tie_t;
 390  tie_t = (val << 28) >> 28;
 391  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 392}
 393
 394static unsigned
 395Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 396{
 397  unsigned tie_t = 0;
 398  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 399  return tie_t;
 400}
 401
 402static void
 403Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 404{
 405  uint32 tie_t;
 406  tie_t = (val << 28) >> 28;
 407  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 408}
 409
 410static unsigned
 411Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 412{
 413  unsigned tie_t = 0;
 414  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 415  return tie_t;
 416}
 417
 418static void
 419Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 420{
 421  uint32 tie_t;
 422  tie_t = (val << 28) >> 28;
 423  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 424}
 425
 426static unsigned
 427Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 428{
 429  unsigned tie_t = 0;
 430  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 431  return tie_t;
 432}
 433
 434static void
 435Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 436{
 437  uint32 tie_t;
 438  tie_t = (val << 28) >> 28;
 439  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 440}
 441
 442static unsigned
 443Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
 444{
 445  unsigned tie_t = 0;
 446  tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
 447  return tie_t;
 448}
 449
 450static void
 451Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 452{
 453  uint32 tie_t;
 454  tie_t = (val << 31) >> 31;
 455  insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
 456}
 457
 458static unsigned
 459Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 460{
 461  unsigned tie_t = 0;
 462  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 463  return tie_t;
 464}
 465
 466static void
 467Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 468{
 469  uint32 tie_t;
 470  tie_t = (val << 31) >> 31;
 471  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 472}
 473
 474static unsigned
 475Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 476{
 477  unsigned tie_t = 0;
 478  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 479  return tie_t;
 480}
 481
 482static void
 483Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 484{
 485  uint32 tie_t;
 486  tie_t = (val << 28) >> 28;
 487  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 488}
 489
 490static unsigned
 491Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 492{
 493  unsigned tie_t = 0;
 494  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 495  return tie_t;
 496}
 497
 498static void
 499Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 500{
 501  uint32 tie_t;
 502  tie_t = (val << 28) >> 28;
 503  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 504}
 505
 506static unsigned
 507Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 508{
 509  unsigned tie_t = 0;
 510  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 511  return tie_t;
 512}
 513
 514static void
 515Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 516{
 517  uint32 tie_t;
 518  tie_t = (val << 31) >> 31;
 519  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 520}
 521
 522static unsigned
 523Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 524{
 525  unsigned tie_t = 0;
 526  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 527  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 528  return tie_t;
 529}
 530
 531static void
 532Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 533{
 534  uint32 tie_t;
 535  tie_t = (val << 28) >> 28;
 536  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 537  tie_t = (val << 27) >> 31;
 538  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 539}
 540
 541static unsigned
 542Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 543{
 544  unsigned tie_t = 0;
 545  tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
 546  return tie_t;
 547}
 548
 549static void
 550Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 551{
 552  uint32 tie_t;
 553  tie_t = (val << 20) >> 20;
 554  insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
 555}
 556
 557static unsigned
 558Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 559{
 560  unsigned tie_t = 0;
 561  tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 562  return tie_t;
 563}
 564
 565static void
 566Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 567{
 568  uint32 tie_t;
 569  tie_t = (val << 24) >> 24;
 570  insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 571}
 572
 573static unsigned
 574Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 575{
 576  unsigned tie_t = 0;
 577  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 578  return tie_t;
 579}
 580
 581static void
 582Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 583{
 584  uint32 tie_t;
 585  tie_t = (val << 28) >> 28;
 586  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 587}
 588
 589static unsigned
 590Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 591{
 592  unsigned tie_t = 0;
 593  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 594  tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 595  return tie_t;
 596}
 597
 598static void
 599Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 600{
 601  uint32 tie_t;
 602  tie_t = (val << 24) >> 24;
 603  insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 604  tie_t = (val << 20) >> 28;
 605  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 606}
 607
 608static unsigned
 609Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 610{
 611  unsigned tie_t = 0;
 612  tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
 613  return tie_t;
 614}
 615
 616static void
 617Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 618{
 619  uint32 tie_t;
 620  tie_t = (val << 16) >> 16;
 621  insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
 622}
 623
 624static unsigned
 625Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 626{
 627  unsigned tie_t = 0;
 628  tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
 629  return tie_t;
 630}
 631
 632static void
 633Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 634{
 635  uint32 tie_t;
 636  tie_t = (val << 14) >> 14;
 637  insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
 638}
 639
 640static unsigned
 641Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 642{
 643  unsigned tie_t = 0;
 644  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 645  return tie_t;
 646}
 647
 648static void
 649Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 650{
 651  uint32 tie_t;
 652  tie_t = (val << 28) >> 28;
 653  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 654}
 655
 656static unsigned
 657Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 658{
 659  unsigned tie_t = 0;
 660  tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 661  return tie_t;
 662}
 663
 664static void
 665Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 666{
 667  uint32 tie_t;
 668  tie_t = (val << 31) >> 31;
 669  insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 670}
 671
 672static unsigned
 673Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 674{
 675  unsigned tie_t = 0;
 676  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 677  return tie_t;
 678}
 679
 680static void
 681Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 682{
 683  uint32 tie_t;
 684  tie_t = (val << 31) >> 31;
 685  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 686}
 687
 688static unsigned
 689Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
 690{
 691  unsigned tie_t = 0;
 692  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 693  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 694  return tie_t;
 695}
 696
 697static void
 698Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 699{
 700  uint32 tie_t;
 701  tie_t = (val << 28) >> 28;
 702  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 703  tie_t = (val << 27) >> 31;
 704  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 705}
 706
 707static unsigned
 708Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
 709{
 710  unsigned tie_t = 0;
 711  tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 712  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 713  return tie_t;
 714}
 715
 716static void
 717Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 718{
 719  uint32 tie_t;
 720  tie_t = (val << 28) >> 28;
 721  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 722  tie_t = (val << 27) >> 31;
 723  insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 724}
 725
 726static unsigned
 727Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
 728{
 729  unsigned tie_t = 0;
 730  tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 731  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 732  return tie_t;
 733}
 734
 735static void
 736Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 737{
 738  uint32 tie_t;
 739  tie_t = (val << 28) >> 28;
 740  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 741  tie_t = (val << 27) >> 31;
 742  insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 743}
 744
 745static unsigned
 746Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
 747{
 748  unsigned tie_t = 0;
 749  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 750  return tie_t;
 751}
 752
 753static void
 754Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 755{
 756  uint32 tie_t;
 757  tie_t = (val << 31) >> 31;
 758  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 759}
 760
 761static unsigned
 762Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
 763{
 764  unsigned tie_t = 0;
 765  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 766  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 767  return tie_t;
 768}
 769
 770static void
 771Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 772{
 773  uint32 tie_t;
 774  tie_t = (val << 28) >> 28;
 775  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 776  tie_t = (val << 27) >> 31;
 777  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 778}
 779
 780static unsigned
 781Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
 782{
 783  unsigned tie_t = 0;
 784  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 785  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 786  return tie_t;
 787}
 788
 789static void
 790Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 791{
 792  uint32 tie_t;
 793  tie_t = (val << 28) >> 28;
 794  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 795  tie_t = (val << 24) >> 28;
 796  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 797}
 798
 799static unsigned
 800Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
 801{
 802  unsigned tie_t = 0;
 803  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 804  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 805  return tie_t;
 806}
 807
 808static void
 809Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 810{
 811  uint32 tie_t;
 812  tie_t = (val << 28) >> 28;
 813  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 814  tie_t = (val << 24) >> 28;
 815  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 816}
 817
 818static unsigned
 819Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 820{
 821  unsigned tie_t = 0;
 822  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 823  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 824  return tie_t;
 825}
 826
 827static void
 828Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 829{
 830  uint32 tie_t;
 831  tie_t = (val << 28) >> 28;
 832  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 833  tie_t = (val << 24) >> 28;
 834  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 835}
 836
 837static unsigned
 838Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
 839{
 840  unsigned tie_t = 0;
 841  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 842  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 843  return tie_t;
 844}
 845
 846static void
 847Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 848{
 849  uint32 tie_t;
 850  tie_t = (val << 28) >> 28;
 851  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 852  tie_t = (val << 24) >> 28;
 853  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 854}
 855
 856static unsigned
 857Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
 858{
 859  unsigned tie_t = 0;
 860  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 861  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 862  return tie_t;
 863}
 864
 865static void
 866Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 867{
 868  uint32 tie_t;
 869  tie_t = (val << 28) >> 28;
 870  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 871  tie_t = (val << 24) >> 28;
 872  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 873}
 874
 875static unsigned
 876Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
 877{
 878  unsigned tie_t = 0;
 879  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 880  return tie_t;
 881}
 882
 883static void
 884Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 885{
 886  uint32 tie_t;
 887  tie_t = (val << 28) >> 28;
 888  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 889}
 890
 891static unsigned
 892Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
 893{
 894  unsigned tie_t = 0;
 895  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 896  return tie_t;
 897}
 898
 899static void
 900Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 901{
 902  uint32 tie_t;
 903  tie_t = (val << 28) >> 28;
 904  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 905}
 906
 907static unsigned
 908Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
 909{
 910  unsigned tie_t = 0;
 911  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 912  return tie_t;
 913}
 914
 915static void
 916Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 917{
 918  uint32 tie_t;
 919  tie_t = (val << 28) >> 28;
 920  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 921}
 922
 923static unsigned
 924Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
 925{
 926  unsigned tie_t = 0;
 927  tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 928  tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 929  return tie_t;
 930}
 931
 932static void
 933Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 934{
 935  uint32 tie_t;
 936  tie_t = (val << 30) >> 30;
 937  insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 938  tie_t = (val << 28) >> 30;
 939  insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 940}
 941
 942static unsigned
 943Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
 944{
 945  unsigned tie_t = 0;
 946  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 947  return tie_t;
 948}
 949
 950static void
 951Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 952{
 953  uint32 tie_t;
 954  tie_t = (val << 31) >> 31;
 955  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 956}
 957
 958static unsigned
 959Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
 960{
 961  unsigned tie_t = 0;
 962  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 963  return tie_t;
 964}
 965
 966static void
 967Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 968{
 969  uint32 tie_t;
 970  tie_t = (val << 28) >> 28;
 971  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 972}
 973
 974static unsigned
 975Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
 976{
 977  unsigned tie_t = 0;
 978  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 979  return tie_t;
 980}
 981
 982static void
 983Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 984{
 985  uint32 tie_t;
 986  tie_t = (val << 28) >> 28;
 987  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 988}
 989
 990static unsigned
 991Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
 992{
 993  unsigned tie_t = 0;
 994  tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
 995  return tie_t;
 996}
 997
 998static void
 999Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1000{
1001  uint32 tie_t;
1002  tie_t = (val << 30) >> 30;
1003  insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1004}
1005
1006static unsigned
1007Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1008{
1009  unsigned tie_t = 0;
1010  tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1011  return tie_t;
1012}
1013
1014static void
1015Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1016{
1017  uint32 tie_t;
1018  tie_t = (val << 30) >> 30;
1019  insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1020}
1021
1022static unsigned
1023Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1024{
1025  unsigned tie_t = 0;
1026  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1027  return tie_t;
1028}
1029
1030static void
1031Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1032{
1033  uint32 tie_t;
1034  tie_t = (val << 28) >> 28;
1035  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1036}
1037
1038static unsigned
1039Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1040{
1041  unsigned tie_t = 0;
1042  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1043  return tie_t;
1044}
1045
1046static void
1047Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1048{
1049  uint32 tie_t;
1050  tie_t = (val << 28) >> 28;
1051  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1052}
1053
1054static unsigned
1055Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1056{
1057  unsigned tie_t = 0;
1058  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1059  return tie_t;
1060}
1061
1062static void
1063Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1064{
1065  uint32 tie_t;
1066  tie_t = (val << 29) >> 29;
1067  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1068}
1069
1070static unsigned
1071Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1072{
1073  unsigned tie_t = 0;
1074  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1075  return tie_t;
1076}
1077
1078static void
1079Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1080{
1081  uint32 tie_t;
1082  tie_t = (val << 29) >> 29;
1083  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1084}
1085
1086static unsigned
1087Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1088{
1089  unsigned tie_t = 0;
1090  tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1091  return tie_t;
1092}
1093
1094static void
1095Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1096{
1097  uint32 tie_t;
1098  tie_t = (val << 31) >> 31;
1099  insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1100}
1101
1102static unsigned
1103Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1104{
1105  unsigned tie_t = 0;
1106  tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1107  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1108  return tie_t;
1109}
1110
1111static void
1112Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1113{
1114  uint32 tie_t;
1115  tie_t = (val << 28) >> 28;
1116  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1117  tie_t = (val << 26) >> 30;
1118  insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1119}
1120
1121static unsigned
1122Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1123{
1124  unsigned tie_t = 0;
1125  tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1126  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1127  return tie_t;
1128}
1129
1130static void
1131Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1132{
1133  uint32 tie_t;
1134  tie_t = (val << 28) >> 28;
1135  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1136  tie_t = (val << 26) >> 30;
1137  insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1138}
1139
1140static unsigned
1141Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1142{
1143  unsigned tie_t = 0;
1144  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1145  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1146  return tie_t;
1147}
1148
1149static void
1150Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1151{
1152  uint32 tie_t;
1153  tie_t = (val << 28) >> 28;
1154  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1155  tie_t = (val << 25) >> 29;
1156  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1157}
1158
1159static unsigned
1160Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1161{
1162  unsigned tie_t = 0;
1163  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1164  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1165  return tie_t;
1166}
1167
1168static void
1169Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1170{
1171  uint32 tie_t;
1172  tie_t = (val << 28) >> 28;
1173  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1174  tie_t = (val << 25) >> 29;
1175  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1176}
1177
1178static void
1179Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1180                    uint32 val ATTRIBUTE_UNUSED)
1181{
1182  /* Do nothing.  */
1183}
1184
1185static unsigned
1186Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1187{
1188  return 0;
1189}
1190
1191static unsigned
1192Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1193{
1194  return 4;
1195}
1196
1197static unsigned
1198Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1199{
1200  return 8;
1201}
1202
1203static unsigned
1204Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1205{
1206  return 12;
1207}
1208
1209
1210/* Functional units.  */
1211
1212static xtensa_funcUnit_internal funcUnits[] = {
1213
1214};
1215
1216
1217/* Register files.  */
1218
1219static xtensa_regfile_internal regfiles[] = {
1220  { "AR", "a", 0, 32, 64 }
1221};
1222
1223
1224/* Interfaces.  */
1225
1226static xtensa_interface_internal interfaces[] = {
1227
1228};
1229
1230
1231/* Constant tables.  */
1232
1233/* constant table ai4c */
1234static const unsigned CONST_TBL_ai4c_0[] = {
1235  0xffffffff,
1236  0x1,
1237  0x2,
1238  0x3,
1239  0x4,
1240  0x5,
1241  0x6,
1242  0x7,
1243  0x8,
1244  0x9,
1245  0xa,
1246  0xb,
1247  0xc,
1248  0xd,
1249  0xe,
1250  0xf,
1251  0
1252};
1253
1254/* constant table b4c */
1255static const unsigned CONST_TBL_b4c_0[] = {
1256  0xffffffff,
1257  0x1,
1258  0x2,
1259  0x3,
1260  0x4,
1261  0x5,
1262  0x6,
1263  0x7,
1264  0x8,
1265  0xa,
1266  0xc,
1267  0x10,
1268  0x20,
1269  0x40,
1270  0x80,
1271  0x100,
1272  0
1273};
1274
1275/* constant table b4cu */
1276static const unsigned CONST_TBL_b4cu_0[] = {
1277  0x8000,
1278  0x10000,
1279  0x2,
1280  0x3,
1281  0x4,
1282  0x5,
1283  0x6,
1284  0x7,
1285  0x8,
1286  0xa,
1287  0xc,
1288  0x10,
1289  0x20,
1290  0x40,
1291  0x80,
1292  0x100,
1293  0
1294};
1295
1296
1297/* Instruction operands.  */
1298
1299static int
1300Operand_soffsetx4_decode (uint32 *valp)
1301{
1302  unsigned soffsetx4_0, offset_0;
1303  offset_0 = *valp & 0x3ffff;
1304  soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1305  *valp = soffsetx4_0;
1306  return 0;
1307}
1308
1309static int
1310Operand_soffsetx4_encode (uint32 *valp)
1311{
1312  unsigned offset_0, soffsetx4_0;
1313  soffsetx4_0 = *valp;
1314  offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1315  *valp = offset_0;
1316  return 0;
1317}
1318
1319static int
1320Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1321{
1322  *valp -= (pc & ~0x3);
1323  return 0;
1324}
1325
1326static int
1327Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1328{
1329  *valp += (pc & ~0x3);
1330  return 0;
1331}
1332
1333static int
1334Operand_uimm12x8_decode (uint32 *valp)
1335{
1336  unsigned uimm12x8_0, imm12_0;
1337  imm12_0 = *valp & 0xfff;
1338  uimm12x8_0 = imm12_0 << 3;
1339  *valp = uimm12x8_0;
1340  return 0;
1341}
1342
1343static int
1344Operand_uimm12x8_encode (uint32 *valp)
1345{
1346  unsigned imm12_0, uimm12x8_0;
1347  uimm12x8_0 = *valp;
1348  imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1349  *valp = imm12_0;
1350  return 0;
1351}
1352
1353static int
1354Operand_simm4_decode (uint32 *valp)
1355{
1356  unsigned simm4_0, mn_0;
1357  mn_0 = *valp & 0xf;
1358  simm4_0 = ((int) mn_0 << 28) >> 28;
1359  *valp = simm4_0;
1360  return 0;
1361}
1362
1363static int
1364Operand_simm4_encode (uint32 *valp)
1365{
1366  unsigned mn_0, simm4_0;
1367  simm4_0 = *valp;
1368  mn_0 = (simm4_0 & 0xf);
1369  *valp = mn_0;
1370  return 0;
1371}
1372
1373static int
1374Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1375{
1376  return 0;
1377}
1378
1379static int
1380Operand_arr_encode (uint32 *valp)
1381{
1382  return (*valp & ~0xf) != 0;
1383}
1384
1385static int
1386Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1387{
1388  return 0;
1389}
1390
1391static int
1392Operand_ars_encode (uint32 *valp)
1393{
1394  return (*valp & ~0xf) != 0;
1395}
1396
1397static int
1398Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1399{
1400  return 0;
1401}
1402
1403static int
1404Operand_art_encode (uint32 *valp)
1405{
1406  return (*valp & ~0xf) != 0;
1407}
1408
1409static int
1410Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1411{
1412  return 0;
1413}
1414
1415static int
1416Operand_ar0_encode (uint32 *valp)
1417{
1418  return (*valp & ~0x3f) != 0;
1419}
1420
1421static int
1422Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1423{
1424  return 0;
1425}
1426
1427static int
1428Operand_ar4_encode (uint32 *valp)
1429{
1430  return (*valp & ~0x3f) != 0;
1431}
1432
1433static int
1434Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1435{
1436  return 0;
1437}
1438
1439static int
1440Operand_ar8_encode (uint32 *valp)
1441{
1442  return (*valp & ~0x3f) != 0;
1443}
1444
1445static int
1446Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1447{
1448  return 0;
1449}
1450
1451static int
1452Operand_ar12_encode (uint32 *valp)
1453{
1454  return (*valp & ~0x3f) != 0;
1455}
1456
1457static int
1458Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1459{
1460  return 0;
1461}
1462
1463static int
1464Operand_ars_entry_encode (uint32 *valp)
1465{
1466  return (*valp & ~0x3f) != 0;
1467}
1468
1469static int
1470Operand_immrx4_decode (uint32 *valp)
1471{
1472  unsigned immrx4_0, r_0;
1473  r_0 = *valp & 0xf;
1474  immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2;
1475  *valp = immrx4_0;
1476  return 0;
1477}
1478
1479static int
1480Operand_immrx4_encode (uint32 *valp)
1481{
1482  unsigned r_0, immrx4_0;
1483  immrx4_0 = *valp;
1484  r_0 = ((immrx4_0 >> 2) & 0xf);
1485  *valp = r_0;
1486  return 0;
1487}
1488
1489static int
1490Operand_lsi4x4_decode (uint32 *valp)
1491{
1492  unsigned lsi4x4_0, r_0;
1493  r_0 = *valp & 0xf;
1494  lsi4x4_0 = r_0 << 2;
1495  *valp = lsi4x4_0;
1496  return 0;
1497}
1498
1499static int
1500Operand_lsi4x4_encode (uint32 *valp)
1501{
1502  unsigned r_0, lsi4x4_0;
1503  lsi4x4_0 = *valp;
1504  r_0 = ((lsi4x4_0 >> 2) & 0xf);
1505  *valp = r_0;
1506  return 0;
1507}
1508
1509static int
1510Operand_simm7_decode (uint32 *valp)
1511{
1512  unsigned simm7_0, imm7_0;
1513  imm7_0 = *valp & 0x7f;
1514  simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1515  *valp = simm7_0;
1516  return 0;
1517}
1518
1519static int
1520Operand_simm7_encode (uint32 *valp)
1521{
1522  unsigned imm7_0, simm7_0;
1523  simm7_0 = *valp;
1524  imm7_0 = (simm7_0 & 0x7f);
1525  *valp = imm7_0;
1526  return 0;
1527}
1528
1529static int
1530Operand_uimm6_decode (uint32 *valp)
1531{
1532  unsigned uimm6_0, imm6_0;
1533  imm6_0 = *valp & 0x3f;
1534  uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0);
1535  *valp = uimm6_0;
1536  return 0;
1537}
1538
1539static int
1540Operand_uimm6_encode (uint32 *valp)
1541{
1542  unsigned imm6_0, uimm6_0;
1543  uimm6_0 = *valp;
1544  imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1545  *valp = imm6_0;
1546  return 0;
1547}
1548
1549static int
1550Operand_uimm6_ator (uint32 *valp, uint32 pc)
1551{
1552  *valp -= pc;
1553  return 0;
1554}
1555
1556static int
1557Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1558{
1559  *valp += pc;
1560  return 0;
1561}
1562
1563static int
1564Operand_ai4const_decode (uint32 *valp)
1565{
1566  unsigned ai4const_0, t_0;
1567  t_0 = *valp & 0xf;
1568  ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1569  *valp = ai4const_0;
1570  return 0;
1571}
1572
1573static int
1574Operand_ai4const_encode (uint32 *valp)
1575{
1576  unsigned t_0, ai4const_0;
1577  ai4const_0 = *valp;
1578  switch (ai4const_0)
1579    {
1580    case 0xffffffff: t_0 = 0; break;
1581    case 0x1: t_0 = 0x1; break;
1582    case 0x2: t_0 = 0x2; break;
1583    case 0x3: t_0 = 0x3; break;
1584    case 0x4: t_0 = 0x4; break;
1585    case 0x5: t_0 = 0x5; break;
1586    case 0x6: t_0 = 0x6; break;
1587    case 0x7: t_0 = 0x7; break;
1588    case 0x8: t_0 = 0x8; break;
1589    case 0x9: t_0 = 0x9; break;
1590    case 0xa: t_0 = 0xa; break;
1591    case 0xb: t_0 = 0xb; break;
1592    case 0xc: t_0 = 0xc; break;
1593    case 0xd: t_0 = 0xd; break;
1594    case 0xe: t_0 = 0xe; break;
1595    default: t_0 = 0xf; break;
1596    }
1597  *valp = t_0;
1598  return 0;
1599}
1600
1601static int
1602Operand_b4const_decode (uint32 *valp)
1603{
1604  unsigned b4const_0, r_0;
1605  r_0 = *valp & 0xf;
1606  b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1607  *valp = b4const_0;
1608  return 0;
1609}
1610
1611static int
1612Operand_b4const_encode (uint32 *valp)
1613{
1614  unsigned r_0, b4const_0;
1615  b4const_0 = *valp;
1616  switch (b4const_0)
1617    {
1618    case 0xffffffff: r_0 = 0; break;
1619    case 0x1: r_0 = 0x1; break;
1620    case 0x2: r_0 = 0x2; break;
1621    case 0x3: r_0 = 0x3; break;
1622    case 0x4: r_0 = 0x4; break;
1623    case 0x5: r_0 = 0x5; break;
1624    case 0x6: r_0 = 0x6; break;
1625    case 0x7: r_0 = 0x7; break;
1626    case 0x8: r_0 = 0x8; break;
1627    case 0xa: r_0 = 0x9; break;
1628    case 0xc: r_0 = 0xa; break;
1629    case 0x10: r_0 = 0xb; break;
1630    case 0x20: r_0 = 0xc; break;
1631    case 0x40: r_0 = 0xd; break;
1632    case 0x80: r_0 = 0xe; break;
1633    default: r_0 = 0xf; break;
1634    }
1635  *valp = r_0;
1636  return 0;
1637}
1638
1639static int
1640Operand_b4constu_decode (uint32 *valp)
1641{
1642  unsigned b4constu_0, r_0;
1643  r_0 = *valp & 0xf;
1644  b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1645  *valp = b4constu_0;
1646  return 0;
1647}
1648
1649static int
1650Operand_b4constu_encode (uint32 *valp)
1651{
1652  unsigned r_0, b4constu_0;
1653  b4constu_0 = *valp;
1654  switch (b4constu_0)
1655    {
1656    case 0x8000: r_0 = 0; break;
1657    case 0x10000: r_0 = 0x1; break;
1658    case 0x2: r_0 = 0x2; break;
1659    case 0x3: r_0 = 0x3; break;
1660    case 0x4: r_0 = 0x4; break;
1661    case 0x5: r_0 = 0x5; break;
1662    case 0x6: r_0 = 0x6; break;
1663    case 0x7: r_0 = 0x7; break;
1664    case 0x8: r_0 = 0x8; break;
1665    case 0xa: r_0 = 0x9; break;
1666    case 0xc: r_0 = 0xa; break;
1667    case 0x10: r_0 = 0xb; break;
1668    case 0x20: r_0 = 0xc; break;
1669    case 0x40: r_0 = 0xd; break;
1670    case 0x80: r_0 = 0xe; break;
1671    default: r_0 = 0xf; break;
1672    }
1673  *valp = r_0;
1674  return 0;
1675}
1676
1677static int
1678Operand_uimm8_decode (uint32 *valp)
1679{
1680  unsigned uimm8_0, imm8_0;
1681  imm8_0 = *valp & 0xff;
1682  uimm8_0 = imm8_0;
1683  *valp = uimm8_0;
1684  return 0;
1685}
1686
1687static int
1688Operand_uimm8_encode (uint32 *valp)
1689{
1690  unsigned imm8_0, uimm8_0;
1691  uimm8_0 = *valp;
1692  imm8_0 = (uimm8_0 & 0xff);
1693  *valp = imm8_0;
1694  return 0;
1695}
1696
1697static int
1698Operand_uimm8x2_decode (uint32 *valp)
1699{
1700  unsigned uimm8x2_0, imm8_0;
1701  imm8_0 = *valp & 0xff;
1702  uimm8x2_0 = imm8_0 << 1;
1703  *valp = uimm8x2_0;
1704  return 0;
1705}
1706
1707static int
1708Operand_uimm8x2_encode (uint32 *valp)
1709{
1710  unsigned imm8_0, uimm8x2_0;
1711  uimm8x2_0 = *valp;
1712  imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1713  *valp = imm8_0;
1714  return 0;
1715}
1716
1717static int
1718Operand_uimm8x4_decode (uint32 *valp)
1719{
1720  unsigned uimm8x4_0, imm8_0;
1721  imm8_0 = *valp & 0xff;
1722  uimm8x4_0 = imm8_0 << 2;
1723  *valp = uimm8x4_0;
1724  return 0;
1725}
1726
1727static int
1728Operand_uimm8x4_encode (uint32 *valp)
1729{
1730  unsigned imm8_0, uimm8x4_0;
1731  uimm8x4_0 = *valp;
1732  imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1733  *valp = imm8_0;
1734  return 0;
1735}
1736
1737static int
1738Operand_uimm4x16_decode (uint32 *valp)
1739{
1740  unsigned uimm4x16_0, op2_0;
1741  op2_0 = *valp & 0xf;
1742  uimm4x16_0 = op2_0 << 4;
1743  *valp = uimm4x16_0;
1744  return 0;
1745}
1746
1747static int
1748Operand_uimm4x16_encode (uint32 *valp)
1749{
1750  unsigned op2_0, uimm4x16_0;
1751  uimm4x16_0 = *valp;
1752  op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1753  *valp = op2_0;
1754  return 0;
1755}
1756
1757static int
1758Operand_simm8_decode (uint32 *valp)
1759{
1760  unsigned simm8_0, imm8_0;
1761  imm8_0 = *valp & 0xff;
1762  simm8_0 = ((int) imm8_0 << 24) >> 24;
1763  *valp = simm8_0;
1764  return 0;
1765}
1766
1767static int
1768Operand_simm8_encode (uint32 *valp)
1769{
1770  unsigned imm8_0, simm8_0;
1771  simm8_0 = *valp;
1772  imm8_0 = (simm8_0 & 0xff);
1773  *valp = imm8_0;
1774  return 0;
1775}
1776
1777static int
1778Operand_simm8x256_decode (uint32 *valp)
1779{
1780  unsigned simm8x256_0, imm8_0;
1781  imm8_0 = *valp & 0xff;
1782  simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1783  *valp = simm8x256_0;
1784  return 0;
1785}
1786
1787static int
1788Operand_simm8x256_encode (uint32 *valp)
1789{
1790  unsigned imm8_0, simm8x256_0;
1791  simm8x256_0 = *valp;
1792  imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1793  *valp = imm8_0;
1794  return 0;
1795}
1796
1797static int
1798Operand_simm12b_decode (uint32 *valp)
1799{
1800  unsigned simm12b_0, imm12b_0;
1801  imm12b_0 = *valp & 0xfff;
1802  simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1803  *valp = simm12b_0;
1804  return 0;
1805}
1806
1807static int
1808Operand_simm12b_encode (uint32 *valp)
1809{
1810  unsigned imm12b_0, simm12b_0;
1811  simm12b_0 = *valp;
1812  imm12b_0 = (simm12b_0 & 0xfff);
1813  *valp = imm12b_0;
1814  return 0;
1815}
1816
1817static int
1818Operand_msalp32_decode (uint32 *valp)
1819{
1820  unsigned msalp32_0, sal_0;
1821  sal_0 = *valp & 0x1f;
1822  msalp32_0 = 0x20 - sal_0;
1823  *valp = msalp32_0;
1824  return 0;
1825}
1826
1827static int
1828Operand_msalp32_encode (uint32 *valp)
1829{
1830  unsigned sal_0, msalp32_0;
1831  msalp32_0 = *valp;
1832  sal_0 = (0x20 - msalp32_0) & 0x1f;
1833  *valp = sal_0;
1834  return 0;
1835}
1836
1837static int
1838Operand_op2p1_decode (uint32 *valp)
1839{
1840  unsigned op2p1_0, op2_0;
1841  op2_0 = *valp & 0xf;
1842  op2p1_0 = op2_0 + 0x1;
1843  *valp = op2p1_0;
1844  return 0;
1845}
1846
1847static int
1848Operand_op2p1_encode (uint32 *valp)
1849{
1850  unsigned op2_0, op2p1_0;
1851  op2p1_0 = *valp;
1852  op2_0 = (op2p1_0 - 0x1) & 0xf;
1853  *valp = op2_0;
1854  return 0;
1855}
1856
1857static int
1858Operand_label8_decode (uint32 *valp)
1859{
1860  unsigned label8_0, imm8_0;
1861  imm8_0 = *valp & 0xff;
1862  label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1863  *valp = label8_0;
1864  return 0;
1865}
1866
1867static int
1868Operand_label8_encode (uint32 *valp)
1869{
1870  unsigned imm8_0, label8_0;
1871  label8_0 = *valp;
1872  imm8_0 = (label8_0 - 0x4) & 0xff;
1873  *valp = imm8_0;
1874  return 0;
1875}
1876
1877static int
1878Operand_label8_ator (uint32 *valp, uint32 pc)
1879{
1880  *valp -= pc;
1881  return 0;
1882}
1883
1884static int
1885Operand_label8_rtoa (uint32 *valp, uint32 pc)
1886{
1887  *valp += pc;
1888  return 0;
1889}
1890
1891static int
1892Operand_ulabel8_decode (uint32 *valp)
1893{
1894  unsigned ulabel8_0, imm8_0;
1895  imm8_0 = *valp & 0xff;
1896  ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0);
1897  *valp = ulabel8_0;
1898  return 0;
1899}
1900
1901static int
1902Operand_ulabel8_encode (uint32 *valp)
1903{
1904  unsigned imm8_0, ulabel8_0;
1905  ulabel8_0 = *valp;
1906  imm8_0 = (ulabel8_0 - 0x4) & 0xff;
1907  *valp = imm8_0;
1908  return 0;
1909}
1910
1911static int
1912Operand_ulabel8_ator (uint32 *valp, uint32 pc)
1913{
1914  *valp -= pc;
1915  return 0;
1916}
1917
1918static int
1919Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
1920{
1921  *valp += pc;
1922  return 0;
1923}
1924
1925static int
1926Operand_label12_decode (uint32 *valp)
1927{
1928  unsigned label12_0, imm12_0;
1929  imm12_0 = *valp & 0xfff;
1930  label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
1931  *valp = label12_0;
1932  return 0;
1933}
1934
1935static int
1936Operand_label12_encode (uint32 *valp)
1937{
1938  unsigned imm12_0, label12_0;
1939  label12_0 = *valp;
1940  imm12_0 = (label12_0 - 0x4) & 0xfff;
1941  *valp = imm12_0;
1942  return 0;
1943}
1944
1945static int
1946Operand_label12_ator (uint32 *valp, uint32 pc)
1947{
1948  *valp -= pc;
1949  return 0;
1950}
1951
1952static int
1953Operand_label12_rtoa (uint32 *valp, uint32 pc)
1954{
1955  *valp += pc;
1956  return 0;
1957}
1958
1959static int
1960Operand_soffset_decode (uint32 *valp)
1961{
1962  unsigned soffset_0, offset_0;
1963  offset_0 = *valp & 0x3ffff;
1964  soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
1965  *valp = soffset_0;
1966  return 0;
1967}
1968
1969static int
1970Operand_soffset_encode (uint32 *valp)
1971{
1972  unsigned offset_0, soffset_0;
1973  soffset_0 = *valp;
1974  offset_0 = (soffset_0 - 0x4) & 0x3ffff;
1975  *valp = offset_0;
1976  return 0;
1977}
1978
1979static int
1980Operand_soffset_ator (uint32 *valp, uint32 pc)
1981{
1982  *valp -= pc;
1983  return 0;
1984}
1985
1986static int
1987Operand_soffset_rtoa (uint32 *valp, uint32 pc)
1988{
1989  *valp += pc;
1990  return 0;
1991}
1992
1993static int
1994Operand_uimm16x4_decode (uint32 *valp)
1995{
1996  unsigned uimm16x4_0, imm16_0;
1997  imm16_0 = *valp & 0xffff;
1998  uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2;
1999  *valp = uimm16x4_0;
2000  return 0;
2001}
2002
2003static int
2004Operand_uimm16x4_encode (uint32 *valp)
2005{
2006  unsigned imm16_0, uimm16x4_0;
2007  uimm16x4_0 = *valp;
2008  imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2009  *valp = imm16_0;
2010  return 0;
2011}
2012
2013static int
2014Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2015{
2016  *valp -= ((pc + 3) & ~0x3);
2017  return 0;
2018}
2019
2020static int
2021Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2022{
2023  *valp += ((pc + 3) & ~0x3);
2024  return 0;
2025}
2026
2027static int
2028Operand_immt_decode (uint32 *valp)
2029{
2030  unsigned immt_0, t_0;
2031  t_0 = *valp & 0xf;
2032  immt_0 = t_0;
2033  *valp = immt_0;
2034  return 0;
2035}
2036
2037static int
2038Operand_immt_encode (uint32 *valp)
2039{
2040  unsigned t_0, immt_0;
2041  immt_0 = *valp;
2042  t_0 = immt_0 & 0xf;
2043  *valp = t_0;
2044  return 0;
2045}
2046
2047static int
2048Operand_imms_decode (uint32 *valp)
2049{
2050  unsigned imms_0, s_0;
2051  s_0 = *valp & 0xf;
2052  imms_0 = s_0;
2053  *valp = imms_0;
2054  return 0;
2055}
2056
2057static int
2058Operand_imms_encode (uint32 *valp)
2059{
2060  unsigned s_0, imms_0;
2061  imms_0 = *valp;
2062  s_0 = imms_0 & 0xf;
2063  *valp = s_0;
2064  return 0;
2065}
2066
2067static xtensa_operand_internal operands[] = {
2068  { "soffsetx4", 10, -1, 0,
2069    XTENSA_OPERAND_IS_PCRELATIVE,
2070    Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2071    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2072  { "uimm12x8", 3, -1, 0,
2073    0,
2074    Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2075    0, 0 },
2076  { "simm4", 26, -1, 0,
2077    0,
2078    Operand_simm4_encode, Operand_simm4_decode,
2079    0, 0 },
2080  { "arr", 14, 0, 1,
2081    XTENSA_OPERAND_IS_REGISTER,
2082    Operand_arr_encode, Operand_arr_decode,
2083    0, 0 },
2084  { "ars", 5, 0, 1,
2085    XTENSA_OPERAND_IS_REGISTER,
2086    Operand_ars_encode, Operand_ars_decode,
2087    0, 0 },
2088  { "*ars_invisible", 5, 0, 1,
2089    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2090    Operand_ars_encode, Operand_ars_decode,
2091    0, 0 },
2092  { "art", 0, 0, 1,
2093    XTENSA_OPERAND_IS_REGISTER,
2094    Operand_art_encode, Operand_art_decode,
2095    0, 0 },
2096  { "ar0", 35, 0, 1,
2097    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2098    Operand_ar0_encode, Operand_ar0_decode,
2099    0, 0 },
2100  { "ar4", 36, 0, 1,
2101    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2102    Operand_ar4_encode, Operand_ar4_decode,
2103    0, 0 },
2104  { "ar8", 37, 0, 1,
2105    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2106    Operand_ar8_encode, Operand_ar8_decode,
2107    0, 0 },
2108  { "ar12", 38, 0, 1,
2109    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2110    Operand_ar12_encode, Operand_ar12_decode,
2111    0, 0 },
2112  { "ars_entry", 5, 0, 1,
2113    XTENSA_OPERAND_IS_REGISTER,
2114    Operand_ars_entry_encode, Operand_ars_entry_decode,
2115    0, 0 },
2116  { "immrx4", 14, -1, 0,
2117    0,
2118    Operand_immrx4_encode, Operand_immrx4_decode,
2119    0, 0 },
2120  { "lsi4x4", 14, -1, 0,
2121    0,
2122    Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2123    0, 0 },
2124  { "simm7", 34, -1, 0,
2125    0,
2126    Operand_simm7_encode, Operand_simm7_decode,
2127    0, 0 },
2128  { "uimm6", 33, -1, 0,
2129    XTENSA_OPERAND_IS_PCRELATIVE,
2130    Operand_uimm6_encode, Operand_uimm6_decode,
2131    Operand_uimm6_ator, Operand_uimm6_rtoa },
2132  { "ai4const", 0, -1, 0,
2133    0,
2134    Operand_ai4const_encode, Operand_ai4const_decode,
2135    0, 0 },
2136  { "b4const", 14, -1, 0,
2137    0,
2138    Operand_b4const_encode, Operand_b4const_decode,
2139    0, 0 },
2140  { "b4constu", 14, -1, 0,
2141    0,
2142    Operand_b4constu_encode, Operand_b4constu_decode,
2143    0, 0 },
2144  { "uimm8", 4, -1, 0,
2145    0,
2146    Operand_uimm8_encode, Operand_uimm8_decode,
2147    0, 0 },
2148  { "uimm8x2", 4, -1, 0,
2149    0,
2150    Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2151    0, 0 },
2152  { "uimm8x4", 4, -1, 0,
2153    0,
2154    Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2155    0, 0 },
2156  { "uimm4x16", 13, -1, 0,
2157    0,
2158    Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2159    0, 0 },
2160  { "simm8", 4, -1, 0,
2161    0,
2162    Operand_simm8_encode, Operand_simm8_decode,
2163    0, 0 },
2164  { "simm8x256", 4, -1, 0,
2165    0,
2166    Operand_simm8x256_encode, Operand_simm8x256_decode,
2167    0, 0 },
2168  { "simm12b", 6, -1, 0,
2169    0,
2170    Operand_simm12b_encode, Operand_simm12b_decode,
2171    0, 0 },
2172  { "msalp32", 18, -1, 0,
2173    0,
2174    Operand_msalp32_encode, Operand_msalp32_decode,
2175    0, 0 },
2176  { "op2p1", 13, -1, 0,
2177    0,
2178    Operand_op2p1_encode, Operand_op2p1_decode,
2179    0, 0 },
2180  { "label8", 4, -1, 0,
2181    XTENSA_OPERAND_IS_PCRELATIVE,
2182    Operand_label8_encode, Operand_label8_decode,
2183    Operand_label8_ator, Operand_label8_rtoa },
2184  { "ulabel8", 4, -1, 0,
2185    XTENSA_OPERAND_IS_PCRELATIVE,
2186    Operand_ulabel8_encode, Operand_ulabel8_decode,
2187    Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2188  { "label12", 3, -1, 0,
2189    XTENSA_OPERAND_IS_PCRELATIVE,
2190    Operand_label12_encode, Operand_label12_decode,
2191    Operand_label12_ator, Operand_label12_rtoa },
2192  { "soffset", 10, -1, 0,
2193    XTENSA_OPERAND_IS_PCRELATIVE,
2194    Operand_soffset_encode, Operand_soffset_decode,
2195    Operand_soffset_ator, Operand_soffset_rtoa },
2196  { "uimm16x4", 7, -1, 0,
2197    XTENSA_OPERAND_IS_PCRELATIVE,
2198    Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2199    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2200  { "immt", 0, -1, 0,
2201    0,
2202    Operand_immt_encode, Operand_immt_decode,
2203    0, 0 },
2204  { "imms", 5, -1, 0,
2205    0,
2206    Operand_imms_encode, Operand_imms_decode,
2207    0, 0 },
2208  { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2209  { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2210  { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2211  { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2212  { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2213  { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2214  { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2215  { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2216  { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2217  { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2218  { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2219  { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2220  { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2221  { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2222  { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2223  { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2224  { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2225  { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2226  { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2227  { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2228  { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2229  { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2230  { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2231  { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2232  { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2233  { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2234  { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2235  { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2236  { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2237  { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2238  { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2239  { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2240  { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2241  { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2242  { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }
2243};
2244
2245
2246/* Iclass table.  */
2247
2248static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2249  { { STATE_PSRING }, 'i' },
2250  { { STATE_PSEXCM }, 'm' },
2251  { { STATE_EPC1 }, 'i' }
2252};
2253
2254static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2255  { { STATE_PSEXCM }, 'i' },
2256  { { STATE_PSRING }, 'i' },
2257  { { STATE_DEPC }, 'i' }
2258};
2259
2260static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2261  { { 0 /* soffsetx4 */ }, 'i' },
2262  { { 10 /* ar12 */ }, 'o' }
2263};
2264
2265static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2266  { { STATE_PSCALLINC }, 'o' }
2267};
2268
2269static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2270  { { 0 /* soffsetx4 */ }, 'i' },
2271  { { 9 /* ar8 */ }, 'o' }
2272};
2273
2274static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2275  { { STATE_PSCALLINC }, 'o' }
2276};
2277
2278static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2279  { { 0 /* soffsetx4 */ }, 'i' },
2280  { { 8 /* ar4 */ }, 'o' }
2281};
2282
2283static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2284  { { STATE_PSCALLINC }, 'o' }
2285};
2286
2287static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2288  { { 4 /* ars */ }, 'i' },
2289  { { 10 /* ar12 */ }, 'o' }
2290};
2291
2292static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2293  { { STATE_PSCALLINC }, 'o' }
2294};
2295
2296static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2297  { { 4 /* ars */ }, 'i' },
2298  { { 9 /* ar8 */ }, 'o' }
2299};
2300
2301static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2302  { { STATE_PSCALLINC }, 'o' }
2303};
2304
2305static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2306  { { 4 /* ars */ }, 'i' },
2307  { { 8 /* ar4 */ }, 'o' }
2308};
2309
2310static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2311  { { STATE_PSCALLINC }, 'o' }
2312};
2313
2314static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2315  { { 11 /* ars_entry */ }, 's' },
2316  { { 4 /* ars */ }, 'i' },
2317  { { 1 /* uimm12x8 */ }, 'i' }
2318};
2319
2320static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2321  { { STATE_PSCALLINC }, 'i' },
2322  { { STATE_PSEXCM }, 'i' },
2323  { { STATE_PSWOE }, 'i' },
2324  { { STATE_WindowBase }, 'm' },
2325  { { STATE_WindowStart }, 'm' }
2326};
2327
2328static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2329  { { 6 /* art */ }, 'o' },
2330  { { 4 /* ars */ }, 'i' }
2331};
2332
2333static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2334  { { STATE_WindowBase }, 'i' },
2335  { { STATE_WindowStart }, 'i' }
2336};
2337
2338static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2339  { { 2 /* simm4 */ }, 'i' }
2340};
2341
2342static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2343  { { STATE_PSEXCM }, 'i' },
2344  { { STATE_PSRING }, 'i' },
2345  { { STATE_WindowBase }, 'm' }
2346};
2347
2348static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2349  { { 5 /* *ars_invisible */ }, 'i' }
2350};
2351
2352static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2353  { { STATE_WindowBase }, 'm' },
2354  { { STATE_WindowStart }, 'm' },
2355  { { STATE_PSEXCM }, 'i' },
2356  { { STATE_PSWOE }, 'i' }
2357};
2358
2359static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2360  { { STATE_EPC1 }, 'i' },
2361  { { STATE_PSEXCM }, 'm' },
2362  { { STATE_PSRING }, 'i' },
2363  { { STATE_WindowBase }, 'm' },
2364  { { STATE_WindowStart }, 'm' },
2365  { { STATE_PSOWB }, 'i' }
2366};
2367
2368static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2369  { { 6 /* art */ }, 'o' },
2370  { { 4 /* ars */ }, 'i' },
2371  { { 12 /* immrx4 */ }, 'i' }
2372};
2373
2374static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2375  { { STATE_PSEXCM }, 'i' },
2376  { { STATE_PSRING }, 'i' }
2377};
2378
2379static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2380  { { 6 /* art */ }, 'i' },
2381  { { 4 /* ars */ }, 'i' },
2382  { { 12 /* immrx4 */ }, 'i' }
2383};
2384
2385static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2386  { { STATE_PSEXCM }, 'i' },
2387  { { STATE_PSRING }, 'i' }
2388};
2389
2390static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2391  { { 6 /* art */ }, 'o' }
2392};
2393
2394static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2395  { { STATE_PSEXCM }, 'i' },
2396  { { STATE_PSRING }, 'i' },
2397  { { STATE_WindowBase }, 'i' }
2398};
2399
2400static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2401  { { 6 /* art */ }, 'i' }
2402};
2403
2404static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2405  { { STATE_PSEXCM }, 'i' },
2406  { { STATE_PSRING }, 'i' },
2407  { { STATE_WindowBase }, 'o' }
2408};
2409
2410static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2411  { { 6 /* art */ }, 'm' }
2412};
2413
2414static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2415  { { STATE_PSEXCM }, 'i' },
2416  { { STATE_PSRING }, 'i' },
2417  { { STATE_WindowBase }, 'm' }
2418};
2419
2420static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2421  { { 6 /* art */ }, 'o' }
2422};
2423
2424static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2425  { { STATE_PSEXCM }, 'i' },
2426  { { STATE_PSRING }, 'i' },
2427  { { STATE_WindowStart }, 'i' }
2428};
2429
2430static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2431  { { 6 /* art */ }, 'i' }
2432};
2433
2434static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2435  { { STATE_PSEXCM }, 'i' },
2436  { { STATE_PSRING }, 'i' },
2437  { { STATE_WindowStart }, 'o' }
2438};
2439
2440static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2441  { { 6 /* art */ }, 'm' }
2442};
2443
2444static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2445  { { STATE_PSEXCM }, 'i' },
2446  { { STATE_PSRING }, 'i' },
2447  { { STATE_WindowStart }, 'm' }
2448};
2449
2450static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2451  { { 3 /* arr */ }, 'o' },
2452  { { 4 /* ars */ }, 'i' },
2453  { { 6 /* art */ }, 'i' }
2454};
2455
2456static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2457  { { 3 /* arr */ }, 'o' },
2458  { { 4 /* ars */ }, 'i' },
2459  { { 16 /* ai4const */ }, 'i' }
2460};
2461
2462static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2463  { { 4 /* ars */ }, 'i' },
2464  { { 15 /* uimm6 */ }, 'i' }
2465};
2466
2467static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2468  { { 6 /* art */ }, 'o' },
2469  { { 4 /* ars */ }, 'i' },
2470  { { 13 /* lsi4x4 */ }, 'i' }
2471};
2472
2473static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2474  { { 6 /* art */ }, 'o' },
2475  { { 4 /* ars */ }, 'i' }
2476};
2477
2478static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2479  { { 4 /* ars */ }, 'o' },
2480  { { 14 /* simm7 */ }, 'i' }
2481};
2482
2483static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2484  { { 5 /* *ars_invisible */ }, 'i' }
2485};
2486
2487static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2488  { { 6 /* art */ }, 'i' },
2489  { { 4 /* ars */ }, 'i' },
2490  { { 13 /* lsi4x4 */ }, 'i' }
2491};
2492
2493static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2494  { { 6 /* art */ }, 'o' },
2495  { { 4 /* ars */ }, 'i' },
2496  { { 23 /* simm8 */ }, 'i' }
2497};
2498
2499static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2500  { { 6 /* art */ }, 'o' },
2501  { { 4 /* ars */ }, 'i' },
2502  { { 24 /* simm8x256 */ }, 'i' }
2503};
2504
2505static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2506  { { 3 /* arr */ }, 'o' },
2507  { { 4 /* ars */ }, 'i' },
2508  { { 6 /* art */ }, 'i' }
2509};
2510
2511static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2512  { { 3 /* arr */ }, 'o' },
2513  { { 4 /* ars */ }, 'i' },
2514  { { 6 /* art */ }, 'i' }
2515};
2516
2517static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2518  { { 4 /* ars */ }, 'i' },
2519  { { 17 /* b4const */ }, 'i' },
2520  { { 28 /* label8 */ }, 'i' }
2521};
2522
2523static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2524  { { 4 /* ars */ }, 'i' },
2525  { { 37 /* bbi */ }, 'i' },
2526  { { 28 /* label8 */ }, 'i' }
2527};
2528
2529static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2530  { { 4 /* ars */ }, 'i' },
2531  { { 18 /* b4constu */ }, 'i' },
2532  { { 28 /* label8 */ }, 'i' }
2533};
2534
2535static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2536  { { 4 /* ars */ }, 'i' },
2537  { { 6 /* art */ }, 'i' },
2538  { { 28 /* label8 */ }, 'i' }
2539};
2540
2541static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2542  { { 4 /* ars */ }, 'i' },
2543  { { 30 /* label12 */ }, 'i' }
2544};
2545
2546static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2547  { { 0 /* soffsetx4 */ }, 'i' },
2548  { { 7 /* ar0 */ }, 'o' }
2549};
2550
2551static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2552  { { 4 /* ars */ }, 'i' },
2553  { { 7 /* ar0 */ }, 'o' }
2554};
2555
2556static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2557  { { 3 /* arr */ }, 'o' },
2558  { { 6 /* art */ }, 'i' },
2559  { { 52 /* sae */ }, 'i' },
2560  { { 27 /* op2p1 */ }, 'i' }
2561};
2562
2563static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
2564  { { 31 /* soffset */ }, 'i' }
2565};
2566
2567static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
2568  { { 4 /* ars */ }, 'i' }
2569};
2570
2571static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
2572  { { 6 /* art */ }, 'o' },
2573  { { 4 /* ars */ }, 'i' },
2574  { { 20 /* uimm8x2 */ }, 'i' }
2575};
2576
2577static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
2578  { { 6 /* art */ }, 'o' },
2579  { { 4 /* ars */ }, 'i' },
2580  { { 20 /* uimm8x2 */ }, 'i' }
2581};
2582
2583static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
2584  { { 6 /* art */ }, 'o' },
2585  { { 4 /* ars */ }, 'i' },
2586  { { 21 /* uimm8x4 */ }, 'i' }
2587};
2588
2589static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
2590  { { 6 /* art */ }, 'o' },
2591  { { 32 /* uimm16x4 */ }, 'i' }
2592};
2593
2594static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2595  { { STATE_LITBADDR }, 'i' },
2596  { { STATE_LITBEN }, 'i' }
2597};
2598
2599static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
2600  { { 6 /* art */ }, 'o' },
2601  { { 4 /* ars */ }, 'i' },
2602  { { 19 /* uimm8 */ }, 'i' }
2603};
2604
2605static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
2606  { { 4 /* ars */ }, 'i' },
2607  { { 29 /* ulabel8 */ }, 'i' }
2608};
2609
2610static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
2611  { { STATE_LBEG }, 'o' },
2612  { { STATE_LEND }, 'o' },
2613  { { STATE_LCOUNT }, 'o' }
2614};
2615
2616static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
2617  { { 4 /* ars */ }, 'i' },
2618  { { 29 /* ulabel8 */ }, 'i' }
2619};
2620
2621static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
2622  { { STATE_LBEG }, 'o' },
2623  { { STATE_LEND }, 'o' },
2624  { { STATE_LCOUNT }, 'o' }
2625};
2626
2627static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
2628  { { 6 /* art */ }, 'o' },
2629  { { 25 /* simm12b */ }, 'i' }
2630};
2631
2632static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
2633  { { 3 /* arr */ }, 'm' },
2634  { { 4 /* ars */ }, 'i' },
2635  { { 6 /* art */ }, 'i' }
2636};
2637
2638static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
2639  { { 3 /* arr */ }, 'o' },
2640  { { 6 /* art */ }, 'i' }
2641};
2642
2643static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
2644  { { 5 /* *ars_invisible */ }, 'i' }
2645};
2646
2647static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
2648  { { 6 /* art */ }, 'i' },
2649  { { 4 /* ars */ }, 'i' },
2650  { { 20 /* uimm8x2 */ }, 'i' }
2651};
2652
2653static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
2654  { { 6 /* art */ }, 'i' },
2655  { { 4 /* ars */ }, 'i' },
2656  { { 21 /* uimm8x4 */ }, 'i' }
2657};
2658
2659static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
2660  { { 6 /* art */ }, 'i' },
2661  { { 4 /* ars */ }, 'i' },
2662  { { 19 /* uimm8 */ }, 'i' }
2663};
2664
2665static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
2666  { { 4 /* ars */ }, 'i' }
2667};
2668
2669static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
2670  { { STATE_SAR }, 'o' }
2671};
2672
2673static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
2674  { { 56 /* sas */ }, 'i' }
2675};
2676
2677static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
2678  { { STATE_SAR }, 'o' }
2679};
2680
2681static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
2682  { { 3 /* arr */ }, 'o' },
2683  { { 4 /* ars */ }, 'i' }
2684};
2685
2686static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
2687  { { STATE_SAR }, 'i' }
2688};
2689
2690static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
2691  { { 3 /* arr */ }, 'o' },
2692  { { 4 /* ars */ }, 'i' },
2693  { { 6 /* art */ }, 'i' }
2694};
2695
2696static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
2697  { { STATE_SAR }, 'i' }
2698};
2699
2700static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
2701  { { 3 /* arr */ }, 'o' },
2702  { { 6 /* art */ }, 'i' }
2703};
2704
2705static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
2706  { { STATE_SAR }, 'i' }
2707};
2708
2709static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
2710  { { 3 /* arr */ }, 'o' },
2711  { { 4 /* ars */ }, 'i' },
2712  { { 26 /* msalp32 */ }, 'i' }
2713};
2714
2715static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
2716  { { 3 /* arr */ }, 'o' },
2717  { { 6 /* art */ }, 'i' },
2718  { { 54 /* sargt */ }, 'i' }
2719};
2720
2721static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
2722  { { 3 /* arr */ }, 'o' },
2723  { { 6 /* art */ }, 'i' },
2724  { { 40 /* s */ }, 'i' }
2725};
2726
2727static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
2728  { { STATE_XTSYNC }, 'i' }
2729};
2730
2731static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
2732  { { 6 /* art */ }, 'o' },
2733  { { 40 /* s */ }, 'i' }
2734};
2735
2736static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
2737  { { STATE_PSWOE }, 'i' },
2738  { { STATE_PSCALLINC }, 'i' },
2739  { { STATE_PSOWB }, 'i' },
2740  { { STATE_PSRING }, 'i' },
2741  { { STATE_PSUM }, 'i' },
2742  { { STATE_PSEXCM }, 'i' },
2743  { { STATE_PSINTLEVEL }, 'm' }
2744};
2745
2746static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
2747  { { 6 /* art */ }, 'o' }
2748};
2749
2750static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
2751  { { STATE_LEND }, 'i' }
2752};
2753
2754static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
2755  { { 6 /* art */ }, 'i' }
2756};
2757
2758static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
2759  { { STATE_LEND }, 'o' }
2760};
2761
2762static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
2763  { { 6 /* art */ }, 'm' }
2764};
2765
2766static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
2767  { { STATE_LEND }, 'm' }
2768};
2769
2770static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
2771  { { 6 /* art */ }, 'o' }
2772};
2773
2774static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
2775  { { STATE_LCOUNT }, 'i' }
2776};
2777
2778static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
2779  { { 6 /* art */ }, 'i' }
2780};
2781
2782static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
2783  { { STATE_XTSYNC }, 'o' },
2784  { { STATE_LCOUNT }, 'o' }
2785};
2786
2787static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
2788  { { 6 /* art */ }, 'm' }
2789};
2790
2791static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
2792  { { STATE_XTSYNC }, 'o' },
2793  { { STATE_LCOUNT }, 'm' }
2794};
2795
2796static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
2797  { { 6 /* art */ }, 'o' }
2798};
2799
2800static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
2801  { { STATE_LBEG }, 'i' }
2802};
2803
2804static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
2805  { { 6 /* art */ }, 'i' }
2806};
2807
2808static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
2809  { { STATE_LBEG }, 'o' }
2810};
2811
2812static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
2813  { { 6 /* art */ }, 'm' }
2814};
2815
2816static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
2817  { { STATE_LBEG }, 'm' }
2818};
2819
2820static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
2821  { { 6 /* art */ }, 'o' }
2822};
2823
2824static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
2825  { { STATE_SAR }, 'i' }
2826};
2827
2828static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
2829  { { 6 /* art */ }, 'i' }
2830};
2831
2832static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
2833  { { STATE_SAR }, 'o' },
2834  { { STATE_XTSYNC }, 'o' }
2835};
2836
2837static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
2838  { { 6 /* art */ }, 'm' }
2839};
2840
2841static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
2842  { { STATE_SAR }, 'm' }
2843};
2844
2845static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
2846  { { 6 /* art */ }, 'o' }
2847};
2848
2849static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
2850  { { STATE_LITBADDR }, 'i' },
2851  { { STATE_LITBEN }, 'i' }
2852};
2853
2854static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
2855  { { 6 /* art */ }, 'i' }
2856};
2857
2858static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
2859  { { STATE_LITBADDR }, 'o' },
2860  { { STATE_LITBEN }, 'o' }
2861};
2862
2863static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
2864  { { 6 /* art */ }, 'm' }
2865};
2866
2867static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
2868  { { STATE_LITBADDR }, 'm' },
2869  { { STATE_LITBEN }, 'm' }
2870};
2871
2872static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
2873  { { 6 /* art */ }, 'o' }
2874};
2875
2876static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
2877  { { STATE_PSEXCM }, 'i' },
2878  { { STATE_PSRING }, 'i' }
2879};
2880
2881static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
2882  { { 6 /* art */ }, 'o' }
2883};
2884
2885static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
2886  { { STATE_PSEXCM }, 'i' },
2887  { { STATE_PSRING }, 'i' }
2888};
2889
2890static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
2891  { { 6 /* art */ }, 'o' }
2892};
2893
2894static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
2895  { { STATE_PSWOE }, 'i' },
2896  { { STATE_PSCALLINC }, 'i' },
2897  { { STATE_PSOWB }, 'i' },
2898  { { STATE_PSRING }, 'i' },
2899  { { STATE_PSUM }, 'i' },
2900  { { STATE_PSEXCM }, 'i' },
2901  { { STATE_PSINTLEVEL }, 'i' }
2902};
2903
2904static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
2905  { { 6 /* art */ }, 'i' }
2906};
2907
2908static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
2909  { { STATE_PSWOE }, 'o' },
2910  { { STATE_PSCALLINC }, 'o' },
2911  { { STATE_PSOWB }, 'o' },
2912  { { STATE_PSRING }, 'm' },
2913  { { STATE_PSUM }, 'o' },
2914  { { STATE_PSEXCM }, 'm' },
2915  { { STATE_PSINTLEVEL }, 'o' }
2916};
2917
2918static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
2919  { { 6 /* art */ }, 'm' }
2920};
2921
2922static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
2923  { { STATE_PSWOE }, 'm' },
2924  { { STATE_PSCALLINC }, 'm' },
2925  { { STATE_PSOWB }, 'm' },
2926  { { STATE_PSRING }, 'm' },
2927  { { STATE_PSUM }, 'm' },
2928  { { STATE_PSEXCM }, 'm' },
2929  { { STATE_PSINTLEVEL }, 'm' }
2930};
2931
2932static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
2933  { { 6 /* art */ }, 'o' }
2934};
2935
2936static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
2937  { { STATE_PSEXCM }, 'i' },
2938  { { STATE_PSRING }, 'i' },
2939  { { STATE_EPC1 }, 'i' }
2940};
2941
2942static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
2943  { { 6 /* art */ }, 'i' }
2944};
2945
2946static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
2947  { { STATE_PSEXCM }, 'i' },
2948  { { STATE_PSRING }, 'i' },
2949  { { STATE_EPC1 }, 'o' }
2950};
2951
2952static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
2953  { { 6 /* art */ }, 'm' }
2954};
2955
2956static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
2957  { { STATE_PSEXCM }, 'i' },
2958  { { STATE_PSRING }, 'i' },
2959  { { STATE_EPC1 }, 'm' }
2960};
2961
2962static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
2963  { { 6 /* art */ }, 'o' }
2964};
2965
2966static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
2967  { { STATE_PSEXCM }, 'i' },
2968  { { STATE_PSRING }, 'i' },
2969  { { STATE_EXCSAVE1 }, 'i' }
2970};
2971
2972static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
2973  { { 6 /* art */ }, 'i' }
2974};
2975
2976static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
2977  { { STATE_PSEXCM }, 'i' },
2978  { { STATE_PSRING }, 'i' },
2979  { { STATE_EXCSAVE1 }, 'o' }
2980};
2981
2982static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
2983  { { 6 /* art */ }, 'm' }
2984};
2985
2986static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
2987  { { STATE_PSEXCM }, 'i' },
2988  { { STATE_PSRING }, 'i' },
2989  { { STATE_EXCSAVE1 }, 'm' }
2990};
2991
2992static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
2993  { { 6 /* art */ }, 'o' }
2994};
2995
2996static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
2997  { { STATE_PSEXCM }, 'i' },
2998  { { STATE_PSRING }, 'i' },
2999  { { STATE_EPC2 }, 'i' }
3000};
3001
3002static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3003  { { 6 /* art */ }, 'i' }
3004};
3005
3006static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3007  { { STATE_PSEXCM }, 'i' },
3008  { { STATE_PSRING }, 'i' },
3009  { { STATE_EPC2 }, 'o' }
3010};
3011
3012static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3013  { { 6 /* art */ }, 'm' }
3014};
3015
3016static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3017  { { STATE_PSEXCM }, 'i' },
3018  { { STATE_PSRING }, 'i' },
3019  { { STATE_EPC2 }, 'm' }
3020};
3021
3022static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3023  { { 6 /* art */ }, 'o' }
3024};
3025
3026static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3027  { { STATE_PSEXCM }, 'i' },
3028  { { STATE_PSRING }, 'i' },
3029  { { STATE_EXCSAVE2 }, 'i' }
3030};
3031
3032static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3033  { { 6 /* art */ }, 'i' }
3034};
3035
3036static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3037  { { STATE_PSEXCM }, 'i' },
3038  { { STATE_PSRING }, 'i' },
3039  { { STATE_EXCSAVE2 }, 'o' }
3040};
3041
3042static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3043  { { 6 /* art */ }, 'm' }
3044};
3045
3046static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3047  { { STATE_PSEXCM }, 'i' },
3048  { { STATE_PSRING }, 'i' },
3049  { { STATE_EXCSAVE2 }, 'm' }
3050};
3051
3052static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3053  { { 6 /* art */ }, 'o' }
3054};
3055
3056static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3057  { { STATE_PSEXCM }, 'i' },
3058  { { STATE_PSRING }, 'i' },
3059  { { STATE_EPC3 }, 'i' }
3060};
3061
3062static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3063  { { 6 /* art */ }, 'i' }
3064};
3065
3066static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3067  { { STATE_PSEXCM }, 'i' },
3068  { { STATE_PSRING }, 'i' },
3069  { { STATE_EPC3 }, 'o' }
3070};
3071
3072static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3073  { { 6 /* art */ }, 'm' }
3074};
3075
3076static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3077  { { STATE_PSEXCM }, 'i' },
3078  { { STATE_PSRING }, 'i' },
3079  { { STATE_EPC3 }, 'm' }
3080};
3081
3082static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3083  { { 6 /* art */ }, 'o' }
3084};
3085
3086static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3087  { { STATE_PSEXCM }, 'i' },
3088  { { STATE_PSRING }, 'i' },
3089  { { STATE_EXCSAVE3 }, 'i' }
3090};
3091
3092static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3093  { { 6 /* art */ }, 'i' }
3094};
3095
3096static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3097  { { STATE_PSEXCM }, 'i' },
3098  { { STATE_PSRING }, 'i' },
3099  { { STATE_EXCSAVE3 }, 'o' }
3100};
3101
3102static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3103  { { 6 /* art */ }, 'm' }
3104};
3105
3106static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3107  { { STATE_PSEXCM }, 'i' },
3108  { { STATE_PSRING }, 'i' },
3109  { { STATE_EXCSAVE3 }, 'm' }
3110};
3111
3112static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3113  { { 6 /* art */ }, 'o' }
3114};
3115
3116static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3117  { { STATE_PSEXCM }, 'i' },
3118  { { STATE_PSRING }, 'i' },
3119  { { STATE_EPC4 }, 'i' }
3120};
3121
3122static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3123  { { 6 /* art */ }, 'i' }
3124};
3125
3126static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3127  { { STATE_PSEXCM }, 'i' },
3128  { { STATE_PSRING }, 'i' },
3129  { { STATE_EPC4 }, 'o' }
3130};
3131
3132static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3133  { { 6 /* art */ }, 'm' }
3134};
3135
3136static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3137  { { STATE_PSEXCM }, 'i' },
3138  { { STATE_PSRING }, 'i' },
3139  { { STATE_EPC4 }, 'm' }
3140};
3141
3142static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3143  { { 6 /* art */ }, 'o' }
3144};
3145
3146static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3147  { { STATE_PSEXCM }, 'i' },
3148  { { STATE_PSRING }, 'i' },
3149  { { STATE_EXCSAVE4 }, 'i' }
3150};
3151
3152static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3153  { { 6 /* art */ }, 'i' }
3154};
3155
3156static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3157  { { STATE_PSEXCM }, 'i' },
3158  { { STATE_PSRING }, 'i' },
3159  { { STATE_EXCSAVE4 }, 'o' }
3160};
3161
3162static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3163  { { 6 /* art */ }, 'm' }
3164};
3165
3166static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3167  { { STATE_PSEXCM }, 'i' },
3168  { { STATE_PSRING }, 'i' },
3169  { { STATE_EXCSAVE4 }, 'm' }
3170};
3171
3172static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3173  { { 6 /* art */ }, 'o' }
3174};
3175
3176static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3177  { { STATE_PSEXCM }, 'i' },
3178  { { STATE_PSRING }, 'i' },
3179  { { STATE_EPS2 }, 'i' }
3180};
3181
3182static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3183  { { 6 /* art */ }, 'i' }
3184};
3185
3186static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3187  { { STATE_PSEXCM }, 'i' },
3188  { { STATE_PSRING }, 'i' },
3189  { { STATE_EPS2 }, 'o' }
3190};
3191
3192static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3193  { { 6 /* art */ }, 'm' }
3194};
3195
3196static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3197  { { STATE_PSEXCM }, 'i' },
3198  { { STATE_PSRING }, 'i' },
3199  { { STATE_EPS2 }, 'm' }
3200};
3201
3202static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3203  { { 6 /* art */ }, 'o' }
3204};
3205
3206static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3207  { { STATE_PSEXCM }, 'i' },
3208  { { STATE_PSRING }, 'i' },
3209  { { STATE_EPS3 }, 'i' }
3210};
3211
3212static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3213  { { 6 /* art */ }, 'i' }
3214};
3215
3216static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3217  { { STATE_PSEXCM }, 'i' },
3218  { { STATE_PSRING }, 'i' },
3219  { { STATE_EPS3 }, 'o' }
3220};
3221
3222static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3223  { { 6 /* art */ }, 'm' }
3224};
3225
3226static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3227  { { STATE_PSEXCM }, 'i' },
3228  { { STATE_PSRING }, 'i' },
3229  { { STATE_EPS3 }, 'm' }
3230};
3231
3232static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3233  { { 6 /* art */ }, 'o' }
3234};
3235
3236static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3237  { { STATE_PSEXCM }, 'i' },
3238  { { STATE_PSRING }, 'i' },
3239  { { STATE_EPS4 }, 'i' }
3240};
3241
3242static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3243  { { 6 /* art */ }, 'i' }
3244};
3245
3246static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3247  { { STATE_PSEXCM }, 'i' },
3248  { { STATE_PSRING }, 'i' },
3249  { { STATE_EPS4 }, 'o' }
3250};
3251
3252static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3253  { { 6 /* art */ }, 'm' }
3254};
3255
3256static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3257  { { STATE_PSEXCM }, 'i' },
3258  { { STATE_PSRING }, 'i' },
3259  { { STATE_EPS4 }, 'm' }
3260};
3261
3262static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3263  { { 6 /* art */ }, 'o' }
3264};
3265
3266static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3267  { { STATE_PSEXCM }, 'i' },
3268  { { STATE_PSRING }, 'i' },
3269  { { STATE_EXCVADDR }, 'i' }
3270};
3271
3272static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3273  { { 6 /* art */ }, 'i' }
3274};
3275
3276static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3277  { { STATE_PSEXCM }, 'i' },
3278  { { STATE_PSRING }, 'i' },
3279  { { STATE_EXCVADDR }, 'o' }
3280};
3281
3282static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3283  { { 6 /* art */ }, 'm' }
3284};
3285
3286static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3287  { { STATE_PSEXCM }, 'i' },
3288  { { STATE_PSRING }, 'i' },
3289  { { STATE_EXCVADDR }, 'm' }
3290};
3291
3292static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3293  { { 6 /* art */ }, 'o' }
3294};
3295
3296static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3297  { { STATE_PSEXCM }, 'i' },
3298  { { STATE_PSRING }, 'i' },
3299  { { STATE_DEPC }, 'i' }
3300};
3301
3302static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3303  { { 6 /* art */ }, 'i' }
3304};
3305
3306static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3307  { { STATE_PSEXCM }, 'i' },
3308  { { STATE_PSRING }, 'i' },
3309  { { STATE_DEPC }, 'o' }
3310};
3311
3312static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3313  { { 6 /* art */ }, 'm' }
3314};
3315
3316static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3317  { { STATE_PSEXCM }, 'i' },
3318  { { STATE_PSRING }, 'i' },
3319  { { STATE_DEPC }, 'm' }
3320};
3321
3322static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3323  { { 6 /* art */ }, 'o' }
3324};
3325
3326static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3327  { { STATE_PSEXCM }, 'i' },
3328  { { STATE_PSRING }, 'i' },
3329  { { STATE_EXCCAUSE }, 'i' },
3330  { { STATE_XTSYNC }, 'i' }
3331};
3332
3333static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3334  { { 6 /* art */ }, 'i' }
3335};
3336
3337static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3338  { { STATE_PSEXCM }, 'i' },
3339  { { STATE_PSRING }, 'i' },
3340  { { STATE_EXCCAUSE }, 'o' }
3341};
3342
3343static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3344  { { 6 /* art */ }, 'm' }
3345};
3346
3347static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3348  { { STATE_PSEXCM }, 'i' },
3349  { { STATE_PSRING }, 'i' },
3350  { { STATE_EXCCAUSE }, 'm' }
3351};
3352
3353static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3354  { { 6 /* art */ }, 'o' }
3355};
3356
3357static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3358  { { STATE_PSEXCM }, 'i' },
3359  { { STATE_PSRING }, 'i' },
3360  { { STATE_MISC0 }, 'i' }
3361};
3362
3363static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3364  { { 6 /* art */ }, 'i' }
3365};
3366
3367static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3368  { { STATE_PSEXCM }, 'i' },
3369  { { STATE_PSRING }, 'i' },
3370  { { STATE_MISC0 }, 'o' }
3371};
3372
3373static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3374  { { 6 /* art */ }, 'm' }
3375};
3376
3377static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3378  { { STATE_PSEXCM }, 'i' },
3379  { { STATE_PSRING }, 'i' },
3380  { { STATE_MISC0 }, 'm' }
3381};
3382
3383static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3384  { { 6 /* art */ }, 'o' }
3385};
3386
3387static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3388  { { STATE_PSEXCM }, 'i' },
3389  { { STATE_PSRING }, 'i' },
3390  { { STATE_MISC1 }, 'i' }
3391};
3392
3393static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3394  { { 6 /* art */ }, 'i' }
3395};
3396
3397static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3398  { { STATE_PSEXCM }, 'i' },
3399  { { STATE_PSRING }, 'i' },
3400  { { STATE_MISC1 }, 'o' }
3401};
3402
3403static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3404  { { 6 /* art */ }, 'm' }
3405};
3406
3407static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3408  { { STATE_PSEXCM }, 'i' },
3409  { { STATE_PSRING }, 'i' },
3410  { { STATE_MISC1 }, 'm' }
3411};
3412
3413static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3414  { { 6 /* art */ }, 'o' }
3415};
3416
3417static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
3418  { { STATE_PSEXCM }, 'i' },
3419  { { STATE_PSRING }, 'i' }
3420};
3421
3422static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3423  { { 40 /* s */ }, 'i' }
3424};
3425
3426static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3427  { { STATE_PSWOE }, 'o' },
3428  { { STATE_PSCALLINC }, 'o' },
3429  { { STATE_PSOWB }, 'o' },
3430  { { STATE_PSRING }, 'm' },
3431  { { STATE_PSUM }, 'o' },
3432  { { STATE_PSEXCM }, 'm' },
3433  { { STATE_PSINTLEVEL }, 'o' },
3434  { { STATE_EPC1 }, 'i' },
3435  { { STATE_EPC2 }, 'i' },
3436  { { STATE_EPC3 }, 'i' },
3437  { { STATE_EPC4 }, 'i' },
3438  { { STATE_EPS2 }, 'i' },
3439  { { STATE_EPS3 }, 'i' },
3440  { { STATE_EPS4 }, 'i' },
3441  { { STATE_InOCDMode }, 'm' }
3442};
3443
3444static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3445  { { 40 /* s */ }, 'i' }
3446};
3447
3448static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3449  { { STATE_PSEXCM }, 'i' },
3450  { { STATE_PSRING }, 'i' },
3451  { { STATE_PSINTLEVEL }, 'o' }
3452};
3453
3454static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3455  { { 6 /* art */ }, 'o' }
3456};
3457
3458static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3459  { { STATE_PSEXCM }, 'i' },
3460  { { STATE_PSRING }, 'i' },
3461  { { STATE_INTERRUPT }, 'i' }
3462};
3463
3464static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3465  { { 6 /* art */ }, 'i' }
3466};
3467
3468static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3469  { { STATE_PSEXCM }, 'i' },
3470  { { STATE_PSRING }, 'i' },
3471  { { STATE_XTSYNC }, 'o' },
3472  { { STATE_INTERRUPT }, 'm' }
3473};
3474
3475static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
3476  { { 6 /* art */ }, 'i' }
3477};
3478
3479static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
3480  { { STATE_PSEXCM }, 'i' },
3481  { { STATE_PSRING }, 'i' },
3482  { { STATE_XTSYNC }, 'o' },
3483  { { STATE_INTERRUPT }, 'm' }
3484};
3485
3486static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
3487  { { 6 /* art */ }, 'o' }
3488};
3489
3490static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
3491  { { STATE_PSEXCM }, 'i' },
3492  { { STATE_PSRING }, 'i' },
3493  { { STATE_INTENABLE }, 'i' }
3494};
3495
3496static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
3497  { { 6 /* art */ }, 'i' }
3498};
3499
3500static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
3501  { { STATE_PSEXCM }, 'i' },
3502  { { STATE_PSRING }, 'i' },
3503  { { STATE_INTENABLE }, 'o' }
3504};
3505
3506static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
3507  { { 6 /* art */ }, 'm' }
3508};
3509
3510static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
3511  { { STATE_PSEXCM }, 'i' },
3512  { { STATE_PSRING }, 'i' },
3513  { { STATE_INTENABLE }, 'm' }
3514};
3515
3516static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
3517  { { 34 /* imms */ }, 'i' },
3518  { { 33 /* immt */ }, 'i' }
3519};
3520
3521static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
3522  { { STATE_PSEXCM }, 'i' },
3523  { { STATE_PSINTLEVEL }, 'i' }
3524};
3525
3526static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
3527  { { 34 /* imms */ }, 'i' }
3528};
3529
3530static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
3531  { { STATE_PSEXCM }, 'i' },
3532  { { STATE_PSINTLEVEL }, 'i' }
3533};
3534
3535static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
3536  { { 6 /* art */ }, 'o' }
3537};
3538
3539static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
3540  { { STATE_PSEXCM }, 'i' },
3541  { { STATE_PSRING }, 'i' },
3542  { { STATE_DBREAKA0 }, 'i' }
3543};
3544
3545static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
3546  { { 6 /* art */ }, 'i' }
3547};
3548
3549static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
3550  { { STATE_PSEXCM }, 'i' },
3551  { { STATE_PSRING }, 'i' },
3552  { { STATE_DBREAKA0 }, 'o' },
3553  { { STATE_XTSYNC }, 'o' }
3554};
3555
3556static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
3557  { { 6 /* art */ }, 'm' }
3558};
3559
3560static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
3561  { { STATE_PSEXCM }, 'i' },
3562  { { STATE_PSRING }, 'i' },
3563  { { STATE_DBREAKA0 }, 'm' },
3564  { { STATE_XTSYNC }, 'o' }
3565};
3566
3567static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
3568  { { 6 /* art */ }, 'o' }
3569};
3570
3571static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
3572  { { STATE_PSEXCM }, 'i' },
3573  { { STATE_PSRING }, 'i' },
3574  { { STATE_DBREAKC0 }, 'i' }
3575};
3576
3577static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
3578  { { 6 /* art */ }, 'i' }
3579};
3580
3581static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
3582  { { STATE_PSEXCM }, 'i' },
3583  { { STATE_PSRING }, 'i' },
3584  { { STATE_DBREAKC0 }, 'o' },
3585  { { STATE_XTSYNC }, 'o' }
3586};
3587
3588static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
3589  { { 6 /* art */ }, 'm' }
3590};
3591
3592static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
3593  { { STATE_PSEXCM }, 'i' },
3594  { { STATE_PSRING }, 'i' },
3595  { { STATE_DBREAKC0 }, 'm' },
3596  { { STATE_XTSYNC }, 'o' }
3597};
3598
3599static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
3600  { { 6 /* art */ }, 'o' }
3601};
3602
3603static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
3604  { { STATE_PSEXCM }, 'i' },
3605  { { STATE_PSRING }, 'i' },
3606  { { STATE_DBREAKA1 }, 'i' }
3607};
3608
3609static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
3610  { { 6 /* art */ }, 'i' }
3611};
3612
3613static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
3614  { { STATE_PSEXCM }, 'i' },
3615  { { STATE_PSRING }, 'i' },
3616  { { STATE_DBREAKA1 }, 'o' },
3617  { { STATE_XTSYNC }, 'o' }
3618};
3619
3620static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
3621  { { 6 /* art */ }, 'm' }
3622};
3623
3624static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
3625  { { STATE_PSEXCM }, 'i' },
3626  { { STATE_PSRING }, 'i' },
3627  { { STATE_DBREAKA1 }, 'm' },
3628  { { STATE_XTSYNC }, 'o' }
3629};
3630
3631static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
3632  { { 6 /* art */ }, 'o' }
3633};
3634
3635static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
3636  { { STATE_PSEXCM }, 'i' },
3637  { { STATE_PSRING }, 'i' },
3638  { { STATE_DBREAKC1 }, 'i' }
3639};
3640
3641static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
3642  { { 6 /* art */ }, 'i' }
3643};
3644
3645static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
3646  { { STATE_PSEXCM }, 'i' },
3647  { { STATE_PSRING }, 'i' },
3648  { { STATE_DBREAKC1 }, 'o' },
3649  { { STATE_XTSYNC }, 'o' }
3650};
3651
3652static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
3653  { { 6 /* art */ }, 'm' }
3654};
3655
3656static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
3657  { { STATE_PSEXCM }, 'i' },
3658  { { STATE_PSRING }, 'i' },
3659  { { STATE_DBREAKC1 }, 'm' },
3660  { { STATE_XTSYNC }, 'o' }
3661};
3662
3663static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
3664  { { 6 /* art */ }, 'o' }
3665};
3666
3667static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
3668  { { STATE_PSEXCM }, 'i' },
3669  { { STATE_PSRING }, 'i' },
3670  { { STATE_IBREAKA0 }, 'i' }
3671};
3672
3673static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
3674  { { 6 /* art */ }, 'i' }
3675};
3676
3677static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
3678  { { STATE_PSEXCM }, 'i' },
3679  { { STATE_PSRING }, 'i' },
3680  { { STATE_IBREAKA0 }, 'o' }
3681};
3682
3683static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
3684  { { 6 /* art */ }, 'm' }
3685};
3686
3687static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
3688  { { STATE_PSEXCM }, 'i' },
3689  { { STATE_PSRING }, 'i' },
3690  { { STATE_IBREAKA0 }, 'm' }
3691};
3692
3693static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
3694  { { 6 /* art */ }, 'o' }
3695};
3696
3697static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
3698  { { STATE_PSEXCM }, 'i' },
3699  { { STATE_PSRING }, 'i' },
3700  { { STATE_IBREAKA1 }, 'i' }
3701};
3702
3703static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
3704  { { 6 /* art */ }, 'i' }
3705};
3706
3707static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
3708  { { STATE_PSEXCM }, 'i' },
3709  { { STATE_PSRING }, 'i' },
3710  { { STATE_IBREAKA1 }, 'o' }
3711};
3712
3713static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
3714  { { 6 /* art */ }, 'm' }
3715};
3716
3717static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
3718  { { STATE_PSEXCM }, 'i' },
3719  { { STATE_PSRING }, 'i' },
3720  { { STATE_IBREAKA1 }, 'm' }
3721};
3722
3723static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
3724  { { 6 /* art */ }, 'o' }
3725};
3726
3727static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
3728  { { STATE_PSEXCM }, 'i' },
3729  { { STATE_PSRING }, 'i' },
3730  { { STATE_IBREAKENABLE }, 'i' }
3731};
3732
3733static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
3734  { { 6 /* art */ }, 'i' }
3735};
3736
3737static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
3738  { { STATE_PSEXCM }, 'i' },
3739  { { STATE_PSRING }, 'i' },
3740  { { STATE_IBREAKENABLE }, 'o' }
3741};
3742
3743static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
3744  { { 6 /* art */ }, 'm' }
3745};
3746
3747static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
3748  { { STATE_PSEXCM }, 'i' },
3749  { { STATE_PSRING }, 'i' },
3750  { { STATE_IBREAKENABLE }, 'm' }
3751};
3752
3753static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
3754  { { 6 /* art */ }, 'o' }
3755};
3756
3757static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
3758  { { STATE_PSEXCM }, 'i' },
3759  { { STATE_PSRING }, 'i' },
3760  { { STATE_DEBUGCAUSE }, 'i' },
3761  { { STATE_DBNUM }, 'i' }
3762};
3763
3764static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
3765  { { 6 /* art */ }, 'i' }
3766};
3767
3768static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
3769  { { STATE_PSEXCM }, 'i' },
3770  { { STATE_PSRING }, 'i' },
3771  { { STATE_DEBUGCAUSE }, 'o' },
3772  { { STATE_DBNUM }, 'o' }
3773};
3774
3775static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
3776  { { 6 /* art */ }, 'm' }
3777};
3778
3779static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
3780  { { STATE_PSEXCM }, 'i' },
3781  { { STATE_PSRING }, 'i' },
3782  { { STATE_DEBUGCAUSE }, 'm' },
3783  { { STATE_DBNUM }, 'm' }
3784};
3785
3786static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
3787  { { 6 /* art */ }, 'o' }
3788};
3789
3790static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
3791  { { STATE_PSEXCM }, 'i' },
3792  { { STATE_PSRING }, 'i' },
3793  { { STATE_ICOUNT }, 'i' }
3794};
3795
3796static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
3797  { { 6 /* art */ }, 'i' }
3798};
3799
3800static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
3801  { { STATE_PSEXCM }, 'i' },
3802  { { STATE_PSRING }, 'i' },
3803  { { STATE_XTSYNC }, 'o' },
3804  { { STATE_ICOUNT }, 'o' }
3805};
3806
3807static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
3808  { { 6 /* art */ }, 'm' }
3809};
3810
3811static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
3812  { { STATE_PSEXCM }, 'i' },
3813  { { STATE_PSRING }, 'i' },
3814  { { STATE_XTSYNC }, 'o' },
3815  { { STATE_ICOUNT }, 'm' }
3816};
3817
3818static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
3819  { { 6 /* art */ }, 'o' }
3820};
3821
3822static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
3823  { { STATE_PSEXCM }, 'i' },
3824  { { STATE_PSRING }, 'i' },
3825  { { STATE_ICOUNTLEVEL }, 'i' }
3826};
3827
3828static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
3829  { { 6 /* art */ }, 'i' }
3830};
3831
3832static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
3833  { { STATE_PSEXCM }, 'i' },
3834  { { STATE_PSRING }, 'i' },
3835  { { STATE_ICOUNTLEVEL }, 'o' }
3836};
3837
3838static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
3839  { { 6 /* art */ }, 'm' }
3840};
3841
3842static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
3843  { { STATE_PSEXCM }, 'i' },
3844  { { STATE_PSRING }, 'i' },
3845  { { STATE_ICOUNTLEVEL }, 'm' }
3846};
3847
3848static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
3849  { { 6 /* art */ }, 'o' }
3850};
3851
3852static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
3853  { { STATE_PSEXCM }, 'i' },
3854  { { STATE_PSRING }, 'i' },
3855  { { STATE_DDR }, 'i' }
3856};
3857
3858static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
3859  { { 6 /* art */ }, 'i' }
3860};
3861
3862static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
3863  { { STATE_PSEXCM }, 'i' },
3864  { { STATE_PSRING }, 'i' },
3865  { { STATE_XTSYNC }, 'o' },
3866  { { STATE_DDR }, 'o' }
3867};
3868
3869static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
3870  { { 6 /* art */ }, 'm' }
3871};
3872
3873static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
3874  { { STATE_PSEXCM }, 'i' },
3875  { { STATE_PSRING }, 'i' },
3876  { { STATE_XTSYNC }, 'o' },
3877  { { STATE_DDR }, 'm' }
3878};
3879
3880static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
3881  { { STATE_InOCDMode }, 'm' },
3882  { { STATE_EPC4 }, 'i' },
3883  { { STATE_PSWOE }, 'o' },
3884  { { STATE_PSCALLINC }, 'o' },
3885  { { STATE_PSOWB }, 'o' },
3886  { { STATE_PSRING }, 'o' },
3887  { { STATE_PSUM }, 'o' },
3888  { { STATE_PSEXCM }, 'o' },
3889  { { STATE_PSINTLEVEL }, 'o' },
3890  { { STATE_EPS4 }, 'i' }
3891};
3892
3893static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
3894  { { STATE_InOCDMode }, 'm' }
3895};
3896
3897static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
3898  { { 6 /* art */ }, 'o' }
3899};
3900
3901static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
3902  { { STATE_PSEXCM }, 'i' },
3903  { { STATE_PSRING }, 'i' },
3904  { { STATE_CCOUNT }, 'i' }
3905};
3906
3907static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
3908  { { 6 /* art */ }, 'i' }
3909};
3910
3911static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
3912  { { STATE_PSEXCM }, 'i' },
3913  { { STATE_PSRING }, 'i' },
3914  { { STATE_XTSYNC }, 'o' },
3915  { { STATE_CCOUNT }, 'o' }
3916};
3917
3918static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
3919  { { 6 /* art */ }, 'm' }
3920};
3921
3922static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
3923  { { STATE_PSEXCM }, 'i' },
3924  { { STATE_PSRING }, 'i' },
3925  { { STATE_XTSYNC }, 'o' },
3926  { { STATE_CCOUNT }, 'm' }
3927};
3928
3929static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
3930  { { 6 /* art */ }, 'o' }
3931};
3932
3933static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
3934  { { STATE_PSEXCM }, 'i' },
3935  { { STATE_PSRING }, 'i' },
3936  { { STATE_CCOMPARE0 }, 'i' }
3937};
3938
3939static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
3940  { { 6 /* art */ }, 'i' }
3941};
3942
3943static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
3944  { { STATE_PSEXCM }, 'i' },
3945  { { STATE_PSRING }, 'i' },
3946  { { STATE_CCOMPARE0 }, 'o' },
3947  { { STATE_INTERRUPT }, 'm' }
3948};
3949
3950static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
3951  { { 6 /* art */ }, 'm' }
3952};
3953
3954static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
3955  { { STATE_PSEXCM }, 'i' },
3956  { { STATE_PSRING }, 'i' },
3957  { { STATE_CCOMPARE0 }, 'm' },
3958  { { STATE_INTERRUPT }, 'm' }
3959};
3960
3961static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
3962  { { 6 /* art */ }, 'o' }
3963};
3964
3965static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
3966  { { STATE_PSEXCM }, 'i' },
3967  { { STATE_PSRING }, 'i' },
3968  { { STATE_CCOMPARE1 }, 'i' }
3969};
3970
3971static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
3972  { { 6 /* art */ }, 'i' }
3973};
3974
3975static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
3976  { { STATE_PSEXCM }, 'i' },
3977  { { STATE_PSRING }, 'i' },
3978  { { STATE_CCOMPARE1 }, 'o' },
3979  { { STATE_INTERRUPT }, 'm' }
3980};
3981
3982static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
3983  { { 6 /* art */ }, 'm' }
3984};
3985
3986static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
3987  { { STATE_PSEXCM }, 'i' },
3988  { { STATE_PSRING }, 'i' },
3989  { { STATE_CCOMPARE1 }, 'm' },
3990  { { STATE_INTERRUPT }, 'm' }
3991};
3992
3993static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
3994  { { 6 /* art */ }, 'o' }
3995};
3996
3997static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
3998  { { STATE_PSEXCM }, 'i' },
3999  { { STATE_PSRING }, 'i' },
4000  { { STATE_CCOMPARE2 }, 'i' }
4001};
4002
4003static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4004  { { 6 /* art */ }, 'i' }
4005};
4006
4007static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4008  { { STATE_PSEXCM }, 'i' },
4009  { { STATE_PSRING }, 'i' },
4010  { { STATE_CCOMPARE2 }, 'o' },
4011  { { STATE_INTERRUPT }, 'm' }
4012};
4013
4014static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4015  { { 6 /* art */ }, 'm' }
4016};
4017
4018static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4019  { { STATE_PSEXCM }, 'i' },
4020  { { STATE_PSRING }, 'i' },
4021  { { STATE_CCOMPARE2 }, 'm' },
4022  { { STATE_INTERRUPT }, 'm' }
4023};
4024
4025static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
4026  { { 4 /* ars */ }, 'i' },
4027  { { 21 /* uimm8x4 */ }, 'i' }
4028};
4029
4030static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
4031  { { 4 /* ars */ }, 'i' },
4032  { { 21 /* uimm8x4 */ }, 'i' }
4033};
4034
4035static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
4036  { { STATE_PSEXCM }, 'i' },
4037  { { STATE_PSRING }, 'i' }
4038};
4039
4040static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
4041  { { 6 /* art */ }, 'o' },
4042  { { 4 /* ars */ }, 'i' }
4043};
4044
4045static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
4046  { { STATE_PSEXCM }, 'i' },
4047  { { STATE_PSRING }, 'i' }
4048};
4049
4050static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
4051  { { 6 /* art */ }, 'i' },
4052  { { 4 /* ars */ }, 'i' }
4053};
4054
4055static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
4056  { { STATE_PSEXCM }, 'i' },
4057  { { STATE_PSRING }, 'i' }
4058};
4059
4060static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
4061  { { 4 /* ars */ }, 'i' },
4062  { { 21 /* uimm8x4 */ }, 'i' }
4063};
4064
4065static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
4066  { { 4 /* ars */ }, 'i' },
4067  { { 22 /* uimm4x16 */ }, 'i' }
4068};
4069
4070static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
4071  { { STATE_PSEXCM }, 'i' },
4072  { { STATE_PSRING }, 'i' }
4073};
4074
4075static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
4076  { { 4 /* ars */ }, 'i' },
4077  { { 21 /* uimm8x4 */ }, 'i' }
4078};
4079
4080static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
4081  { { STATE_PSEXCM }, 'i' },
4082  { { STATE_PSRING }, 'i' }
4083};
4084
4085static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
4086  { { 4 /* ars */ }, 'i' },
4087  { { 21 /* uimm8x4 */ }, 'i' }
4088};
4089
4090static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
4091  { { 6 /* art */ }, 'i' },
4092  { { 4 /* ars */ }, 'i' }
4093};
4094
4095static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
4096  { { STATE_PSEXCM }, 'i' },
4097  { { STATE_PSRING }, 'i' }
4098};
4099
4100static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
4101  { { 6 /* art */ }, 'o' },
4102  { { 4 /* ars */ }, 'i' }
4103};
4104
4105static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
4106  { { STATE_PSEXCM }, 'i' },
4107  { { STATE_PSRING }, 'i' }
4108};
4109
4110static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
4111  { { 6 /* art */ }, 'i' }
4112};
4113
4114static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
4115  { { STATE_PSEXCM }, 'i' },
4116  { { STATE_PSRING }, 'i' },
4117  { { STATE_PTBASE }, 'o' },
4118  { { STATE_XTSYNC }, 'o' }
4119};
4120
4121static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
4122  { { 6 /* art */ }, 'o' }
4123};
4124
4125static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
4126  { { STATE_PSEXCM }, 'i' },
4127  { { STATE_PSRING }, 'i' },
4128  { { STATE_PTBASE }, 'i' },
4129  { { STATE_EXCVADDR }, 'i' }
4130};
4131
4132static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
4133  { { 6 /* art */ }, 'm' }
4134};
4135
4136static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
4137  { { STATE_PSEXCM }, 'i' },
4138  { { STATE_PSRING }, 'i' },
4139  { { STATE_PTBASE }, 'm' },
4140  { { STATE_EXCVADDR }, 'i' },
4141  { { STATE_XTSYNC }, 'o' }
4142};
4143
4144static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
4145  { { 6 /* art */ }, 'o' }
4146};
4147
4148static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
4149  { { STATE_PSEXCM }, 'i' },
4150  { { STATE_PSRING }, 'i' },
4151  { { STATE_ASID3 }, 'i' },
4152  { { STATE_ASID2 }, 'i' },
4153  { { STATE_ASID1 }, 'i' }
4154};
4155
4156static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
4157  { { 6 /* art */ }, 'i' }
4158};
4159
4160static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
4161  { { STATE_XTSYNC }, 'o' },
4162  { { STATE_PSEXCM }, 'i' },
4163  { { STATE_PSRING }, 'i' },
4164  { { STATE_ASID3 }, 'o' },
4165  { { STATE_ASID2 }, 'o' },
4166  { { STATE_ASID1 }, 'o' }
4167};
4168
4169static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
4170  { { 6 /* art */ }, 'm' }
4171};
4172
4173static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
4174  { { STATE_XTSYNC }, 'o' },
4175  { { STATE_PSEXCM }, 'i' },
4176  { { STATE_PSRING }, 'i' },
4177  { { STATE_ASID3 }, 'm' },
4178  { { STATE_ASID2 }, 'm' },
4179  { { STATE_ASID1 }, 'm' }
4180};
4181
4182static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
4183  { { 6 /* art */ }, 'o' }
4184};
4185
4186static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
4187  { { STATE_PSEXCM }, 'i' },
4188  { { STATE_PSRING }, 'i' },
4189  { { STATE_INSTPGSZID4 }, 'i' }
4190};
4191
4192static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
4193  { { 6 /* art */ }, 'i' }
4194};
4195
4196static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
4197  { { STATE_XTSYNC }, 'o' },
4198  { { STATE_PSEXCM }, 'i' },
4199  { { STATE_PSRING }, 'i' },
4200  { { STATE_INSTPGSZID4 }, 'o' }
4201};
4202
4203static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
4204  { { 6 /* art */ }, 'm' }
4205};
4206
4207static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
4208  { { STATE_XTSYNC }, 'o' },
4209  { { STATE_PSEXCM }, 'i' },
4210  { { STATE_PSRING }, 'i' },
4211  { { STATE_INSTPGSZID4 }, 'm' }
4212};
4213
4214static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
4215  { { 6 /* art */ }, 'o' }
4216};
4217
4218static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
4219  { { STATE_PSEXCM }, 'i' },
4220  { { STATE_PSRING }, 'i' },
4221  { { STATE_DATAPGSZID4 }, 'i' }
4222};
4223
4224static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
4225  { { 6 /* art */ }, 'i' }
4226};
4227
4228static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
4229  { { STATE_XTSYNC }, 'o' },
4230  { { STATE_PSEXCM }, 'i' },
4231  { { STATE_PSRING }, 'i' },
4232  { { STATE_DATAPGSZID4 }, 'o' }
4233};
4234
4235static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
4236  { { 6 /* art */ }, 'm' }
4237};
4238
4239static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
4240  { { STATE_XTSYNC }, 'o' },
4241  { { STATE_PSEXCM }, 'i' },
4242  { { STATE_PSRING }, 'i' },
4243  { { STATE_DATAPGSZID4 }, 'm' }
4244};
4245
4246static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4247  { { 4 /* ars */ }, 'i' }
4248};
4249
4250static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4251  { { STATE_PSEXCM }, 'i' },
4252  { { STATE_PSRING }, 'i' },
4253  { { STATE_XTSYNC }, 'o' }
4254};
4255
4256static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4257  { { 6 /* art */ }, 'o' },
4258  { { 4 /* ars */ }, 'i' }
4259};
4260
4261static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
4262  { { STATE_PSEXCM }, 'i' },
4263  { { STATE_PSRING }, 'i' }
4264};
4265
4266static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4267  { { 6 /* art */ }, 'i' },
4268  { { 4 /* ars */ }, 'i' }
4269};
4270
4271static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4272  { { STATE_PSEXCM }, 'i' },
4273  { { STATE_PSRING }, 'i' },
4274  { { STATE_XTSYNC }, 'o' }
4275};
4276
4277static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4278  { { 4 /* ars */ }, 'i' }
4279};
4280
4281static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
4282  { { STATE_PSEXCM }, 'i' },
4283  { { STATE_PSRING }, 'i' }
4284};
4285
4286static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4287  { { 6 /* art */ }, 'o' },
4288  { { 4 /* ars */ }, 'i' }
4289};
4290
4291static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
4292  { { STATE_PSEXCM }, 'i' },
4293  { { STATE_PSRING }, 'i' }
4294};
4295
4296static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4297  { { 6 /* art */ }, 'i' },
4298  { { 4 /* ars */ }, 'i' }
4299};
4300
4301static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
4302  { { STATE_PSEXCM }, 'i' },
4303  { { STATE_PSRING }, 'i' }
4304};
4305
4306static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
4307  { { STATE_PTBASE }, 'i' },
4308  { { STATE_EXCVADDR }, 'i' }
4309};
4310
4311static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
4312  { { STATE_EXCVADDR }, 'i' }
4313};
4314
4315static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
4316  { { STATE_EXCVADDR }, 'i' }
4317};
4318
4319static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4320  { { 6 /* art */ }, 'o' },
4321  { { 4 /* ars */ }, 'i' }
4322};
4323
4324static xtensa_iclass_internal iclasses[] = {
4325  { 0, 0 /* xt_iclass_excw */,
4326    0, 0, 0, 0 },
4327  { 0, 0 /* xt_iclass_rfe */,
4328    3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4329  { 0, 0 /* xt_iclass_rfde */,
4330    3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4331  { 0, 0 /* xt_iclass_syscall */,
4332    0, 0, 0, 0 },
4333  { 0, 0 /* xt_iclass_simcall */,
4334    0, 0, 0, 0 },
4335  { 2, Iclass_xt_iclass_call12_args,
4336    1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
4337  { 2, Iclass_xt_iclass_call8_args,
4338    1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
4339  { 2, Iclass_xt_iclass_call4_args,
4340    1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
4341  { 2, Iclass_xt_iclass_callx12_args,
4342    1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
4343  { 2, Iclass_xt_iclass_callx8_args,
4344    1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
4345  { 2, Iclass_xt_iclass_callx4_args,
4346    1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
4347  { 3, Iclass_xt_iclass_entry_args,
4348    5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
4349  { 2, Iclass_xt_iclass_movsp_args,
4350    2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
4351  { 1, Iclass_xt_iclass_rotw_args,
4352    3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
4353  { 1, Iclass_xt_iclass_retw_args,
4354    4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
4355  { 0, 0 /* xt_iclass_rfwou */,
4356    6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
4357  { 3, Iclass_xt_iclass_l32e_args,
4358    2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
4359  { 3, Iclass_xt_iclass_s32e_args,
4360    2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
4361  { 1, Iclass_xt_iclass_rsr_windowbase_args,
4362    3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
4363  { 1, Iclass_xt_iclass_wsr_windowbase_args,
4364    3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
4365  { 1, Iclass_xt_iclass_xsr_windowbase_args,
4366    3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
4367  { 1, Iclass_xt_iclass_rsr_windowstart_args,
4368    3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
4369  { 1, Iclass_xt_iclass_wsr_windowstart_args,
4370    3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
4371  { 1, Iclass_xt_iclass_xsr_windowstart_args,
4372    3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
4373  { 3, Iclass_xt_iclass_add_n_args,
4374    0, 0, 0, 0 },
4375  { 3, Iclass_xt_iclass_addi_n_args,
4376    0, 0, 0, 0 },
4377  { 2, Iclass_xt_iclass_bz6_args,
4378    0, 0, 0, 0 },
4379  { 0, 0 /* xt_iclass_ill_n */,
4380    0, 0, 0, 0 },
4381  { 3, Iclass_xt_iclass_loadi4_args,
4382    0, 0, 0, 0 },
4383  { 2, Iclass_xt_iclass_mov_n_args,
4384    0, 0, 0, 0 },
4385  { 2, Iclass_xt_iclass_movi_n_args,
4386    0, 0, 0, 0 },
4387  { 0, 0 /* xt_iclass_nopn */,
4388    0, 0, 0, 0 },
4389  { 1, Iclass_xt_iclass_retn_args,
4390    0, 0, 0, 0 },
4391  { 3, Iclass_xt_iclass_storei4_args,
4392    0, 0, 0, 0 },
4393  { 3, Iclass_xt_iclass_addi_args,
4394    0, 0, 0, 0 },
4395  { 3, Iclass_xt_iclass_addmi_args,
4396    0, 0, 0, 0 },
4397  { 3, Iclass_xt_iclass_addsub_args,
4398    0, 0, 0, 0 },
4399  { 3, Iclass_xt_iclass_bit_args,
4400    0, 0, 0, 0 },
4401  { 3, Iclass_xt_iclass_bsi8_args,
4402    0, 0, 0, 0 },
4403  { 3, Iclass_xt_iclass_bsi8b_args,
4404    0, 0, 0, 0 },
4405  { 3, Iclass_xt_iclass_bsi8u_args,
4406    0, 0, 0, 0 },
4407  { 3, Iclass_xt_iclass_bst8_args,
4408    0, 0, 0, 0 },
4409  { 2, Iclass_xt_iclass_bsz12_args,
4410    0, 0, 0, 0 },
4411  { 2, Iclass_xt_iclass_call0_args,
4412    0, 0, 0, 0 },
4413  { 2, Iclass_xt_iclass_callx0_args,
4414    0, 0, 0, 0 },
4415  { 4, Iclass_xt_iclass_exti_args,
4416    0, 0, 0, 0 },
4417  { 0, 0 /* xt_iclass_ill */,
4418    0, 0, 0, 0 },
4419  { 1, Iclass_xt_iclass_jump_args,
4420    0, 0, 0, 0 },
4421  { 1, Iclass_xt_iclass_jumpx_args,
4422    0, 0, 0, 0 },
4423  { 3, Iclass_xt_iclass_l16ui_args,
4424    0, 0, 0, 0 },
4425  { 3, Iclass_xt_iclass_l16si_args,
4426    0, 0, 0, 0 },
4427  { 3, Iclass_xt_iclass_l32i_args,
4428    0, 0, 0, 0 },
4429  { 2, Iclass_xt_iclass_l32r_args,
4430    2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
4431  { 3, Iclass_xt_iclass_l8i_args,
4432    0, 0, 0, 0 },
4433  { 2, Iclass_xt_iclass_loop_args,
4434    3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
4435  { 2, Iclass_xt_iclass_loopz_args,
4436    3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
4437  { 2, Iclass_xt_iclass_movi_args,
4438    0, 0, 0, 0 },
4439  { 3, Iclass_xt_iclass_movz_args,
4440    0, 0, 0, 0 },
4441  { 2, Iclass_xt_iclass_neg_args,
4442    0, 0, 0, 0 },
4443  { 0, 0 /* xt_iclass_nop */,
4444    0, 0, 0, 0 },
4445  { 1, Iclass_xt_iclass_return_args,
4446    0, 0, 0, 0 },
4447  { 3, Iclass_xt_iclass_s16i_args,
4448    0, 0, 0, 0 },
4449  { 3, Iclass_xt_iclass_s32i_args,
4450    0, 0, 0, 0 },
4451  { 3, Iclass_xt_iclass_s8i_args,
4452    0, 0, 0, 0 },
4453  { 1, Iclass_xt_iclass_sar_args,
4454    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
4455  { 1, Iclass_xt_iclass_sari_args,
4456    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
4457  { 2, Iclass_xt_iclass_shifts_args,
4458    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
4459  { 3, Iclass_xt_iclass_shiftst_args,
4460    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
4461  { 2, Iclass_xt_iclass_shiftt_args,
4462    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
4463  { 3, Iclass_xt_iclass_slli_args,
4464    0, 0, 0, 0 },
4465  { 3, Iclass_xt_iclass_srai_args,
4466    0, 0, 0, 0 },
4467  { 3, Iclass_xt_iclass_srli_args,
4468    0, 0, 0, 0 },
4469  { 0, 0 /* xt_iclass_memw */,
4470    0, 0, 0, 0 },
4471  { 0, 0 /* xt_iclass_extw */,
4472    0, 0, 0, 0 },
4473  { 0, 0 /* xt_iclass_isync */,
4474    0, 0, 0, 0 },
4475  { 0, 0 /* xt_iclass_sync */,
4476    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
4477  { 2, Iclass_xt_iclass_rsil_args,
4478    7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
4479  { 1, Iclass_xt_iclass_rsr_lend_args,
4480    1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
4481  { 1, Iclass_xt_iclass_wsr_lend_args,
4482    1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
4483  { 1, Iclass_xt_iclass_xsr_lend_args,
4484    1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
4485  { 1, Iclass_xt_iclass_rsr_lcount_args,
4486    1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
4487  { 1, Iclass_xt_iclass_wsr_lcount_args,
4488    2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
4489  { 1, Iclass_xt_iclass_xsr_lcount_args,
4490    2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
4491  { 1, Iclass_xt_iclass_rsr_lbeg_args,
4492    1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
4493  { 1, Iclass_xt_iclass_wsr_lbeg_args,
4494    1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
4495  { 1, Iclass_xt_iclass_xsr_lbeg_args,
4496    1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
4497  { 1, Iclass_xt_iclass_rsr_sar_args,
4498    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
4499  { 1, Iclass_xt_iclass_wsr_sar_args,
4500    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
4501  { 1, Iclass_xt_iclass_xsr_sar_args,
4502    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
4503  { 1, Iclass_xt_iclass_rsr_litbase_args,
4504    2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
4505  { 1, Iclass_xt_iclass_wsr_litbase_args,
4506    2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
4507  { 1, Iclass_xt_iclass_xsr_litbase_args,
4508    2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
4509  { 1, Iclass_xt_iclass_rsr_176_args,
4510    2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
4511  { 1, Iclass_xt_iclass_rsr_208_args,
4512    2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
4513  { 1, Iclass_xt_iclass_rsr_ps_args,
4514    7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
4515  { 1, Iclass_xt_iclass_wsr_ps_args,
4516    7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
4517  { 1, Iclass_xt_iclass_xsr_ps_args,
4518    7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
4519  { 1, Iclass_xt_iclass_rsr_epc1_args,
4520    3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
4521  { 1, Iclass_xt_iclass_wsr_epc1_args,
4522    3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
4523  { 1, Iclass_xt_iclass_xsr_epc1_args,
4524    3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
4525  { 1, Iclass_xt_iclass_rsr_excsave1_args,
4526    3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
4527  { 1, Iclass_xt_iclass_wsr_excsave1_args,
4528    3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
4529  { 1, Iclass_xt_iclass_xsr_excsave1_args,
4530    3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
4531  { 1, Iclass_xt_iclass_rsr_epc2_args,
4532    3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
4533  { 1, Iclass_xt_iclass_wsr_epc2_args,
4534    3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
4535  { 1, Iclass_xt_iclass_xsr_epc2_args,
4536    3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
4537  { 1, Iclass_xt_iclass_rsr_excsave2_args,
4538    3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
4539  { 1, Iclass_xt_iclass_wsr_excsave2_args,
4540    3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
4541  { 1, Iclass_xt_iclass_xsr_excsave2_args,
4542    3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
4543  { 1, Iclass_xt_iclass_rsr_epc3_args,
4544    3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
4545  { 1, Iclass_xt_iclass_wsr_epc3_args,
4546    3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
4547  { 1, Iclass_xt_iclass_xsr_epc3_args,
4548    3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
4549  { 1, Iclass_xt_iclass_rsr_excsave3_args,
4550    3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
4551  { 1, Iclass_xt_iclass_wsr_excsave3_args,
4552    3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
4553  { 1, Iclass_xt_iclass_xsr_excsave3_args,
4554    3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
4555  { 1, Iclass_xt_iclass_rsr_epc4_args,
4556    3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
4557  { 1, Iclass_xt_iclass_wsr_epc4_args,
4558    3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
4559  { 1, Iclass_xt_iclass_xsr_epc4_args,
4560    3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
4561  { 1, Iclass_xt_iclass_rsr_excsave4_args,
4562    3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
4563  { 1, Iclass_xt_iclass_wsr_excsave4_args,
4564    3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
4565  { 1, Iclass_xt_iclass_xsr_excsave4_args,
4566    3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
4567  { 1, Iclass_xt_iclass_rsr_eps2_args,
4568    3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
4569  { 1, Iclass_xt_iclass_wsr_eps2_args,
4570    3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
4571  { 1, Iclass_xt_iclass_xsr_eps2_args,
4572    3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
4573  { 1, Iclass_xt_iclass_rsr_eps3_args,
4574    3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
4575  { 1, Iclass_xt_iclass_wsr_eps3_args,
4576    3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
4577  { 1, Iclass_xt_iclass_xsr_eps3_args,
4578    3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
4579  { 1, Iclass_xt_iclass_rsr_eps4_args,
4580    3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
4581  { 1, Iclass_xt_iclass_wsr_eps4_args,
4582    3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
4583  { 1, Iclass_xt_iclass_xsr_eps4_args,
4584    3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
4585  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
4586    3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
4587  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
4588    3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
4589  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
4590    3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
4591  { 1, Iclass_xt_iclass_rsr_depc_args,
4592    3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
4593  { 1, Iclass_xt_iclass_wsr_depc_args,
4594    3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
4595  { 1, Iclass_xt_iclass_xsr_depc_args,
4596    3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
4597  { 1, Iclass_xt_iclass_rsr_exccause_args,
4598    4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
4599  { 1, Iclass_xt_iclass_wsr_exccause_args,
4600    3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
4601  { 1, Iclass_xt_iclass_xsr_exccause_args,
4602    3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
4603  { 1, Iclass_xt_iclass_rsr_misc0_args,
4604    3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
4605  { 1, Iclass_xt_iclass_wsr_misc0_args,
4606    3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
4607  { 1, Iclass_xt_iclass_xsr_misc0_args,
4608    3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
4609  { 1, Iclass_xt_iclass_rsr_misc1_args,
4610    3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
4611  { 1, Iclass_xt_iclass_wsr_misc1_args,
4612    3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
4613  { 1, Iclass_xt_iclass_xsr_misc1_args,
4614    3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
4615  { 1, Iclass_xt_iclass_rsr_prid_args,
4616    2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
4617  { 1, Iclass_xt_iclass_rfi_args,
4618    15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
4619  { 1, Iclass_xt_iclass_wait_args,
4620    3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
4621  { 1, Iclass_xt_iclass_rsr_interrupt_args,
4622    3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
4623  { 1, Iclass_xt_iclass_wsr_intset_args,
4624    4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
4625  { 1, Iclass_xt_iclass_wsr_intclear_args,
4626    4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
4627  { 1, Iclass_xt_iclass_rsr_intenable_args,
4628    3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
4629  { 1, Iclass_xt_iclass_wsr_intenable_args,
4630    3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
4631  { 1, Iclass_xt_iclass_xsr_intenable_args,
4632    3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
4633  { 2, Iclass_xt_iclass_break_args,
4634    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
4635  { 1, Iclass_xt_iclass_break_n_args,
4636    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
4637  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
4638    3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
4639  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
4640    4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
4641  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
4642    4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
4643  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
4644    3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
4645  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
4646    4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
4647  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
4648    4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
4649  { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
4650    3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
4651  { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
4652    4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
4653  { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
4654    4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
4655  { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
4656    3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
4657  { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
4658    4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
4659  { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
4660    4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
4661  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
4662    3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
4663  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
4664    3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
4665  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
4666    3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
4667  { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
4668    3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
4669  { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
4670    3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
4671  { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
4672    3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
4673  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
4674    3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
4675  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
4676    3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
4677  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
4678    3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
4679  { 1, Iclass_xt_iclass_rsr_debugcause_args,
4680    4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
4681  { 1, Iclass_xt_iclass_wsr_debugcause_args,
4682    4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
4683  { 1, Iclass_xt_iclass_xsr_debugcause_args,
4684    4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
4685  { 1, Iclass_xt_iclass_rsr_icount_args,
4686    3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
4687  { 1, Iclass_xt_iclass_wsr_icount_args,
4688    4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
4689  { 1, Iclass_xt_iclass_xsr_icount_args,
4690    4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
4691  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
4692    3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
4693  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
4694    3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
4695  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
4696    3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
4697  { 1, Iclass_xt_iclass_rsr_ddr_args,
4698    3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
4699  { 1, Iclass_xt_iclass_wsr_ddr_args,
4700    4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
4701  { 1, Iclass_xt_iclass_xsr_ddr_args,
4702    4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
4703  { 0, 0 /* xt_iclass_rfdo */,
4704    10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
4705  { 0, 0 /* xt_iclass_rfdd */,
4706    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
4707  { 1, Iclass_xt_iclass_rsr_ccount_args,
4708    3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
4709  { 1, Iclass_xt_iclass_wsr_ccount_args,
4710    4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
4711  { 1, Iclass_xt_iclass_xsr_ccount_args,
4712    4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
4713  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
4714    3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
4715  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
4716    4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
4717  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
4718    4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
4719  { 1, Iclass_xt_iclass_rsr_ccompare1_args,
4720    3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
4721  { 1, Iclass_xt_iclass_wsr_ccompare1_args,
4722    4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
4723  { 1, Iclass_xt_iclass_xsr_ccompare1_args,
4724    4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
4725  { 1, Iclass_xt_iclass_rsr_ccompare2_args,
4726    3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
4727  { 1, Iclass_xt_iclass_wsr_ccompare2_args,
4728    4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
4729  { 1, Iclass_xt_iclass_xsr_ccompare2_args,
4730    4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
4731  { 2, Iclass_xt_iclass_icache_args,
4732    0, 0, 0, 0 },
4733  { 2, Iclass_xt_iclass_icache_inv_args,
4734    2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
4735  { 2, Iclass_xt_iclass_licx_args,
4736    2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
4737  { 2, Iclass_xt_iclass_sicx_args,
4738    2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
4739  { 2, Iclass_xt_iclass_dcache_args,
4740    0, 0, 0, 0 },
4741  { 2, Iclass_xt_iclass_dcache_ind_args,
4742    2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
4743  { 2, Iclass_xt_iclass_dcache_inv_args,
4744    2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
4745  { 2, Iclass_xt_iclass_dpf_args,
4746    0, 0, 0, 0 },
4747  { 2, Iclass_xt_iclass_sdct_args,
4748    2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
4749  { 2, Iclass_xt_iclass_ldct_args,
4750    2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
4751  { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
4752    4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
4753  { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
4754    4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
4755  { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
4756    5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
4757  { 1, Iclass_xt_iclass_rsr_rasid_args,
4758    5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
4759  { 1, Iclass_xt_iclass_wsr_rasid_args,
4760    6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
4761  { 1, Iclass_xt_iclass_xsr_rasid_args,
4762    6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
4763  { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
4764    3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
4765  { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
4766    4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
4767  { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
4768    4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
4769  { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
4770    3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
4771  { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
4772    4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
4773  { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
4774    4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
4775  { 1, Iclass_xt_iclass_idtlb_args,
4776    3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
4777  { 2, Iclass_xt_iclass_rdtlb_args,
4778    2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
4779  { 2, Iclass_xt_iclass_wdtlb_args,
4780    3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
4781  { 1, Iclass_xt_iclass_iitlb_args,
4782    2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
4783  { 2, Iclass_xt_iclass_ritlb_args,
4784    2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
4785  { 2, Iclass_xt_iclass_witlb_args,
4786    2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
4787  { 0, 0 /* xt_iclass_ldpte */,
4788    2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
4789  { 0, 0 /* xt_iclass_hwwitlba */,
4790    1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
4791  { 0, 0 /* xt_iclass_hwwdtlba */,
4792    1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
4793  { 2, Iclass_xt_iclass_nsa_args,
4794    0, 0, 0, 0 }
4795};
4796
4797
4798/*  Opcode encodings.  */
4799
4800static void
4801Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4802{
4803  slotbuf[0] = 0x80200;
4804}
4805
4806static void
4807Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
4808{
4809  slotbuf[0] = 0x300;
4810}
4811
4812static void
4813Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
4814{
4815  slotbuf[0] = 0x2300;
4816}
4817
4818static void
4819Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
4820{
4821  slotbuf[0] = 0x500;
4822}
4823
4824static void
4825Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
4826{
4827  slotbuf[0] = 0x1500;
4828}
4829
4830static void
4831Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
4832{
4833  slotbuf[0] = 0x5c0000;
4834}
4835
4836static void
4837Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
4838{
4839  slotbuf[0] = 0x580000;
4840}
4841
4842static void
4843Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
4844{
4845  slotbuf[0] = 0x540000;
4846}
4847
4848static void
4849Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
4850{
4851  slotbuf[0] = 0xf0000;
4852}
4853
4854static void
4855Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
4856{
4857  slotbuf[0] = 0xb0000;
4858}
4859
4860static void
4861Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
4862{
4863  slotbuf[0] = 0x70000;
4864}
4865
4866static void
4867Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
4868{
4869  slotbuf[0] = 0x6c0000;
4870}
4871
4872static void
4873Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
4874{
4875  slotbuf[0] = 0x100;
4876}
4877
4878static void
4879Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4880{
4881  slotbuf[0] = 0x804;
4882}
4883
4884static void
4885Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4886{
4887  slotbuf[0] = 0x60000;
4888}
4889
4890static void
4891Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4892{
4893  slotbuf[0] = 0xd10f;
4894}
4895
4896static void
4897Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
4898{
4899  slotbuf[0] = 0x4300;
4900}
4901
4902static void
4903Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
4904{
4905  slotbuf[0] = 0x5300;
4906}
4907
4908static void
4909Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
4910{
4911  slotbuf[0] = 0x90;
4912}
4913
4914static void
4915Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
4916{
4917  slotbuf[0] = 0x94;
4918}
4919
4920static void
4921Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4922{
4923  slotbuf[0] = 0x4830;
4924}
4925
4926static void
4927Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4928{
4929  slotbuf[0] = 0x4831;
4930}
4931
4932static void
4933Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4934{
4935  slotbuf[0] = 0x4816;
4936}
4937
4938static void
4939Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4940{
4941  slotbuf[0] = 0x4930;
4942}
4943
4944static void
4945Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4946{
4947  slotbuf[0] = 0x4931;
4948}
4949
4950static void
4951Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4952{
4953  slotbuf[0] = 0x4916;
4954}
4955
4956static void
4957Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4958{
4959  slotbuf[0] = 0xa000;
4960}
4961
4962static void
4963Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4964{
4965  slotbuf[0] = 0xb000;
4966}
4967
4968static void
4969Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4970{
4971  slotbuf[0] = 0xc800;
4972}
4973
4974static void
4975Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4976{
4977  slotbuf[0] = 0xcc00;
4978}
4979
4980static void
4981Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4982{
4983  slotbuf[0] = 0xd60f;
4984}
4985
4986static void
4987Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4988{
4989  slotbuf[0] = 0x8000;
4990}
4991
4992static void
4993Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4994{
4995  slotbuf[0] = 0xd000;
4996}
4997
4998static void
4999Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5000{
5001  slotbuf[0] = 0xc000;
5002}
5003
5004static void
5005Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5006{
5007  slotbuf[0] = 0xd30f;
5008}
5009
5010static void
5011Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5012{
5013  slotbuf[0] = 0xd00f;
5014}
5015
5016static void
5017Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5018{
5019  slotbuf[0] = 0x9000;
5020}
5021
5022static void
5023Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5024{
5025  slotbuf[0] = 0x200c00;
5026}
5027
5028static void
5029Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5030{
5031  slotbuf[0] = 0x200d00;
5032}
5033
5034static void
5035Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
5036{
5037  slotbuf[0] = 0x8;
5038}
5039
5040static void
5041Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
5042{
5043  slotbuf[0] = 0xc;
5044}
5045
5046static void
5047Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5048{
5049  slotbuf[0] = 0x9;
5050}
5051
5052static void
5053Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5054{
5055  slotbuf[0] = 0xa;
5056}
5057
5058static void
5059Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5060{
5061  slotbuf[0] = 0xb;
5062}
5063
5064static void
5065Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5066{
5067  slotbuf[0] = 0xd;
5068}
5069
5070static void
5071Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5072{
5073  slotbuf[0] = 0xe;
5074}
5075
5076static void
5077Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5078{
5079  slotbuf[0] = 0xf;
5080}
5081
5082static void
5083Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
5084{
5085  slotbuf[0] = 0x1;
5086}
5087
5088static void
5089Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
5090{
5091  slotbuf[0] = 0x2;
5092}
5093
5094static void
5095Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
5096{
5097  slotbuf[0] = 0x3;
5098}
5099
5100static void
5101Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5102{
5103  slotbuf[0] = 0x680000;
5104}
5105
5106static void
5107Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5108{
5109  slotbuf[0] = 0x690000;
5110}
5111
5112static void
5113Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5114{
5115  slotbuf[0] = 0x6b0000;
5116}
5117
5118static void
5119Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
5120{
5121  slotbuf[0] = 0x6a0000;
5122}
5123
5124static void
5125Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
5126{
5127  slotbuf[0] = 0x700600;
5128}
5129
5130static void
5131Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5132{
5133  slotbuf[0] = 0x700e00;
5134}
5135
5136static void
5137Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5138{
5139  slotbuf[0] = 0x6f0000;
5140}
5141
5142static void
5143Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5144{
5145  slotbuf[0] = 0x6e0000;
5146}
5147
5148static void
5149Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
5150{
5151  slotbuf[0] = 0x700100;
5152}
5153
5154static void
5155Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
5156{
5157  slotbuf[0] = 0x700900;
5158}
5159
5160static void
5161Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
5162{
5163  slotbuf[0] = 0x700a00;
5164}
5165
5166static void
5167Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
5168{
5169  slotbuf[0] = 0x700200;
5170}
5171
5172static void
5173Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5174{
5175  slotbuf[0] = 0x700b00;
5176}
5177
5178static void
5179Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5180{
5181  slotbuf[0] = 0x700300;
5182}
5183
5184static void
5185Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
5186{
5187  slotbuf[0] = 0x700800;
5188}
5189
5190static void
5191Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
5192{
5193  slotbuf[0] = 0x700000;
5194}
5195
5196static void
5197Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
5198{
5199  slotbuf[0] = 0x700400;
5200}
5201
5202static void
5203Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5204{
5205  slotbuf[0] = 0x700c00;
5206}
5207
5208static void
5209Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5210{
5211  slotbuf[0] = 0x700500;
5212}
5213
5214static void
5215Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
5216{
5217  slotbuf[0] = 0x700d00;
5218}
5219
5220static void
5221Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5222{
5223  slotbuf[0] = 0x640000;
5224}
5225
5226static void
5227Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5228{
5229  slotbuf[0] = 0x650000;
5230}
5231
5232static void
5233Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5234{
5235  slotbuf[0] = 0x670000;
5236}
5237
5238static void
5239Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5240{
5241  slotbuf[0] = 0x660000;
5242}
5243
5244static void
5245Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
5246{
5247  slotbuf[0] = 0x500000;
5248}
5249
5250static void
5251Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
5252{
5253  slotbuf[0] = 0x30000;
5254}
5255
5256static void
5257Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5258{
5259  slotbuf[0] = 0x40;
5260}
5261
5262static void
5263Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
5264{
5265  slotbuf[0] = 0;
5266}
5267
5268static void
5269Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
5270{
5271  slotbuf[0] = 0x600000;
5272}
5273
5274static void
5275Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
5276{
5277  slotbuf[0] = 0xa0000;
5278}
5279
5280static void
5281Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5282{
5283  slotbuf[0] = 0x200100;
5284}
5285
5286static void
5287Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
5288{
5289  slotbuf[0] = 0x200900;
5290}
5291
5292static void
5293Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5294{
5295  slotbuf[0] = 0x200200;
5296}
5297
5298static void
5299Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
5300{
5301  slotbuf[0] = 0x100000;
5302}
5303
5304static void
5305Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5306{
5307  slotbuf[0] = 0x200000;
5308}
5309
5310static void
5311Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
5312{
5313  slotbuf[0] = 0x6d0800;
5314}
5315
5316static void
5317Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5318{
5319  slotbuf[0] = 0x6d0900;
5320}
5321
5322static void
5323Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5324{
5325  slotbuf[0] = 0x6d0a00;
5326}
5327
5328static void
5329Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5330{
5331  slotbuf[0] = 0x200a00;
5332}
5333
5334static void
5335Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5336{
5337  slotbuf[0] = 0x38;
5338}
5339
5340static void
5341Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5342{
5343  slotbuf[0] = 0x39;
5344}
5345
5346static void
5347Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5348{
5349  slotbuf[0] = 0x3a;
5350}
5351
5352static void
5353Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5354{
5355  slotbuf[0] = 0x3b;
5356}
5357
5358static void
5359Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5360{
5361  slotbuf[0] = 0x6;
5362}
5363
5364static void
5365Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
5366{
5367  slotbuf[0] = 0x1006;
5368}
5369
5370static void
5371Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
5372{
5373  slotbuf[0] = 0xf0200;
5374}
5375
5376static void
5377Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
5378{
5379  slotbuf[0] = 0x20000;
5380}
5381
5382static void
5383Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5384{
5385  slotbuf[0] = 0x200500;
5386}
5387
5388static void
5389Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5390{
5391  slotbuf[0] = 0x200600;
5392}
5393
5394static void
5395Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5396{
5397  slotbuf[0] = 0x200400;
5398}
5399
5400static void
5401Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5402{
5403  slotbuf[0] = 0x4;
5404}
5405
5406static void
5407Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
5408{
5409  slotbuf[0] = 0x104;
5410}
5411
5412static void
5413Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
5414{
5415  slotbuf[0] = 0x204;
5416}
5417
5418static void
5419Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
5420{
5421  slotbuf[0] = 0x304;
5422}
5423
5424static void
5425Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
5426{
5427  slotbuf[0] = 0x404;
5428}
5429
5430static void
5431Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
5432{
5433  slotbuf[0] = 0x1a;
5434}
5435
5436static void
5437Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
5438{
5439  slotbuf[0] = 0x18;
5440}
5441
5442static void
5443Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
5444{
5445  slotbuf[0] = 0x19;
5446}
5447
5448static void
5449Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
5450{
5451  slotbuf[0] = 0x1b;
5452}
5453
5454static void
5455Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
5456{
5457  slotbuf[0] = 0x10;
5458}
5459
5460static void
5461Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
5462{
5463  slotbuf[0] = 0x12;
5464}
5465
5466static void
5467Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
5468{
5469  slotbuf[0] = 0x14;
5470}
5471
5472static void
5473Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5474{
5475  slotbuf[0] = 0xc0200;
5476}
5477
5478static void
5479Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5480{
5481  slotbuf[0] = 0xd0200;
5482}
5483
5484static void
5485Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5486{
5487  slotbuf[0] = 0x200;
5488}
5489
5490static void
5491Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5492{
5493  slotbuf[0] = 0x10200;
5494}
5495
5496static void
5497Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5498{
5499  slotbuf[0] = 0x20200;
5500}
5501
5502static void
5503Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5504{
5505  slotbuf[0] = 0x30200;
5506}
5507
5508static void
5509Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
5510{
5511  slotbuf[0] = 0x600;
5512}
5513
5514static void
5515Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5516{
5517  slotbuf[0] = 0x130;
5518}
5519
5520static void
5521Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5522{
5523  slotbuf[0] = 0x131;
5524}
5525
5526static void
5527Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5528{
5529  slotbuf[0] = 0x116;
5530}
5531
5532static void
5533Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5534{
5535  slotbuf[0] = 0x230;
5536}
5537
5538static void
5539Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5540{
5541  slotbuf[0] = 0x231;
5542}
5543
5544static void
5545Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5546{
5547  slotbuf[0] = 0x216;
5548}
5549
5550static void
5551Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5552{
5553  slotbuf[0] = 0x30;
5554}
5555
5556static void
5557Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5558{
5559  slotbuf[0] = 0x31;
5560}
5561
5562static void
5563Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5564{
5565  slotbuf[0] = 0x16;
5566}
5567
5568static void
5569Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5570{
5571  slotbuf[0] = 0x330;
5572}
5573
5574static void
5575Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5576{
5577  slotbuf[0] = 0x331;
5578}
5579
5580static void
5581Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5582{
5583  slotbuf[0] = 0x316;
5584}
5585
5586static void
5587Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5588{
5589  slotbuf[0] = 0x530;
5590}
5591
5592static void
5593Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5594{
5595  slotbuf[0] = 0x531;
5596}
5597
5598static void
5599Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5600{
5601  slotbuf[0] = 0x516;
5602}
5603
5604static void
5605Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
5606{
5607  slotbuf[0] = 0xb030;
5608}
5609
5610static void
5611Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
5612{
5613  slotbuf[0] = 0xd030;
5614}
5615
5616static void
5617Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
5618{
5619  slotbuf[0] = 0xe630;
5620}
5621
5622static void
5623Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
5624{
5625  slotbuf[0] = 0xe631;
5626}
5627
5628static void
5629Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
5630{
5631  slotbuf[0] = 0xe616;
5632}
5633
5634static void
5635Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5636{
5637  slotbuf[0] = 0xb130;
5638}
5639
5640static void
5641Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5642{
5643  slotbuf[0] = 0xb131;
5644}
5645
5646static void
5647Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5648{
5649  slotbuf[0] = 0xb116;
5650}
5651
5652static void
5653Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5654{
5655  slotbuf[0] = 0xd130;
5656}
5657
5658static void
5659Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5660{
5661  slotbuf[0] = 0xd131;
5662}
5663
5664static void
5665Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
5666{
5667  slotbuf[0] = 0xd116;
5668}
5669
5670static void
5671Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5672{
5673  slotbuf[0] = 0xb230;
5674}
5675
5676static void
5677Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5678{
5679  slotbuf[0] = 0xb231;
5680}
5681
5682static void
5683Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5684{
5685  slotbuf[0] = 0xb216;
5686}
5687
5688static void
5689Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5690{
5691  slotbuf[0] = 0xd230;
5692}
5693
5694static void
5695Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5696{
5697  slotbuf[0] = 0xd231;
5698}
5699
5700static void
5701Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5702{
5703  slotbuf[0] = 0xd216;
5704}
5705
5706static void
5707Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5708{
5709  slotbuf[0] = 0xb330;
5710}
5711
5712static void
5713Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5714{
5715  slotbuf[0] = 0xb331;
5716}
5717
5718static void
5719Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5720{
5721  slotbuf[0] = 0xb316;
5722}
5723
5724static void
5725Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5726{
5727  slotbuf[0] = 0xd330;
5728}
5729
5730static void
5731Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5732{
5733  slotbuf[0] = 0xd331;
5734}
5735
5736static void
5737Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5738{
5739  slotbuf[0] = 0xd316;
5740}
5741
5742static void
5743Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5744{
5745  slotbuf[0] = 0xb430;
5746}
5747
5748static void
5749Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5750{
5751  slotbuf[0] = 0xb431;
5752}
5753
5754static void
5755Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5756{
5757  slotbuf[0] = 0xb416;
5758}
5759
5760static void
5761Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5762{
5763  slotbuf[0] = 0xd430;
5764}
5765
5766static void
5767Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5768{
5769  slotbuf[0] = 0xd431;
5770}
5771
5772static void
5773Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5774{
5775  slotbuf[0] = 0xd416;
5776}
5777
5778static void
5779Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5780{
5781  slotbuf[0] = 0xc230;
5782}
5783
5784static void
5785Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5786{
5787  slotbuf[0] = 0xc231;
5788}
5789
5790static void
5791Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5792{
5793  slotbuf[0] = 0xc216;
5794}
5795
5796static void
5797Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5798{
5799  slotbuf[0] = 0xc330;
5800}
5801
5802static void
5803Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5804{
5805  slotbuf[0] = 0xc331;
5806}
5807
5808static void
5809Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
5810{
5811  slotbuf[0] = 0xc316;
5812}
5813
5814static void
5815Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5816{
5817  slotbuf[0] = 0xc430;
5818}
5819
5820static void
5821Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5822{
5823  slotbuf[0] = 0xc431;
5824}
5825
5826static void
5827Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5828{
5829  slotbuf[0] = 0xc416;
5830}
5831
5832static void
5833Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5834{
5835  slotbuf[0] = 0xee30;
5836}
5837
5838static void
5839Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5840{
5841  slotbuf[0] = 0xee31;
5842}
5843
5844static void
5845Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5846{
5847  slotbuf[0] = 0xee16;
5848}
5849
5850static void
5851Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5852{
5853  slotbuf[0] = 0xc030;
5854}
5855
5856static void
5857Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5858{
5859  slotbuf[0] = 0xc031;
5860}
5861
5862static void
5863Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5864{
5865  slotbuf[0] = 0xc016;
5866}
5867
5868static void
5869Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
5870{
5871  slotbuf[0] = 0xe830;