qemu/target/xtensa/core-sample_controller/xtensa-modules.inc.c
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   1/* Xtensa configuration-specific ISA information.
   2
   3   Copyright (c) 2003-2016 Tensilica Inc.
   4
   5   Permission is hereby granted, free of charge, to any person obtaining
   6   a copy of this software and associated documentation files (the
   7   "Software"), to deal in the Software without restriction, including
   8   without limitation the rights to use, copy, modify, merge, publish,
   9   distribute, sublicense, and/or sell copies of the Software, and to
  10   permit persons to whom the Software is furnished to do so, subject to
  11   the following conditions:
  12
  13   The above copyright notice and this permission notice shall be included
  14   in all copies or substantial portions of the Software.
  15
  16   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  19   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  20   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
  23
  24#include "qemu/osdep.h"
  25#include "xtensa-isa.h"
  26#include "xtensa-isa-internal.h"
  27
  28
  29/* Sysregs.  */
  30
  31static xtensa_sysreg_internal sysregs[] = {
  32  { "MMID", 89, 0 },
  33  { "DDR", 104, 0 },
  34  { "CONFIGID0", 176, 0 },
  35  { "CONFIGID1", 208, 0 },
  36  { "INTERRUPT", 226, 0 },
  37  { "INTCLEAR", 227, 0 },
  38  { "CCOUNT", 234, 0 },
  39  { "PRID", 235, 0 },
  40  { "ICOUNT", 236, 0 },
  41  { "CCOMPARE0", 240, 0 },
  42  { "CCOMPARE1", 241, 0 },
  43  { "CCOMPARE2", 242, 0 },
  44  { "VECBASE", 231, 0 },
  45  { "EPC1", 177, 0 },
  46  { "EPC2", 178, 0 },
  47  { "EPC3", 179, 0 },
  48  { "EPC4", 180, 0 },
  49  { "EPC5", 181, 0 },
  50  { "EPC6", 182, 0 },
  51  { "EPC7", 183, 0 },
  52  { "EXCSAVE1", 209, 0 },
  53  { "EXCSAVE2", 210, 0 },
  54  { "EXCSAVE3", 211, 0 },
  55  { "EXCSAVE4", 212, 0 },
  56  { "EXCSAVE5", 213, 0 },
  57  { "EXCSAVE6", 214, 0 },
  58  { "EXCSAVE7", 215, 0 },
  59  { "EPS2", 194, 0 },
  60  { "EPS3", 195, 0 },
  61  { "EPS4", 196, 0 },
  62  { "EPS5", 197, 0 },
  63  { "EPS6", 198, 0 },
  64  { "EPS7", 199, 0 },
  65  { "EXCCAUSE", 232, 0 },
  66  { "DEPC", 192, 0 },
  67  { "EXCVADDR", 238, 0 },
  68  { "WINDOWBASE", 72, 0 },
  69  { "WINDOWSTART", 73, 0 },
  70  { "SAR", 3, 0 },
  71  { "PS", 230, 0 },
  72  { "MISC0", 244, 0 },
  73  { "MISC1", 245, 0 },
  74  { "INTENABLE", 228, 0 },
  75  { "DBREAKA0", 144, 0 },
  76  { "DBREAKC0", 160, 0 },
  77  { "DBREAKA1", 145, 0 },
  78  { "DBREAKC1", 161, 0 },
  79  { "IBREAKA0", 128, 0 },
  80  { "IBREAKA1", 129, 0 },
  81  { "IBREAKENABLE", 96, 0 },
  82  { "ICOUNTLEVEL", 237, 0 },
  83  { "DEBUGCAUSE", 233, 0 },
  84  { "SCOMPARE1", 12, 0 },
  85  { "ATOMCTL", 99, 0 },
  86  { "EXPSTATE", 230, 1 }
  87};
  88
  89#define NUM_SYSREGS 55
  90#define MAX_SPECIAL_REG 245
  91#define MAX_USER_REG 230
  92
  93
  94/* Processor states.  */
  95
  96static xtensa_state_internal states[] = {
  97  { "PC", 32, 0 },
  98  { "ICOUNT", 32, 0 },
  99  { "DDR", 32, 0 },
 100  { "INTERRUPT", 22, 0 },
 101  { "CCOUNT", 32, 0 },
 102  { "XTSYNC", 1, 0 },
 103  { "VECBASE", 22, 0 },
 104  { "EPC1", 32, 0 },
 105  { "EPC2", 32, 0 },
 106  { "EPC3", 32, 0 },
 107  { "EPC4", 32, 0 },
 108  { "EPC5", 32, 0 },
 109  { "EPC6", 32, 0 },
 110  { "EPC7", 32, 0 },
 111  { "EXCSAVE1", 32, 0 },
 112  { "EXCSAVE2", 32, 0 },
 113  { "EXCSAVE3", 32, 0 },
 114  { "EXCSAVE4", 32, 0 },
 115  { "EXCSAVE5", 32, 0 },
 116  { "EXCSAVE6", 32, 0 },
 117  { "EXCSAVE7", 32, 0 },
 118  { "EPS2", 13, 0 },
 119  { "EPS3", 13, 0 },
 120  { "EPS4", 13, 0 },
 121  { "EPS5", 13, 0 },
 122  { "EPS6", 13, 0 },
 123  { "EPS7", 13, 0 },
 124  { "EXCCAUSE", 6, 0 },
 125  { "PSINTLEVEL", 4, 0 },
 126  { "PSUM", 1, 0 },
 127  { "PSWOE", 1, 0 },
 128  { "PSEXCM", 1, 0 },
 129  { "DEPC", 32, 0 },
 130  { "EXCVADDR", 32, 0 },
 131  { "WindowBase", 3, 0 },
 132  { "WindowStart", 8, 0 },
 133  { "PSCALLINC", 2, 0 },
 134  { "PSOWB", 4, 0 },
 135  { "SAR", 6, 0 },
 136  { "MISC0", 32, 0 },
 137  { "MISC1", 32, 0 },
 138  { "InOCDMode", 1, 0 },
 139  { "INTENABLE", 22, 0 },
 140  { "DBREAKA0", 32, 0 },
 141  { "DBREAKC0", 8, 0 },
 142  { "DBREAKA1", 32, 0 },
 143  { "DBREAKC1", 8, 0 },
 144  { "IBREAKA0", 32, 0 },
 145  { "IBREAKA1", 32, 0 },
 146  { "IBREAKENABLE", 2, 0 },
 147  { "ICOUNTLEVEL", 4, 0 },
 148  { "DEBUGCAUSE", 6, 0 },
 149  { "DBNUM", 4, 0 },
 150  { "CCOMPARE0", 32, 0 },
 151  { "CCOMPARE1", 32, 0 },
 152  { "CCOMPARE2", 32, 0 },
 153  { "SCOMPARE1", 32, 0 },
 154  { "ATOMCTL", 6, 0 },
 155  { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
 156};
 157
 158#define NUM_STATES 59
 159
 160enum xtensa_state_id {
 161  STATE_PC,
 162  STATE_ICOUNT,
 163  STATE_DDR,
 164  STATE_INTERRUPT,
 165  STATE_CCOUNT,
 166  STATE_XTSYNC,
 167  STATE_VECBASE,
 168  STATE_EPC1,
 169  STATE_EPC2,
 170  STATE_EPC3,
 171  STATE_EPC4,
 172  STATE_EPC5,
 173  STATE_EPC6,
 174  STATE_EPC7,
 175  STATE_EXCSAVE1,
 176  STATE_EXCSAVE2,
 177  STATE_EXCSAVE3,
 178  STATE_EXCSAVE4,
 179  STATE_EXCSAVE5,
 180  STATE_EXCSAVE6,
 181  STATE_EXCSAVE7,
 182  STATE_EPS2,
 183  STATE_EPS3,
 184  STATE_EPS4,
 185  STATE_EPS5,
 186  STATE_EPS6,
 187  STATE_EPS7,
 188  STATE_EXCCAUSE,
 189  STATE_PSINTLEVEL,
 190  STATE_PSUM,
 191  STATE_PSWOE,
 192  STATE_PSEXCM,
 193  STATE_DEPC,
 194  STATE_EXCVADDR,
 195  STATE_WindowBase,
 196  STATE_WindowStart,
 197  STATE_PSCALLINC,
 198  STATE_PSOWB,
 199  STATE_SAR,
 200  STATE_MISC0,
 201  STATE_MISC1,
 202  STATE_InOCDMode,
 203  STATE_INTENABLE,
 204  STATE_DBREAKA0,
 205  STATE_DBREAKC0,
 206  STATE_DBREAKA1,
 207  STATE_DBREAKC1,
 208  STATE_IBREAKA0,
 209  STATE_IBREAKA1,
 210  STATE_IBREAKENABLE,
 211  STATE_ICOUNTLEVEL,
 212  STATE_DEBUGCAUSE,
 213  STATE_DBNUM,
 214  STATE_CCOMPARE0,
 215  STATE_CCOMPARE1,
 216  STATE_CCOMPARE2,
 217  STATE_SCOMPARE1,
 218  STATE_ATOMCTL,
 219  STATE_EXPSTATE
 220};
 221
 222
 223/* Field definitions.  */
 224
 225static unsigned
 226Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 227{
 228  unsigned tie_t = 0;
 229  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 230  return tie_t;
 231}
 232
 233static void
 234Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 235{
 236  uint32 tie_t;
 237  tie_t = (val << 28) >> 28;
 238  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 239}
 240
 241static unsigned
 242Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 243{
 244  unsigned tie_t = 0;
 245  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 246  return tie_t;
 247}
 248
 249static void
 250Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 251{
 252  uint32 tie_t;
 253  tie_t = (val << 28) >> 28;
 254  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 255}
 256
 257static unsigned
 258Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 259{
 260  unsigned tie_t = 0;
 261  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 262  return tie_t;
 263}
 264
 265static void
 266Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 267{
 268  uint32 tie_t;
 269  tie_t = (val << 28) >> 28;
 270  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 271}
 272
 273static unsigned
 274Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 275{
 276  unsigned tie_t = 0;
 277  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 278  return tie_t;
 279}
 280
 281static void
 282Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 283{
 284  uint32 tie_t;
 285  tie_t = (val << 28) >> 28;
 286  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 287}
 288
 289static unsigned
 290Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 291{
 292  unsigned tie_t = 0;
 293  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 294  return tie_t;
 295}
 296
 297static void
 298Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 299{
 300  uint32 tie_t;
 301  tie_t = (val << 28) >> 28;
 302  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 303}
 304
 305static unsigned
 306Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 307{
 308  unsigned tie_t = 0;
 309  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 310  return tie_t;
 311}
 312
 313static void
 314Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 315{
 316  uint32 tie_t;
 317  tie_t = (val << 28) >> 28;
 318  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 319}
 320
 321static unsigned
 322Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 323{
 324  unsigned tie_t = 0;
 325  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 326  return tie_t;
 327}
 328
 329static void
 330Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 331{
 332  uint32 tie_t;
 333  tie_t = (val << 30) >> 30;
 334  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 335}
 336
 337static unsigned
 338Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 339{
 340  unsigned tie_t = 0;
 341  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
 342  return tie_t;
 343}
 344
 345static void
 346Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 347{
 348  uint32 tie_t;
 349  tie_t = (val << 30) >> 30;
 350  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 351}
 352
 353static unsigned
 354Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 355{
 356  unsigned tie_t = 0;
 357  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 358  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 359  return tie_t;
 360}
 361
 362static void
 363Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 364{
 365  uint32 tie_t;
 366  tie_t = (val << 28) >> 28;
 367  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 368  tie_t = (val << 24) >> 28;
 369  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 370}
 371
 372static unsigned
 373Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 374{
 375  unsigned tie_t = 0;
 376  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
 377  return tie_t;
 378}
 379
 380static void
 381Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 382{
 383  uint32 tie_t;
 384  tie_t = (val << 29) >> 29;
 385  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
 386}
 387
 388static unsigned
 389Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 390{
 391  unsigned tie_t = 0;
 392  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 393  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 394  return tie_t;
 395}
 396
 397static void
 398Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 399{
 400  uint32 tie_t;
 401  tie_t = (val << 28) >> 28;
 402  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 403  tie_t = (val << 24) >> 28;
 404  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 405}
 406
 407static unsigned
 408Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
 409{
 410  unsigned tie_t = 0;
 411  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
 412  return tie_t;
 413}
 414
 415static void
 416Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 417{
 418  uint32 tie_t;
 419  tie_t = (val << 29) >> 29;
 420  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
 421}
 422
 423static unsigned
 424Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 425{
 426  unsigned tie_t = 0;
 427  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 428  return tie_t;
 429}
 430
 431static void
 432Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 433{
 434  uint32 tie_t;
 435  tie_t = (val << 28) >> 28;
 436  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 437}
 438
 439static unsigned
 440Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 441{
 442  unsigned tie_t = 0;
 443  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 444  return tie_t;
 445}
 446
 447static void
 448Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 449{
 450  uint32 tie_t;
 451  tie_t = (val << 28) >> 28;
 452  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 453}
 454
 455static unsigned
 456Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 457{
 458  unsigned tie_t = 0;
 459  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 460  return tie_t;
 461}
 462
 463static void
 464Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 465{
 466  uint32 tie_t;
 467  tie_t = (val << 28) >> 28;
 468  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 469}
 470
 471static unsigned
 472Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 473{
 474  unsigned tie_t = 0;
 475  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 476  return tie_t;
 477}
 478
 479static void
 480Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 481{
 482  uint32 tie_t;
 483  tie_t = (val << 28) >> 28;
 484  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 485}
 486
 487static unsigned
 488Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
 489{
 490  unsigned tie_t = 0;
 491  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
 492  return tie_t;
 493}
 494
 495static void
 496Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 497{
 498  uint32 tie_t;
 499  tie_t = (val << 31) >> 31;
 500  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
 501}
 502
 503static unsigned
 504Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 505{
 506  unsigned tie_t = 0;
 507  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
 508  return tie_t;
 509}
 510
 511static void
 512Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 513{
 514  uint32 tie_t;
 515  tie_t = (val << 31) >> 31;
 516  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
 517}
 518
 519static unsigned
 520Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 521{
 522  unsigned tie_t = 0;
 523  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 524  return tie_t;
 525}
 526
 527static void
 528Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 529{
 530  uint32 tie_t;
 531  tie_t = (val << 28) >> 28;
 532  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 533}
 534
 535static unsigned
 536Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 537{
 538  unsigned tie_t = 0;
 539  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 540  return tie_t;
 541}
 542
 543static void
 544Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 545{
 546  uint32 tie_t;
 547  tie_t = (val << 28) >> 28;
 548  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 549}
 550
 551static unsigned
 552Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 553{
 554  unsigned tie_t = 0;
 555  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 556  return tie_t;
 557}
 558
 559static void
 560Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 561{
 562  uint32 tie_t;
 563  tie_t = (val << 31) >> 31;
 564  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 565}
 566
 567static unsigned
 568Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 569{
 570  unsigned tie_t = 0;
 571  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 572  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 573  return tie_t;
 574}
 575
 576static void
 577Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 578{
 579  uint32 tie_t;
 580  tie_t = (val << 28) >> 28;
 581  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 582  tie_t = (val << 27) >> 31;
 583  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 584}
 585
 586static unsigned
 587Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 588{
 589  unsigned tie_t = 0;
 590  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
 591  return tie_t;
 592}
 593
 594static void
 595Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 596{
 597  uint32 tie_t;
 598  tie_t = (val << 20) >> 20;
 599  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
 600}
 601
 602static unsigned
 603Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 604{
 605  unsigned tie_t = 0;
 606  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 607  return tie_t;
 608}
 609
 610static void
 611Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 612{
 613  uint32 tie_t;
 614  tie_t = (val << 24) >> 24;
 615  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 616}
 617
 618static unsigned
 619Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 620{
 621  unsigned tie_t = 0;
 622  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 623  return tie_t;
 624}
 625
 626static void
 627Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 628{
 629  uint32 tie_t;
 630  tie_t = (val << 28) >> 28;
 631  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 632}
 633
 634static unsigned
 635Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 636{
 637  unsigned tie_t = 0;
 638  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 639  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 640  return tie_t;
 641}
 642
 643static void
 644Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 645{
 646  uint32 tie_t;
 647  tie_t = (val << 24) >> 24;
 648  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 649  tie_t = (val << 20) >> 28;
 650  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 651}
 652
 653static unsigned
 654Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 655{
 656  unsigned tie_t = 0;
 657  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
 658  return tie_t;
 659}
 660
 661static void
 662Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 663{
 664  uint32 tie_t;
 665  tie_t = (val << 16) >> 16;
 666  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
 667}
 668
 669static unsigned
 670Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 671{
 672  unsigned tie_t = 0;
 673  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
 674  return tie_t;
 675}
 676
 677static void
 678Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 679{
 680  uint32 tie_t;
 681  tie_t = (val << 14) >> 14;
 682  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
 683}
 684
 685static unsigned
 686Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 687{
 688  unsigned tie_t = 0;
 689  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 690  return tie_t;
 691}
 692
 693static void
 694Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 695{
 696  uint32 tie_t;
 697  tie_t = (val << 28) >> 28;
 698  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 699}
 700
 701static unsigned
 702Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 703{
 704  unsigned tie_t = 0;
 705  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 706  return tie_t;
 707}
 708
 709static void
 710Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 711{
 712  uint32 tie_t;
 713  tie_t = (val << 31) >> 31;
 714  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 715}
 716
 717static unsigned
 718Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 719{
 720  unsigned tie_t = 0;
 721  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 722  return tie_t;
 723}
 724
 725static void
 726Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 727{
 728  uint32 tie_t;
 729  tie_t = (val << 31) >> 31;
 730  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 731}
 732
 733static unsigned
 734Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
 735{
 736  unsigned tie_t = 0;
 737  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 738  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 739  return tie_t;
 740}
 741
 742static void
 743Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 744{
 745  uint32 tie_t;
 746  tie_t = (val << 28) >> 28;
 747  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 748  tie_t = (val << 27) >> 31;
 749  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 750}
 751
 752static unsigned
 753Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
 754{
 755  unsigned tie_t = 0;
 756  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 757  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 758  return tie_t;
 759}
 760
 761static void
 762Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 763{
 764  uint32 tie_t;
 765  tie_t = (val << 28) >> 28;
 766  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 767  tie_t = (val << 27) >> 31;
 768  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 769}
 770
 771static unsigned
 772Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
 773{
 774  unsigned tie_t = 0;
 775  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 776  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 777  return tie_t;
 778}
 779
 780static void
 781Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 782{
 783  uint32 tie_t;
 784  tie_t = (val << 28) >> 28;
 785  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 786  tie_t = (val << 27) >> 31;
 787  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 788}
 789
 790static unsigned
 791Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
 792{
 793  unsigned tie_t = 0;
 794  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 795  return tie_t;
 796}
 797
 798static void
 799Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 800{
 801  uint32 tie_t;
 802  tie_t = (val << 31) >> 31;
 803  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 804}
 805
 806static unsigned
 807Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
 808{
 809  unsigned tie_t = 0;
 810  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 811  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 812  return tie_t;
 813}
 814
 815static void
 816Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 817{
 818  uint32 tie_t;
 819  tie_t = (val << 28) >> 28;
 820  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 821  tie_t = (val << 27) >> 31;
 822  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 823}
 824
 825static unsigned
 826Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
 827{
 828  unsigned tie_t = 0;
 829  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 830  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 831  return tie_t;
 832}
 833
 834static void
 835Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 836{
 837  uint32 tie_t;
 838  tie_t = (val << 28) >> 28;
 839  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 840  tie_t = (val << 24) >> 28;
 841  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 842}
 843
 844static unsigned
 845Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
 846{
 847  unsigned tie_t = 0;
 848  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 849  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 850  return tie_t;
 851}
 852
 853static void
 854Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 855{
 856  uint32 tie_t;
 857  tie_t = (val << 28) >> 28;
 858  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 859  tie_t = (val << 24) >> 28;
 860  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 861}
 862
 863static unsigned
 864Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
 865{
 866  unsigned tie_t = 0;
 867  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 868  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 869  return tie_t;
 870}
 871
 872static void
 873Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 874{
 875  uint32 tie_t;
 876  tie_t = (val << 28) >> 28;
 877  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 878  tie_t = (val << 24) >> 28;
 879  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 880}
 881
 882static unsigned
 883Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
 884{
 885  unsigned tie_t = 0;
 886  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 887  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 888  return tie_t;
 889}
 890
 891static void
 892Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 893{
 894  uint32 tie_t;
 895  tie_t = (val << 28) >> 28;
 896  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 897  tie_t = (val << 24) >> 28;
 898  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 899}
 900
 901static unsigned
 902Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
 903{
 904  unsigned tie_t = 0;
 905  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 906  return tie_t;
 907}
 908
 909static void
 910Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 911{
 912  uint32 tie_t;
 913  tie_t = (val << 28) >> 28;
 914  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 915}
 916
 917static unsigned
 918Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
 919{
 920  unsigned tie_t = 0;
 921  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 922  return tie_t;
 923}
 924
 925static void
 926Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 927{
 928  uint32 tie_t;
 929  tie_t = (val << 28) >> 28;
 930  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 931}
 932
 933static unsigned
 934Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
 935{
 936  unsigned tie_t = 0;
 937  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 938  return tie_t;
 939}
 940
 941static void
 942Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 943{
 944  uint32 tie_t;
 945  tie_t = (val << 28) >> 28;
 946  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 947}
 948
 949static unsigned
 950Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
 951{
 952  unsigned tie_t = 0;
 953  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
 954  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 955  return tie_t;
 956}
 957
 958static void
 959Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 960{
 961  uint32 tie_t;
 962  tie_t = (val << 30) >> 30;
 963  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 964  tie_t = (val << 28) >> 30;
 965  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 966}
 967
 968static unsigned
 969Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
 970{
 971  unsigned tie_t = 0;
 972  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
 973  return tie_t;
 974}
 975
 976static void
 977Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 978{
 979  uint32 tie_t;
 980  tie_t = (val << 31) >> 31;
 981  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
 982}
 983
 984static unsigned
 985Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
 986{
 987  unsigned tie_t = 0;
 988  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 989  return tie_t;
 990}
 991
 992static void
 993Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 994{
 995  uint32 tie_t;
 996  tie_t = (val << 28) >> 28;
 997  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 998}
 999
1000static unsigned
1001Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1002{
1003  unsigned tie_t = 0;
1004  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1005  return tie_t;
1006}
1007
1008static void
1009Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1010{
1011  uint32 tie_t;
1012  tie_t = (val << 28) >> 28;
1013  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1014}
1015
1016static unsigned
1017Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1018{
1019  unsigned tie_t = 0;
1020  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1021  return tie_t;
1022}
1023
1024static void
1025Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1026{
1027  uint32 tie_t;
1028  tie_t = (val << 30) >> 30;
1029  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1030}
1031
1032static unsigned
1033Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1034{
1035  unsigned tie_t = 0;
1036  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1037  return tie_t;
1038}
1039
1040static void
1041Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1042{
1043  uint32 tie_t;
1044  tie_t = (val << 30) >> 30;
1045  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1046}
1047
1048static unsigned
1049Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1050{
1051  unsigned tie_t = 0;
1052  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1053  return tie_t;
1054}
1055
1056static void
1057Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1058{
1059  uint32 tie_t;
1060  tie_t = (val << 28) >> 28;
1061  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1062}
1063
1064static unsigned
1065Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1066{
1067  unsigned tie_t = 0;
1068  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1069  return tie_t;
1070}
1071
1072static void
1073Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1074{
1075  uint32 tie_t;
1076  tie_t = (val << 28) >> 28;
1077  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1078}
1079
1080static unsigned
1081Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1082{
1083  unsigned tie_t = 0;
1084  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1085  return tie_t;
1086}
1087
1088static void
1089Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1090{
1091  uint32 tie_t;
1092  tie_t = (val << 29) >> 29;
1093  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1094}
1095
1096static unsigned
1097Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1098{
1099  unsigned tie_t = 0;
1100  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1101  return tie_t;
1102}
1103
1104static void
1105Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1106{
1107  uint32 tie_t;
1108  tie_t = (val << 29) >> 29;
1109  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1110}
1111
1112static unsigned
1113Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1114{
1115  unsigned tie_t = 0;
1116  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1117  return tie_t;
1118}
1119
1120static void
1121Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1122{
1123  uint32 tie_t;
1124  tie_t = (val << 31) >> 31;
1125  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1126}
1127
1128static unsigned
1129Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1130{
1131  unsigned tie_t = 0;
1132  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1133  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1134  return tie_t;
1135}
1136
1137static void
1138Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1139{
1140  uint32 tie_t;
1141  tie_t = (val << 28) >> 28;
1142  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1143  tie_t = (val << 26) >> 30;
1144  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1145}
1146
1147static unsigned
1148Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1149{
1150  unsigned tie_t = 0;
1151  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1152  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1153  return tie_t;
1154}
1155
1156static void
1157Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1158{
1159  uint32 tie_t;
1160  tie_t = (val << 28) >> 28;
1161  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1162  tie_t = (val << 26) >> 30;
1163  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1164}
1165
1166static unsigned
1167Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1168{
1169  unsigned tie_t = 0;
1170  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1171  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1172  return tie_t;
1173}
1174
1175static void
1176Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1177{
1178  uint32 tie_t;
1179  tie_t = (val << 28) >> 28;
1180  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1181  tie_t = (val << 25) >> 29;
1182  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1183}
1184
1185static unsigned
1186Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1187{
1188  unsigned tie_t = 0;
1189  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1190  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1191  return tie_t;
1192}
1193
1194static void
1195Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1196{
1197  uint32 tie_t;
1198  tie_t = (val << 28) >> 28;
1199  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1200  tie_t = (val << 25) >> 29;
1201  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1202}
1203
1204static unsigned
1205Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1206{
1207  unsigned tie_t = 0;
1208  tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1209  return tie_t;
1210}
1211
1212static void
1213Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1214{
1215  uint32 tie_t;
1216  tie_t = (val << 17) >> 17;
1217  insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1218}
1219
1220static unsigned
1221Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1222{
1223  unsigned tie_t = 0;
1224  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1225  return tie_t;
1226}
1227
1228static void
1229Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1230{
1231  uint32 tie_t;
1232  tie_t = (val << 14) >> 14;
1233  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1234}
1235
1236static unsigned
1237Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1238{
1239  unsigned tie_t = 0;
1240  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1241  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1242  return tie_t;
1243}
1244
1245static void
1246Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1247{
1248  uint32 tie_t;
1249  tie_t = (val << 28) >> 28;
1250  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1251  tie_t = (val << 27) >> 31;
1252  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1253}
1254
1255static unsigned
1256Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1257{
1258  unsigned tie_t = 0;
1259  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1260  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1261  return tie_t;
1262}
1263
1264static void
1265Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1266{
1267  uint32 tie_t;
1268  tie_t = (val << 28) >> 28;
1269  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1270  tie_t = (val << 27) >> 31;
1271  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1272}
1273
1274static unsigned
1275Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1276{
1277  unsigned tie_t = 0;
1278  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1279  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1280  return tie_t;
1281}
1282
1283static void
1284Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1285{
1286  uint32 tie_t;
1287  tie_t = (val << 28) >> 28;
1288  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1289  tie_t = (val << 27) >> 31;
1290  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1291}
1292
1293static unsigned
1294Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1295{
1296  unsigned tie_t = 0;
1297  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1298  return tie_t;
1299}
1300
1301static void
1302Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1303{
1304  uint32 tie_t;
1305  tie_t = (val << 29) >> 29;
1306  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1307}
1308
1309static unsigned
1310Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1311{
1312  unsigned tie_t = 0;
1313  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1314  return tie_t;
1315}
1316
1317static void
1318Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1319{
1320  uint32 tie_t;
1321  tie_t = (val << 29) >> 29;
1322  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1323}
1324
1325static void
1326Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1327                    uint32 val ATTRIBUTE_UNUSED)
1328{
1329  /* Do nothing.  */
1330}
1331
1332static unsigned
1333Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1334{
1335  return 0;
1336}
1337
1338static unsigned
1339Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1340{
1341  return 4;
1342}
1343
1344static unsigned
1345Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1346{
1347  return 8;
1348}
1349
1350static unsigned
1351Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1352{
1353  return 12;
1354}
1355
1356enum xtensa_field_id {
1357  FIELD_t,
1358  FIELD_bbi4,
1359  FIELD_bbi,
1360  FIELD_imm12,
1361  FIELD_imm8,
1362  FIELD_s,
1363  FIELD_imm12b,
1364  FIELD_imm16,
1365  FIELD_m,
1366  FIELD_n,
1367  FIELD_offset,
1368  FIELD_op0,
1369  FIELD_op1,
1370  FIELD_op2,
1371  FIELD_r,
1372  FIELD_sa4,
1373  FIELD_sae4,
1374  FIELD_sae,
1375  FIELD_sal,
1376  FIELD_sargt,
1377  FIELD_sas4,
1378  FIELD_sas,
1379  FIELD_sr,
1380  FIELD_st,
1381  FIELD_thi3,
1382  FIELD_imm4,
1383  FIELD_mn,
1384  FIELD_i,
1385  FIELD_imm6lo,
1386  FIELD_imm6hi,
1387  FIELD_imm7lo,
1388  FIELD_imm7hi,
1389  FIELD_z,
1390  FIELD_imm6,
1391  FIELD_imm7,
1392  FIELD_xt_wbr15_imm,
1393  FIELD_xt_wbr18_imm,
1394  FIELD_bitindex,
1395  FIELD_s3to1,
1396  FIELD__ar0,
1397  FIELD__ar4,
1398  FIELD__ar8,
1399  FIELD__ar12
1400};
1401
1402
1403/* Functional units.  */
1404
1405#define funcUnits 0
1406
1407
1408/* Register files.  */
1409
1410enum xtensa_regfile_id {
1411  REGFILE_AR
1412};
1413
1414static xtensa_regfile_internal regfiles[] = {
1415  { "AR", "a", REGFILE_AR, 32, 32 }
1416};
1417
1418
1419/* Interfaces.  */
1420
1421static xtensa_interface_internal interfaces[] = {
1422  { "IMPWIRE", 32, 0, 0, 'i' }
1423};
1424
1425enum xtensa_interface_id {
1426  INTERFACE_IMPWIRE
1427};
1428
1429
1430/* Constant tables.  */
1431
1432/* constant table ai4c */
1433static const unsigned CONST_TBL_ai4c_0[] = {
1434  0xffffffff,
1435  0x1,
1436  0x2,
1437  0x3,
1438  0x4,
1439  0x5,
1440  0x6,
1441  0x7,
1442  0x8,
1443  0x9,
1444  0xa,
1445  0xb,
1446  0xc,
1447  0xd,
1448  0xe,
1449  0xf,
1450  0
1451};
1452
1453/* constant table b4c */
1454static const unsigned CONST_TBL_b4c_0[] = {
1455  0xffffffff,
1456  0x1,
1457  0x2,
1458  0x3,
1459  0x4,
1460  0x5,
1461  0x6,
1462  0x7,
1463  0x8,
1464  0xa,
1465  0xc,
1466  0x10,
1467  0x20,
1468  0x40,
1469  0x80,
1470  0x100,
1471  0
1472};
1473
1474/* constant table b4cu */
1475static const unsigned CONST_TBL_b4cu_0[] = {
1476  0x8000,
1477  0x10000,
1478  0x2,
1479  0x3,
1480  0x4,
1481  0x5,
1482  0x6,
1483  0x7,
1484  0x8,
1485  0xa,
1486  0xc,
1487  0x10,
1488  0x20,
1489  0x40,
1490  0x80,
1491  0x100,
1492  0
1493};
1494
1495
1496/* Instruction operands.  */
1497
1498static int
1499OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
1500{
1501  unsigned soffsetx4_out_0;
1502  unsigned soffsetx4_in_0;
1503  soffsetx4_in_0 = *valp & 0x3ffff;
1504  soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1505  *valp = soffsetx4_out_0;
1506  return 0;
1507}
1508
1509static int
1510OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
1511{
1512  unsigned soffsetx4_in_0;
1513  unsigned soffsetx4_out_0;
1514  soffsetx4_out_0 = *valp;
1515  soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1516  *valp = soffsetx4_in_0;
1517  return 0;
1518}
1519
1520static int
1521OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
1522{
1523  unsigned uimm12x8_out_0;
1524  unsigned uimm12x8_in_0;
1525  uimm12x8_in_0 = *valp & 0xfff;
1526  uimm12x8_out_0 = uimm12x8_in_0 << 3;
1527  *valp = uimm12x8_out_0;
1528  return 0;
1529}
1530
1531static int
1532OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
1533{
1534  unsigned uimm12x8_in_0;
1535  unsigned uimm12x8_out_0;
1536  uimm12x8_out_0 = *valp;
1537  uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1538  *valp = uimm12x8_in_0;
1539  return 0;
1540}
1541
1542static int
1543OperandSem_opnd_sem_simm4_decode (uint32 *valp)
1544{
1545  unsigned simm4_out_0;
1546  unsigned simm4_in_0;
1547  simm4_in_0 = *valp & 0xf;
1548  simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
1549  *valp = simm4_out_0;
1550  return 0;
1551}
1552
1553static int
1554OperandSem_opnd_sem_simm4_encode (uint32 *valp)
1555{
1556  unsigned simm4_in_0;
1557  unsigned simm4_out_0;
1558  simm4_out_0 = *valp;
1559  simm4_in_0 = (simm4_out_0 & 0xf);
1560  *valp = simm4_in_0;
1561  return 0;
1562}
1563
1564static int
1565OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
1566{
1567  return 0;
1568}
1569
1570static int
1571OperandSem_opnd_sem_AR_encode (uint32 *valp)
1572{
1573  return (*valp >= 32);
1574}
1575
1576static int
1577OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1578{
1579  return 0;
1580}
1581
1582static int
1583OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
1584{
1585  return (*valp >= 32);
1586}
1587
1588static int
1589OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
1590{
1591  return 0;
1592}
1593
1594static int
1595OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
1596{
1597  return (*valp >= 32);
1598}
1599
1600static int
1601OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
1602{
1603  return 0;
1604}
1605
1606static int
1607OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
1608{
1609  return (*valp >= 32);
1610}
1611
1612static int
1613OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
1614{
1615  return 0;
1616}
1617
1618static int
1619OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
1620{
1621  return (*valp >= 32);
1622}
1623
1624static int
1625OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1626{
1627  return 0;
1628}
1629
1630static int
1631OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
1632{
1633  return (*valp >= 32);
1634}
1635
1636static int
1637OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
1638{
1639  unsigned immrx4_out_0;
1640  unsigned immrx4_in_0;
1641  immrx4_in_0 = *valp & 0xf;
1642  immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1643  *valp = immrx4_out_0;
1644  return 0;
1645}
1646
1647static int
1648OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
1649{
1650  unsigned immrx4_in_0;
1651  unsigned immrx4_out_0;
1652  immrx4_out_0 = *valp;
1653  immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1654  *valp = immrx4_in_0;
1655  return 0;
1656}
1657
1658static int
1659OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
1660{
1661  unsigned lsi4x4_out_0;
1662  unsigned lsi4x4_in_0;
1663  lsi4x4_in_0 = *valp & 0xf;
1664  lsi4x4_out_0 = lsi4x4_in_0 << 2;
1665  *valp = lsi4x4_out_0;
1666  return 0;
1667}
1668
1669static int
1670OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
1671{
1672  unsigned lsi4x4_in_0;
1673  unsigned lsi4x4_out_0;
1674  lsi4x4_out_0 = *valp;
1675  lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1676  *valp = lsi4x4_in_0;
1677  return 0;
1678}
1679
1680static int
1681OperandSem_opnd_sem_simm7_decode (uint32 *valp)
1682{
1683  unsigned simm7_out_0;
1684  unsigned simm7_in_0;
1685  simm7_in_0 = *valp & 0x7f;
1686  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
1687  *valp = simm7_out_0;
1688  return 0;
1689}
1690
1691static int
1692OperandSem_opnd_sem_simm7_encode (uint32 *valp)
1693{
1694  unsigned simm7_in_0;
1695  unsigned simm7_out_0;
1696  simm7_out_0 = *valp;
1697  simm7_in_0 = (simm7_out_0 & 0x7f);
1698  *valp = simm7_in_0;
1699  return 0;
1700}
1701
1702static int
1703OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
1704{
1705  unsigned uimm6_out_0;
1706  unsigned uimm6_in_0;
1707  uimm6_in_0 = *valp & 0x3f;
1708  uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1709  *valp = uimm6_out_0;
1710  return 0;
1711}
1712
1713static int
1714OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
1715{
1716  unsigned uimm6_in_0;
1717  unsigned uimm6_out_0;
1718  uimm6_out_0 = *valp;
1719  uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1720  *valp = uimm6_in_0;
1721  return 0;
1722}
1723
1724static int
1725OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
1726{
1727  unsigned ai4const_out_0;
1728  unsigned ai4const_in_0;
1729  ai4const_in_0 = *valp & 0xf;
1730  ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1731  *valp = ai4const_out_0;
1732  return 0;
1733}
1734
1735static int
1736OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
1737{
1738  unsigned ai4const_in_0;
1739  unsigned ai4const_out_0;
1740  ai4const_out_0 = *valp;
1741  switch (ai4const_out_0)
1742    {
1743    case 0xffffffff: ai4const_in_0 = 0; break;
1744    case 0x1: ai4const_in_0 = 0x1; break;
1745    case 0x2: ai4const_in_0 = 0x2; break;
1746    case 0x3: ai4const_in_0 = 0x3; break;
1747    case 0x4: ai4const_in_0 = 0x4; break;
1748    case 0x5: ai4const_in_0 = 0x5; break;
1749    case 0x6: ai4const_in_0 = 0x6; break;
1750    case 0x7: ai4const_in_0 = 0x7; break;
1751    case 0x8: ai4const_in_0 = 0x8; break;
1752    case 0x9: ai4const_in_0 = 0x9; break;
1753    case 0xa: ai4const_in_0 = 0xa; break;
1754    case 0xb: ai4const_in_0 = 0xb; break;
1755    case 0xc: ai4const_in_0 = 0xc; break;
1756    case 0xd: ai4const_in_0 = 0xd; break;
1757    case 0xe: ai4const_in_0 = 0xe; break;
1758    default: ai4const_in_0 = 0xf; break;
1759    }
1760  *valp = ai4const_in_0;
1761  return 0;
1762}
1763
1764static int
1765OperandSem_opnd_sem_b4const_decode (uint32 *valp)
1766{
1767  unsigned b4const_out_0;
1768  unsigned b4const_in_0;
1769  b4const_in_0 = *valp & 0xf;
1770  b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
1771  *valp = b4const_out_0;
1772  return 0;
1773}
1774
1775static int
1776OperandSem_opnd_sem_b4const_encode (uint32 *valp)
1777{
1778  unsigned b4const_in_0;
1779  unsigned b4const_out_0;
1780  b4const_out_0 = *valp;
1781  switch (b4const_out_0)
1782    {
1783    case 0xffffffff: b4const_in_0 = 0; break;
1784    case 0x1: b4const_in_0 = 0x1; break;
1785    case 0x2: b4const_in_0 = 0x2; break;
1786    case 0x3: b4const_in_0 = 0x3; break;
1787    case 0x4: b4const_in_0 = 0x4; break;
1788    case 0x5: b4const_in_0 = 0x5; break;
1789    case 0x6: b4const_in_0 = 0x6; break;
1790    case 0x7: b4const_in_0 = 0x7; break;
1791    case 0x8: b4const_in_0 = 0x8; break;
1792    case 0xa: b4const_in_0 = 0x9; break;
1793    case 0xc: b4const_in_0 = 0xa; break;
1794    case 0x10: b4const_in_0 = 0xb; break;
1795    case 0x20: b4const_in_0 = 0xc; break;
1796    case 0x40: b4const_in_0 = 0xd; break;
1797    case 0x80: b4const_in_0 = 0xe; break;
1798    default: b4const_in_0 = 0xf; break;
1799    }
1800  *valp = b4const_in_0;
1801  return 0;
1802}
1803
1804static int
1805OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
1806{
1807  unsigned b4constu_out_0;
1808  unsigned b4constu_in_0;
1809  b4constu_in_0 = *valp & 0xf;
1810  b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
1811  *valp = b4constu_out_0;
1812  return 0;
1813}
1814
1815static int
1816OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
1817{
1818  unsigned b4constu_in_0;
1819  unsigned b4constu_out_0;
1820  b4constu_out_0 = *valp;
1821  switch (b4constu_out_0)
1822    {
1823    case 0x8000: b4constu_in_0 = 0; break;
1824    case 0x10000: b4constu_in_0 = 0x1; break;
1825    case 0x2: b4constu_in_0 = 0x2; break;
1826    case 0x3: b4constu_in_0 = 0x3; break;
1827    case 0x4: b4constu_in_0 = 0x4; break;
1828    case 0x5: b4constu_in_0 = 0x5; break;
1829    case 0x6: b4constu_in_0 = 0x6; break;
1830    case 0x7: b4constu_in_0 = 0x7; break;
1831    case 0x8: b4constu_in_0 = 0x8; break;
1832    case 0xa: b4constu_in_0 = 0x9; break;
1833    case 0xc: b4constu_in_0 = 0xa; break;
1834    case 0x10: b4constu_in_0 = 0xb; break;
1835    case 0x20: b4constu_in_0 = 0xc; break;
1836    case 0x40: b4constu_in_0 = 0xd; break;
1837    case 0x80: b4constu_in_0 = 0xe; break;
1838    default: b4constu_in_0 = 0xf; break;
1839    }
1840  *valp = b4constu_in_0;
1841  return 0;
1842}
1843
1844static int
1845OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
1846{
1847  unsigned uimm8_out_0;
1848  unsigned uimm8_in_0;
1849  uimm8_in_0 = *valp & 0xff;
1850  uimm8_out_0 = uimm8_in_0;
1851  *valp = uimm8_out_0;
1852  return 0;
1853}
1854
1855static int
1856OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
1857{
1858  unsigned uimm8_in_0;
1859  unsigned uimm8_out_0;
1860  uimm8_out_0 = *valp;
1861  uimm8_in_0 = (uimm8_out_0 & 0xff);
1862  *valp = uimm8_in_0;
1863  return 0;
1864}
1865
1866static int
1867OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
1868{
1869  unsigned uimm8x2_out_0;
1870  unsigned uimm8x2_in_0;
1871  uimm8x2_in_0 = *valp & 0xff;
1872  uimm8x2_out_0 = uimm8x2_in_0 << 1;
1873  *valp = uimm8x2_out_0;
1874  return 0;
1875}
1876
1877static int
1878OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
1879{
1880  unsigned uimm8x2_in_0;
1881  unsigned uimm8x2_out_0;
1882  uimm8x2_out_0 = *valp;
1883  uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
1884  *valp = uimm8x2_in_0;
1885  return 0;
1886}
1887
1888static int
1889OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
1890{
1891  unsigned uimm8x4_out_0;
1892  unsigned uimm8x4_in_0;
1893  uimm8x4_in_0 = *valp & 0xff;
1894  uimm8x4_out_0 = uimm8x4_in_0 << 2;
1895  *valp = uimm8x4_out_0;
1896  return 0;
1897}
1898
1899static int
1900OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
1901{
1902  unsigned uimm8x4_in_0;
1903  unsigned uimm8x4_out_0;
1904  uimm8x4_out_0 = *valp;
1905  uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
1906  *valp = uimm8x4_in_0;
1907  return 0;
1908}
1909
1910static int
1911OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
1912{
1913  unsigned uimm4x16_out_0;
1914  unsigned uimm4x16_in_0;
1915  uimm4x16_in_0 = *valp & 0xf;
1916  uimm4x16_out_0 = uimm4x16_in_0 << 4;
1917  *valp = uimm4x16_out_0;
1918  return 0;
1919}
1920
1921static int
1922OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
1923{
1924  unsigned uimm4x16_in_0;
1925  unsigned uimm4x16_out_0;
1926  uimm4x16_out_0 = *valp;
1927  uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
1928  *valp = uimm4x16_in_0;
1929  return 0;
1930}
1931
1932static int
1933OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
1934{
1935  unsigned uimmrx4_out_0;
1936  unsigned uimmrx4_in_0;
1937  uimmrx4_in_0 = *valp & 0xf;
1938  uimmrx4_out_0 = uimmrx4_in_0 << 2;
1939  *valp = uimmrx4_out_0;
1940  return 0;
1941}
1942
1943static int
1944OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
1945{
1946  unsigned uimmrx4_in_0;
1947  unsigned uimmrx4_out_0;
1948  uimmrx4_out_0 = *valp;
1949  uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
1950  *valp = uimmrx4_in_0;
1951  return 0;
1952}
1953
1954static int
1955OperandSem_opnd_sem_simm8_decode (uint32 *valp)
1956{
1957  unsigned simm8_out_0;
1958  unsigned simm8_in_0;
1959  simm8_in_0 = *valp & 0xff;
1960  simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
1961  *valp = simm8_out_0;
1962  return 0;
1963}
1964
1965static int
1966OperandSem_opnd_sem_simm8_encode (uint32 *valp)
1967{
1968  unsigned simm8_in_0;
1969  unsigned simm8_out_0;
1970  simm8_out_0 = *valp;
1971  simm8_in_0 = (simm8_out_0 & 0xff);
1972  *valp = simm8_in_0;
1973  return 0;
1974}
1975
1976static int
1977OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
1978{
1979  unsigned simm8x256_out_0;
1980  unsigned simm8x256_in_0;
1981  simm8x256_in_0 = *valp & 0xff;
1982  simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
1983  *valp = simm8x256_out_0;
1984  return 0;
1985}
1986
1987static int
1988OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
1989{
1990  unsigned simm8x256_in_0;
1991  unsigned simm8x256_out_0;
1992  simm8x256_out_0 = *valp;
1993  simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
1994  *valp = simm8x256_in_0;
1995  return 0;
1996}
1997
1998static int
1999OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
2000{
2001  unsigned simm12b_out_0;
2002  unsigned simm12b_in_0;
2003  simm12b_in_0 = *valp & 0xfff;
2004  simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
2005  *valp = simm12b_out_0;
2006  return 0;
2007}
2008
2009static int
2010OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
2011{
2012  unsigned simm12b_in_0;
2013  unsigned simm12b_out_0;
2014  simm12b_out_0 = *valp;
2015  simm12b_in_0 = (simm12b_out_0 & 0xfff);
2016  *valp = simm12b_in_0;
2017  return 0;
2018}
2019
2020static int
2021OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
2022{
2023  unsigned msalp32_out_0;
2024  unsigned msalp32_in_0;
2025  msalp32_in_0 = *valp & 0x1f;
2026  msalp32_out_0 = 0x20 - msalp32_in_0;
2027  *valp = msalp32_out_0;
2028  return 0;
2029}
2030
2031static int
2032OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
2033{
2034  unsigned msalp32_in_0;
2035  unsigned msalp32_out_0;
2036  msalp32_out_0 = *valp;
2037  msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2038  *valp = msalp32_in_0;
2039  return 0;
2040}
2041
2042static int
2043OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
2044{
2045  unsigned op2p1_out_0;
2046  unsigned op2p1_in_0;
2047  op2p1_in_0 = *valp & 0xf;
2048  op2p1_out_0 = op2p1_in_0 + 0x1;
2049  *valp = op2p1_out_0;
2050  return 0;
2051}
2052
2053static int
2054OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
2055{
2056  unsigned op2p1_in_0;
2057  unsigned op2p1_out_0;
2058  op2p1_out_0 = *valp;
2059  op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2060  *valp = op2p1_in_0;
2061  return 0;
2062}
2063
2064static int
2065OperandSem_opnd_sem_label8_decode (uint32 *valp)
2066{
2067  unsigned label8_out_0;
2068  unsigned label8_in_0;
2069  label8_in_0 = *valp & 0xff;
2070  label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2071  *valp = label8_out_0;
2072  return 0;
2073}
2074
2075static int
2076OperandSem_opnd_sem_label8_encode (uint32 *valp)
2077{
2078  unsigned label8_in_0;
2079  unsigned label8_out_0;
2080  label8_out_0 = *valp;
2081  label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2082  *valp = label8_in_0;
2083  return 0;
2084}
2085
2086static int
2087OperandSem_opnd_sem_label12_decode (uint32 *valp)
2088{
2089  unsigned label12_out_0;
2090  unsigned label12_in_0;
2091  label12_in_0 = *valp & 0xfff;
2092  label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2093  *valp = label12_out_0;
2094  return 0;
2095}
2096
2097static int
2098OperandSem_opnd_sem_label12_encode (uint32 *valp)
2099{
2100  unsigned label12_in_0;
2101  unsigned label12_out_0;
2102  label12_out_0 = *valp;
2103  label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2104  *valp = label12_in_0;
2105  return 0;
2106}
2107
2108static int
2109OperandSem_opnd_sem_soffset_decode (uint32 *valp)
2110{
2111  unsigned soffset_out_0;
2112  unsigned soffset_in_0;
2113  soffset_in_0 = *valp & 0x3ffff;
2114  soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2115  *valp = soffset_out_0;
2116  return 0;
2117}
2118
2119static int
2120OperandSem_opnd_sem_soffset_encode (uint32 *valp)
2121{
2122  unsigned soffset_in_0;
2123  unsigned soffset_out_0;
2124  soffset_out_0 = *valp;
2125  soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2126  *valp = soffset_in_0;
2127  return 0;
2128}
2129
2130static int
2131OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
2132{
2133  unsigned uimm16x4_out_0;
2134  unsigned uimm16x4_in_0;
2135  uimm16x4_in_0 = *valp & 0xffff;
2136  uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2137  *valp = uimm16x4_out_0;
2138  return 0;
2139}
2140
2141static int
2142OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
2143{
2144  unsigned uimm16x4_in_0;
2145  unsigned uimm16x4_out_0;
2146  uimm16x4_out_0 = *valp;
2147  uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2148  *valp = uimm16x4_in_0;
2149  return 0;
2150}
2151
2152static int
2153OperandSem_opnd_sem_bbi_decode (uint32 *valp)
2154{
2155  unsigned bbi_out_0;
2156  unsigned bbi_in_0;
2157  bbi_in_0 = *valp & 0x1f;
2158  bbi_out_0 = (0 << 5) | bbi_in_0;
2159  *valp = bbi_out_0;
2160  return 0;
2161}
2162
2163static int
2164OperandSem_opnd_sem_bbi_encode (uint32 *valp)
2165{
2166  unsigned bbi_in_0;
2167  unsigned bbi_out_0;
2168  bbi_out_0 = *valp;
2169  bbi_in_0 = (bbi_out_0 & 0x1f);
2170  *valp = bbi_in_0;
2171  return 0;
2172}
2173
2174static int
2175OperandSem_opnd_sem_s_decode (uint32 *valp)
2176{
2177  unsigned s_out_0;
2178  unsigned s_in_0;
2179  s_in_0 = *valp & 0xf;
2180  s_out_0 = (0 << 4) | s_in_0;
2181  *valp = s_out_0;
2182  return 0;
2183}
2184
2185static int
2186OperandSem_opnd_sem_s_encode (uint32 *valp)
2187{
2188  unsigned s_in_0;
2189  unsigned s_out_0;
2190  s_out_0 = *valp;
2191  s_in_0 = (s_out_0 & 0xf);
2192  *valp = s_in_0;
2193  return 0;
2194}
2195
2196static int
2197OperandSem_opnd_sem_immt_decode (uint32 *valp)
2198{
2199  unsigned immt_out_0;
2200  unsigned immt_in_0;
2201  immt_in_0 = *valp & 0xf;
2202  immt_out_0 = immt_in_0;
2203  *valp = immt_out_0;
2204  return 0;
2205}
2206
2207static int
2208OperandSem_opnd_sem_immt_encode (uint32 *valp)
2209{
2210  unsigned immt_in_0;
2211  unsigned immt_out_0;
2212  immt_out_0 = *valp;
2213  immt_in_0 = immt_out_0 & 0xf;
2214  *valp = immt_in_0;
2215  return 0;
2216}
2217
2218static int
2219OperandSem_opnd_sem_tp7_decode (uint32 *valp)
2220{
2221  unsigned tp7_out_0;
2222  unsigned tp7_in_0;
2223  tp7_in_0 = *valp & 0xf;
2224  tp7_out_0 = tp7_in_0 + 0x7;
2225  *valp = tp7_out_0;
2226  return 0;
2227}
2228
2229static int
2230OperandSem_opnd_sem_tp7_encode (uint32 *valp)
2231{
2232  unsigned tp7_in_0;
2233  unsigned tp7_out_0;
2234  tp7_out_0 = *valp;
2235  tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2236  *valp = tp7_in_0;
2237  return 0;
2238}
2239
2240static int
2241OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
2242{
2243  unsigned xt_wbr15_label_out_0;
2244  unsigned xt_wbr15_label_in_0;
2245  xt_wbr15_label_in_0 = *valp & 0x7fff;
2246  xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2247  *valp = xt_wbr15_label_out_0;
2248  return 0;
2249}
2250
2251static int
2252OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
2253{
2254  unsigned xt_wbr15_label_in_0;
2255  unsigned xt_wbr15_label_out_0;
2256  xt_wbr15_label_out_0 = *valp;
2257  xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2258  *valp = xt_wbr15_label_in_0;
2259  return 0;
2260}
2261
2262static int
2263OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
2264{
2265  unsigned xt_wbr18_label_out_0;
2266  unsigned xt_wbr18_label_in_0;
2267  xt_wbr18_label_in_0 = *valp & 0x3ffff;
2268  xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2269  *valp = xt_wbr18_label_out_0;
2270  return 0;
2271}
2272
2273static int
2274OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
2275{
2276  unsigned xt_wbr18_label_in_0;
2277  unsigned xt_wbr18_label_out_0;
2278  xt_wbr18_label_out_0 = *valp;
2279  xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2280  *valp = xt_wbr18_label_in_0;
2281  return 0;
2282}
2283
2284static int
2285OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
2286{
2287  unsigned bitindex_out_0;
2288  unsigned bitindex_in_0;
2289  bitindex_in_0 = *valp & 0x1f;
2290  bitindex_out_0 = (0 << 5) | bitindex_in_0;
2291  *valp = bitindex_out_0;
2292  return 0;
2293}
2294
2295static int
2296OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
2297{
2298  unsigned bitindex_in_0;
2299  unsigned bitindex_out_0;
2300  bitindex_out_0 = *valp;
2301  bitindex_in_0 = (bitindex_out_0 & 0x1f);
2302  *valp = bitindex_in_0;
2303  return 0;
2304}
2305
2306static int
2307Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
2308{
2309  *valp -= (pc & ~0x3);
2310  return 0;
2311}
2312
2313static int
2314Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
2315{
2316  *valp += (pc & ~0x3);
2317  return 0;
2318}
2319
2320static int
2321Operand_uimm6_ator (uint32 *valp, uint32 pc)
2322{
2323  *valp -= pc;
2324  return 0;
2325}
2326
2327static int
2328Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2329{
2330  *valp += pc;
2331  return 0;
2332}
2333
2334static int
2335Operand_label8_ator (uint32 *valp, uint32 pc)
2336{
2337  *valp -= pc;
2338  return 0;
2339}
2340
2341static int
2342Operand_label8_rtoa (uint32 *valp, uint32 pc)
2343{
2344  *valp += pc;
2345  return 0;
2346}
2347
2348static int
2349Operand_label12_ator (uint32 *valp, uint32 pc)
2350{
2351  *valp -= pc;
2352  return 0;
2353}
2354
2355static int
2356Operand_label12_rtoa (uint32 *valp, uint32 pc)
2357{
2358  *valp += pc;
2359  return 0;
2360}
2361
2362static int
2363Operand_soffset_ator (uint32 *valp, uint32 pc)
2364{
2365  *valp -= pc;
2366  return 0;
2367}
2368
2369static int
2370Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2371{
2372  *valp += pc;
2373  return 0;
2374}
2375
2376static int
2377Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2378{
2379  *valp -= ((pc + 3) & ~0x3);
2380  return 0;
2381}
2382
2383static int
2384Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2385{
2386  *valp += ((pc + 3) & ~0x3);
2387  return 0;
2388}
2389
2390static int
2391Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2392{
2393  *valp -= pc;
2394  return 0;
2395}
2396
2397static int
2398Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2399{
2400  *valp += pc;
2401  return 0;
2402}
2403
2404static int
2405Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2406{
2407  *valp -= pc;
2408  return 0;
2409}
2410
2411static int
2412Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2413{
2414  *valp += pc;
2415  return 0;
2416}
2417
2418static xtensa_operand_internal operands[] = {
2419  { "soffsetx4", FIELD_offset, -1, 0,
2420    XTENSA_OPERAND_IS_PCRELATIVE,
2421    OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
2422    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2423  { "uimm12x8", FIELD_imm12, -1, 0,
2424    0,
2425    OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
2426    0, 0 },
2427  { "simm4", FIELD_mn, -1, 0,
2428    0,
2429    OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
2430    0, 0 },
2431  { "arr", FIELD_r, REGFILE_AR, 1,
2432    XTENSA_OPERAND_IS_REGISTER,
2433    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2434    0, 0 },
2435  { "ars", FIELD_s, REGFILE_AR, 1,
2436    XTENSA_OPERAND_IS_REGISTER,
2437    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2438    0, 0 },
2439  { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2440    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2441    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2442    0, 0 },
2443  { "art", FIELD_t, REGFILE_AR, 1,
2444    XTENSA_OPERAND_IS_REGISTER,
2445    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2446    0, 0 },
2447  { "ar0", FIELD__ar0, REGFILE_AR, 1,
2448    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2449    OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
2450    0, 0 },
2451  { "ar4", FIELD__ar4, REGFILE_AR, 1,
2452    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2453    OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
2454    0, 0 },
2455  { "ar8", FIELD__ar8, REGFILE_AR, 1,
2456    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2457    OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
2458    0, 0 },
2459  { "ar12", FIELD__ar12, REGFILE_AR, 1,
2460    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2461    OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
2462    0, 0 },
2463  { "ars_entry", FIELD_s, REGFILE_AR, 1,
2464    XTENSA_OPERAND_IS_REGISTER,
2465    OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
2466    0, 0 },
2467  { "immrx4", FIELD_r, -1, 0,
2468    0,
2469    OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
2470    0, 0 },
2471  { "lsi4x4", FIELD_r, -1, 0,
2472    0,
2473    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
2474    0, 0 },
2475  { "simm7", FIELD_imm7, -1, 0,
2476    0,
2477    OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
2478    0, 0 },
2479  { "uimm6", FIELD_imm6, -1, 0,
2480    XTENSA_OPERAND_IS_PCRELATIVE,
2481    OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
2482    Operand_uimm6_ator, Operand_uimm6_rtoa },
2483  { "ai4const", FIELD_t, -1, 0,
2484    0,
2485    OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
2486    0, 0 },
2487  { "b4const", FIELD_r, -1, 0,
2488    0,
2489    OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
2490    0, 0 },
2491  { "b4constu", FIELD_r, -1, 0,
2492    0,
2493    OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
2494    0, 0 },
2495  { "uimm8", FIELD_imm8, -1, 0,
2496    0,
2497    OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
2498    0, 0 },
2499  { "uimm8x2", FIELD_imm8, -1, 0,
2500    0,
2501    OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
2502    0, 0 },
2503  { "uimm8x4", FIELD_imm8, -1, 0,
2504    0,
2505    OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
2506    0, 0 },
2507  { "uimm4x16", FIELD_op2, -1, 0,
2508    0,
2509    OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
2510    0, 0 },
2511  { "uimmrx4", FIELD_r, -1, 0,
2512    0,
2513    OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
2514    0, 0 },
2515  { "simm8", FIELD_imm8, -1, 0,
2516    0,
2517    OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
2518    0, 0 },
2519  { "simm8x256", FIELD_imm8, -1, 0,
2520    0,
2521    OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
2522    0, 0 },
2523  { "simm12b", FIELD_imm12b, -1, 0,
2524    0,
2525    OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
2526    0, 0 },
2527  { "msalp32", FIELD_sal, -1, 0,
2528    0,
2529    OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
2530    0, 0 },
2531  { "op2p1", FIELD_op2, -1, 0,
2532    0,
2533    OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
2534    0, 0 },
2535  { "label8", FIELD_imm8, -1, 0,
2536    XTENSA_OPERAND_IS_PCRELATIVE,
2537    OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
2538    Operand_label8_ator, Operand_label8_rtoa },
2539  { "label12", FIELD_imm12, -1, 0,
2540    XTENSA_OPERAND_IS_PCRELATIVE,
2541    OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
2542    Operand_label12_ator, Operand_label12_rtoa },
2543  { "soffset", FIELD_offset, -1, 0,
2544    XTENSA_OPERAND_IS_PCRELATIVE,
2545    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
2546    Operand_soffset_ator, Operand_soffset_rtoa },
2547  { "uimm16x4", FIELD_imm16, -1, 0,
2548    XTENSA_OPERAND_IS_PCRELATIVE,
2549    OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
2550    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2551  { "bbi", FIELD_bbi, -1, 0,
2552    0,
2553    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2554    0, 0 },
2555  { "sae", FIELD_sae, -1, 0,
2556    0,
2557    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2558    0, 0 },
2559  { "sas", FIELD_sas, -1, 0,
2560    0,
2561    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2562    0, 0 },
2563  { "sargt", FIELD_sargt, -1, 0,
2564    0,
2565    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2566    0, 0 },
2567  { "s", FIELD_s, -1, 0,
2568    0,
2569    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
2570    0, 0 },
2571  { "immt", FIELD_t, -1, 0,
2572    0,
2573    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2574    0, 0 },
2575  { "imms", FIELD_s, -1, 0,
2576    0,
2577    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2578    0, 0 },
2579  { "tp7", FIELD_t, -1, 0,
2580    0,
2581    OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
2582    0, 0 },
2583  { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2584    XTENSA_OPERAND_IS_PCRELATIVE,
2585    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
2586    Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2587  { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2588    XTENSA_OPERAND_IS_PCRELATIVE,
2589    OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
2590    Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2591  { "bitindex", FIELD_bitindex, -1, 0,
2592    0,
2593    OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
2594    0, 0 },
2595  { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2596  { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2597  { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2598  { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2599  { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2600  { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2601  { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2602  { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2603  { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2604  { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2605  { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2606  { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2607  { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2608  { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2609  { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2610  { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2611  { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2612  { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2613  { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2614  { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2615  { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2616  { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2617  { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2618  { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2619  { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2620  { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2621  { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2622  { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2623  { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2624  { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2625  { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2626  { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
2627  { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
2628};
2629
2630enum xtensa_operand_id {
2631  OPERAND_soffsetx4,
2632  OPERAND_uimm12x8,
2633  OPERAND_simm4,
2634  OPERAND_arr,
2635  OPERAND_ars,
2636  OPERAND__ars_invisible,
2637  OPERAND_art,
2638  OPERAND_ar0,
2639  OPERAND_ar4,
2640  OPERAND_ar8,
2641  OPERAND_ar12,
2642  OPERAND_ars_entry,
2643  OPERAND_immrx4,
2644  OPERAND_lsi4x4,
2645  OPERAND_simm7,
2646  OPERAND_uimm6,
2647  OPERAND_ai4const,
2648  OPERAND_b4const,
2649  OPERAND_b4constu,
2650  OPERAND_uimm8,
2651  OPERAND_uimm8x2,
2652  OPERAND_uimm8x4,
2653  OPERAND_uimm4x16,
2654  OPERAND_uimmrx4,
2655  OPERAND_simm8,
2656  OPERAND_simm8x256,
2657  OPERAND_simm12b,
2658  OPERAND_msalp32,
2659  OPERAND_op2p1,
2660  OPERAND_label8,
2661  OPERAND_label12,
2662  OPERAND_soffset,
2663  OPERAND_uimm16x4,
2664  OPERAND_bbi,
2665  OPERAND_sae,
2666  OPERAND_sas,
2667  OPERAND_sargt,
2668  OPERAND_s,
2669  OPERAND_immt,
2670  OPERAND_imms,
2671  OPERAND_tp7,
2672  OPERAND_xt_wbr15_label,
2673  OPERAND_xt_wbr18_label,
2674  OPERAND_bitindex,
2675  OPERAND_t,
2676  OPERAND_bbi4,
2677  OPERAND_imm12,
2678  OPERAND_imm8,
2679  OPERAND_imm12b,
2680  OPERAND_imm16,
2681  OPERAND_m,
2682  OPERAND_n,
2683  OPERAND_offset,
2684  OPERAND_op0,
2685  OPERAND_op1,
2686  OPERAND_op2,
2687  OPERAND_r,
2688  OPERAND_sa4,
2689  OPERAND_sae4,
2690  OPERAND_sal,
2691  OPERAND_sas4,
2692  OPERAND_sr,
2693  OPERAND_st,
2694  OPERAND_thi3,
2695  OPERAND_imm4,
2696  OPERAND_mn,
2697  OPERAND_i,
2698  OPERAND_imm6lo,
2699  OPERAND_imm6hi,
2700  OPERAND_imm7lo,
2701  OPERAND_imm7hi,
2702  OPERAND_z,
2703  OPERAND_imm6,
2704  OPERAND_imm7,
2705  OPERAND_xt_wbr15_imm,
2706  OPERAND_xt_wbr18_imm,
2707  OPERAND_s3to1
2708};
2709
2710
2711/* Iclass table.  */
2712
2713static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2714  { { STATE_PSEXCM }, 'o' },
2715  { { STATE_EPC1 }, 'i' }
2716};
2717
2718static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2719  { { STATE_DEPC }, 'i' }
2720};
2721
2722static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2723  { { OPERAND_soffsetx4 }, 'i' },
2724  { { OPERAND_ar12 }, 'o' }
2725};
2726
2727static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2728  { { STATE_PSCALLINC }, 'o' }
2729};
2730
2731static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2732  { { OPERAND_soffsetx4 }, 'i' },
2733  { { OPERAND_ar8 }, 'o' }
2734};
2735
2736static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2737  { { STATE_PSCALLINC }, 'o' }
2738};
2739
2740static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2741  { { OPERAND_soffsetx4 }, 'i' },
2742  { { OPERAND_ar4 }, 'o' }
2743};
2744
2745static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2746  { { STATE_PSCALLINC }, 'o' }
2747};
2748
2749static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2750  { { OPERAND_ars }, 'i' },
2751  { { OPERAND_ar12 }, 'o' }
2752};
2753
2754static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2755  { { STATE_PSCALLINC }, 'o' }
2756};
2757
2758static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2759  { { OPERAND_ars }, 'i' },
2760  { { OPERAND_ar8 }, 'o' }
2761};
2762
2763static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2764  { { STATE_PSCALLINC }, 'o' }
2765};
2766
2767static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2768  { { OPERAND_ars }, 'i' },
2769  { { OPERAND_ar4 }, 'o' }
2770};
2771
2772static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2773  { { STATE_PSCALLINC }, 'o' }
2774};
2775
2776static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2777  { { OPERAND_ars_entry }, 's' },
2778  { { OPERAND_ars }, 'i' },
2779  { { OPERAND_uimm12x8 }, 'i' }
2780};
2781
2782static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2783  { { STATE_PSCALLINC }, 'i' },
2784  { { STATE_PSEXCM }, 'i' },
2785  { { STATE_PSWOE }, 'i' },
2786  { { STATE_WindowBase }, 'm' },
2787  { { STATE_WindowStart }, 'm' }
2788};
2789
2790static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2791  { { OPERAND_art }, 'o' },
2792  { { OPERAND_ars }, 'i' }
2793};
2794
2795static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2796  { { STATE_WindowBase }, 'i' },
2797  { { STATE_WindowStart }, 'i' }
2798};
2799
2800static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2801  { { OPERAND_simm4 }, 'i' }
2802};
2803
2804static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2805  { { STATE_WindowBase }, 'm' }
2806};
2807
2808static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2809  { { OPERAND__ars_invisible }, 'i' }
2810};
2811
2812static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2813  { { STATE_WindowBase }, 'm' },
2814  { { STATE_WindowStart }, 'm' },
2815  { { STATE_PSCALLINC }, 'o' },
2816  { { STATE_PSEXCM }, 'i' },
2817  { { STATE_PSWOE }, 'i' }
2818};
2819
2820static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2821  { { STATE_EPC1 }, 'i' },
2822  { { STATE_PSEXCM }, 'o' },
2823  { { STATE_WindowBase }, 'm' },
2824  { { STATE_WindowStart }, 'm' },
2825  { { STATE_PSOWB }, 'i' }
2826};
2827
2828static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2829  { { OPERAND_art }, 'o' },
2830  { { OPERAND_ars }, 'i' },
2831  { { OPERAND_immrx4 }, 'i' }
2832};
2833
2834static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2835  { { OPERAND_art }, 'i' },
2836  { { OPERAND_ars }, 'i' },
2837  { { OPERAND_immrx4 }, 'i' }
2838};
2839
2840static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2841  { { OPERAND_art }, 'o' }
2842};
2843
2844static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2845  { { STATE_WindowBase }, 'i' }
2846};
2847
2848static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2849  { { OPERAND_art }, 'i' }
2850};
2851
2852static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2853  { { STATE_WindowBase }, 'o' }
2854};
2855
2856static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2857  { { OPERAND_art }, 'm' }
2858};
2859
2860static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2861  { { STATE_WindowBase }, 'm' }
2862};
2863
2864static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2865  { { OPERAND_art }, 'o' }
2866};
2867
2868static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2869  { { STATE_WindowStart }, 'i' }
2870};
2871
2872static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2873  { { OPERAND_art }, 'i' }
2874};
2875
2876static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2877  { { STATE_WindowStart }, 'o' }
2878};
2879
2880static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2881  { { OPERAND_art }, 'm' }
2882};
2883
2884static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2885  { { STATE_WindowStart }, 'm' }
2886};
2887
2888static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2889  { { OPERAND_arr }, 'o' },
2890  { { OPERAND_ars }, 'i' },
2891  { { OPERAND_art }, 'i' }
2892};
2893
2894static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2895  { { OPERAND_arr }, 'o' },
2896  { { OPERAND_ars }, 'i' },
2897  { { OPERAND_ai4const }, 'i' }
2898};
2899
2900static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2901  { { OPERAND_ars }, 'i' },
2902  { { OPERAND_uimm6 }, 'i' }
2903};
2904
2905static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2906  { { OPERAND_art }, 'o' },
2907  { { OPERAND_ars }, 'i' },
2908  { { OPERAND_lsi4x4 }, 'i' }
2909};
2910
2911static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2912  { { OPERAND_art }, 'o' },
2913  { { OPERAND_ars }, 'i' }
2914};
2915
2916static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2917  { { OPERAND_ars }, 'o' },
2918  { { OPERAND_simm7 }, 'i' }
2919};
2920
2921static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2922  { { OPERAND__ars_invisible }, 'i' }
2923};
2924
2925static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2926  { { OPERAND_art }, 'i' },
2927  { { OPERAND_ars }, 'i' },
2928  { { OPERAND_lsi4x4 }, 'i' }
2929};
2930
2931static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2932  { { OPERAND_art }, 'o' },
2933  { { OPERAND_ars }, 'i' },
2934  { { OPERAND_simm8 }, 'i' }
2935};
2936
2937static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2938  { { OPERAND_art }, 'o' },
2939  { { OPERAND_ars }, 'i' },
2940  { { OPERAND_simm8x256 }, 'i' }
2941};
2942
2943static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2944  { { OPERAND_arr }, 'o' },
2945  { { OPERAND_ars }, 'i' },
2946  { { OPERAND_art }, 'i' }
2947};
2948
2949static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2950  { { OPERAND_arr }, 'o' },
2951  { { OPERAND_ars }, 'i' },
2952  { { OPERAND_art }, 'i' }
2953};
2954
2955static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2956  { { OPERAND_ars }, 'i' },
2957  { { OPERAND_b4const }, 'i' },
2958  { { OPERAND_label8 }, 'i' }
2959};
2960
2961static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2962  { { OPERAND_ars }, 'i' },
2963  { { OPERAND_bbi }, 'i' },
2964  { { OPERAND_label8 }, 'i' }
2965};
2966
2967static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2968  { { OPERAND_ars }, 'i' },
2969  { { OPERAND_b4constu }, 'i' },
2970  { { OPERAND_label8 }, 'i' }
2971};
2972
2973static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2974  { { OPERAND_ars }, 'i' },
2975  { { OPERAND_art }, 'i' },
2976  { { OPERAND_label8 }, 'i' }
2977};
2978
2979static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2980  { { OPERAND_ars }, 'i' },
2981  { { OPERAND_label12 }, 'i' }
2982};
2983
2984static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2985  { { OPERAND_soffsetx4 }, 'i' },
2986  { { OPERAND_ar0 }, 'o' }
2987};
2988
2989static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2990  { { OPERAND_ars }, 'i' },
2991  { { OPERAND_ar0 }, 'o' }
2992};
2993
2994static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2995  { { OPERAND_arr }, 'o' },
2996  { { OPERAND_art }, 'i' },
2997  { { OPERAND_sae }, 'i' },
2998  { { OPERAND_op2p1 }, 'i' }
2999};
3000
3001static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3002  { { OPERAND_soffset }, 'i' }
3003};
3004
3005static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3006  { { OPERAND_ars }, 'i' }
3007};
3008
3009static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3010  { { OPERAND_art }, 'o' },
3011  { { OPERAND_ars }, 'i' },
3012  { { OPERAND_uimm8x2 }, 'i' }
3013};
3014
3015static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3016  { { OPERAND_art }, 'o' },
3017  { { OPERAND_ars }, 'i' },
3018  { { OPERAND_uimm8x2 }, 'i' }
3019};
3020
3021static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3022  { { OPERAND_art }, 'o' },
3023  { { OPERAND_ars }, 'i' },
3024  { { OPERAND_uimm8x4 }, 'i' }
3025};
3026
3027static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3028  { { OPERAND_art }, 'o' },
3029  { { OPERAND_uimm16x4 }, 'i' }
3030};
3031
3032static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3033  { { OPERAND_art }, 'o' },
3034  { { OPERAND_ars }, 'i' },
3035  { { OPERAND_uimm8 }, 'i' }
3036};
3037
3038static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3039  { { OPERAND_art }, 'o' },
3040  { { OPERAND_simm12b }, 'i' }
3041};
3042
3043static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3044  { { OPERAND_arr }, 'm' },
3045  { { OPERAND_ars }, 'i' },
3046  { { OPERAND_art }, 'i' }
3047};
3048
3049static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3050  { { OPERAND_arr }, 'o' },
3051  { { OPERAND_art }, 'i' }
3052};
3053
3054static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3055  { { OPERAND__ars_invisible }, 'i' }
3056};
3057
3058static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3059  { { OPERAND_art }, 'i' },
3060  { { OPERAND_ars }, 'i' },
3061  { { OPERAND_uimm8x2 }, 'i' }
3062};
3063
3064static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3065  { { OPERAND_art }, 'i' },
3066  { { OPERAND_ars }, 'i' },
3067  { { OPERAND_uimm8x4 }, 'i' }
3068};
3069
3070static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3071  { { OPERAND_art }, 'i' },
3072  { { OPERAND_ars }, 'i' },
3073  { { OPERAND_uimmrx4 }, 'i' }
3074};
3075
3076static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3077  { { OPERAND_art }, 'i' },
3078  { { OPERAND_ars }, 'i' },
3079  { { OPERAND_uimm8 }, 'i' }
3080};
3081
3082static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3083  { { OPERAND_ars }, 'i' }
3084};
3085
3086static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3087  { { STATE_SAR }, 'o' }
3088};
3089
3090static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3091  { { OPERAND_sas }, 'i' }
3092};
3093
3094static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3095  { { STATE_SAR }, 'o' }
3096};
3097
3098static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3099  { { OPERAND_arr }, 'o' },
3100  { { OPERAND_ars }, 'i' }
3101};
3102
3103static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3104  { { STATE_SAR }, 'i' }
3105};
3106
3107static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3108  { { OPERAND_arr }, 'o' },
3109  { { OPERAND_ars }, 'i' },
3110  { { OPERAND_art }, 'i' }
3111};
3112
3113static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3114  { { STATE_SAR }, 'i' }
3115};
3116
3117static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3118  { { OPERAND_arr }, 'o' },
3119  { { OPERAND_art }, 'i' }
3120};
3121
3122static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3123  { { STATE_SAR }, 'i' }
3124};
3125
3126static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3127  { { OPERAND_arr }, 'o' },
3128  { { OPERAND_ars }, 'i' },
3129  { { OPERAND_msalp32 }, 'i' }
3130};
3131
3132static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3133  { { OPERAND_arr }, 'o' },
3134  { { OPERAND_art }, 'i' },
3135  { { OPERAND_sargt }, 'i' }
3136};
3137
3138static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3139  { { OPERAND_arr }, 'o' },
3140  { { OPERAND_art }, 'i' },
3141  { { OPERAND_s }, 'i' }
3142};
3143
3144static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3145  { { STATE_XTSYNC }, 'i' }
3146};
3147
3148static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3149  { { OPERAND_art }, 'o' },
3150  { { OPERAND_s }, 'i' }
3151};
3152
3153static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3154  { { STATE_PSWOE }, 'i' },
3155  { { STATE_PSCALLINC }, 'i' },
3156  { { STATE_PSOWB }, 'i' },
3157  { { STATE_PSUM }, 'i' },
3158  { { STATE_PSEXCM }, 'i' },
3159  { { STATE_PSINTLEVEL }, 'm' }
3160};
3161
3162static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3163  { { OPERAND_art }, 'o' }
3164};
3165
3166static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3167  { { STATE_SAR }, 'i' }
3168};
3169
3170static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3171  { { OPERAND_art }, 'i' }
3172};
3173
3174static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3175  { { STATE_SAR }, 'o' },
3176  { { STATE_XTSYNC }, 'o' }
3177};
3178
3179static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3180  { { OPERAND_art }, 'm' }
3181};
3182
3183static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3184  { { STATE_SAR }, 'm' }
3185};
3186
3187static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3188  { { OPERAND_art }, 'o' }
3189};
3190
3191static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3192  { { OPERAND_art }, 'i' }
3193};
3194
3195static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3196  { { OPERAND_art }, 'm' }
3197};
3198
3199static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3200  { { OPERAND_art }, 'o' }
3201};
3202
3203static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3204  { { OPERAND_art }, 'i' }
3205};
3206
3207static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3208  { { OPERAND_art }, 'm' }
3209};
3210
3211static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3212  { { OPERAND_art }, 'o' }
3213};
3214
3215static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3216  { { OPERAND_art }, 'i' }
3217};
3218
3219static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3220  { { OPERAND_art }, 'o' }
3221};
3222
3223static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3224  { { OPERAND_art }, 'o' }
3225};
3226
3227static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3228  { { STATE_PSWOE }, 'i' },
3229  { { STATE_PSCALLINC }, 'i' },
3230  { { STATE_PSOWB }, 'i' },
3231  { { STATE_PSUM }, 'i' },
3232  { { STATE_PSEXCM }, 'i' },
3233  { { STATE_PSINTLEVEL }, 'i' }
3234};
3235
3236static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3237  { { OPERAND_art }, 'i' }
3238};
3239
3240static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3241  { { STATE_PSWOE }, 'o' },
3242  { { STATE_PSCALLINC }, 'o' },
3243  { { STATE_PSOWB }, 'o' },
3244  { { STATE_PSUM }, 'o' },
3245  { { STATE_PSEXCM }, 'o' },
3246  { { STATE_PSINTLEVEL }, 'o' }
3247};
3248
3249static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3250  { { OPERAND_art }, 'm' }
3251};
3252
3253static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3254  { { STATE_PSWOE }, 'm' },
3255  { { STATE_PSCALLINC }, 'm' },
3256  { { STATE_PSOWB }, 'm' },
3257  { { STATE_PSUM }, 'm' },
3258  { { STATE_PSEXCM }, 'm' },
3259  { { STATE_PSINTLEVEL }, 'm' }
3260};
3261
3262static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3263  { { OPERAND_art }, 'o' }
3264};
3265
3266static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3267  { { STATE_EPC1 }, 'i' }
3268};
3269
3270static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3271  { { OPERAND_art }, 'i' }
3272};
3273
3274static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3275  { { STATE_EPC1 }, 'o' }
3276};
3277
3278static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3279  { { OPERAND_art }, 'm' }
3280};
3281
3282static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3283  { { STATE_EPC1 }, 'm' }
3284};
3285
3286static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3287  { { OPERAND_art }, 'o' }
3288};
3289
3290static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3291  { { STATE_EXCSAVE1 }, 'i' }
3292};
3293
3294static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3295  { { OPERAND_art }, 'i' }
3296};
3297
3298static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3299  { { STATE_EXCSAVE1 }, 'o' }
3300};
3301
3302static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3303  { { OPERAND_art }, 'm' }
3304};
3305
3306static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3307  { { STATE_EXCSAVE1 }, 'm' }
3308};
3309
3310static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3311  { { OPERAND_art }, 'o' }
3312};
3313
3314static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3315  { { STATE_EPC2 }, 'i' }
3316};
3317
3318static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3319  { { OPERAND_art }, 'i' }
3320};
3321
3322static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3323  { { STATE_EPC2 }, 'o' }
3324};
3325
3326static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3327  { { OPERAND_art }, 'm' }
3328};
3329
3330static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3331  { { STATE_EPC2 }, 'm' }
3332};
3333
3334static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3335  { { OPERAND_art }, 'o' }
3336};
3337
3338static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3339  { { STATE_EXCSAVE2 }, 'i' }
3340};
3341
3342static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3343  { { OPERAND_art }, 'i' }
3344};
3345
3346static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3347  { { STATE_EXCSAVE2 }, 'o' }
3348};
3349
3350static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3351  { { OPERAND_art }, 'm' }
3352};
3353
3354static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3355  { { STATE_EXCSAVE2 }, 'm' }
3356};
3357
3358static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3359  { { OPERAND_art }, 'o' }
3360};
3361
3362static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3363  { { STATE_EPC3 }, 'i' }
3364};
3365
3366static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3367  { { OPERAND_art }, 'i' }
3368};
3369
3370static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3371  { { STATE_EPC3 }, 'o' }
3372};
3373
3374static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3375  { { OPERAND_art }, 'm' }
3376};
3377
3378static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3379  { { STATE_EPC3 }, 'm' }
3380};
3381
3382static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3383  { { OPERAND_art }, 'o' }
3384};
3385
3386static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3387  { { STATE_EXCSAVE3 }, 'i' }
3388};
3389
3390static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3391  { { OPERAND_art }, 'i' }
3392};
3393
3394static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3395  { { STATE_EXCSAVE3 }, 'o' }
3396};
3397
3398static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3399  { { OPERAND_art }, 'm' }
3400};
3401
3402static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3403  { { STATE_EXCSAVE3 }, 'm' }
3404};
3405
3406static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3407  { { OPERAND_art }, 'o' }
3408};
3409
3410static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3411  { { STATE_EPC4 }, 'i' }
3412};
3413
3414static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3415  { { OPERAND_art }, 'i' }
3416};
3417
3418static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3419  { { STATE_EPC4 }, 'o' }
3420};
3421
3422static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3423  { { OPERAND_art }, 'm' }
3424};
3425
3426static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3427  { { STATE_EPC4 }, 'm' }
3428};
3429
3430static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3431  { { OPERAND_art }, 'o' }
3432};
3433
3434static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3435  { { STATE_EXCSAVE4 }, 'i' }
3436};
3437
3438static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3439  { { OPERAND_art }, 'i' }
3440};
3441
3442static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3443  { { STATE_EXCSAVE4 }, 'o' }
3444};
3445
3446static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3447  { { OPERAND_art }, 'm' }
3448};
3449
3450static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3451  { { STATE_EXCSAVE4 }, 'm' }
3452};
3453
3454static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3455  { { OPERAND_art }, 'o' }
3456};
3457
3458static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3459  { { STATE_EPC5 }, 'i' }
3460};
3461
3462static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3463  { { OPERAND_art }, 'i' }
3464};
3465
3466static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3467  { { STATE_EPC5 }, 'o' }
3468};
3469
3470static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3471  { { OPERAND_art }, 'm' }
3472};
3473
3474static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3475  { { STATE_EPC5 }, 'm' }
3476};
3477
3478static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3479  { { OPERAND_art }, 'o' }
3480};
3481
3482static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3483  { { STATE_EXCSAVE5 }, 'i' }
3484};
3485
3486static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3487  { { OPERAND_art }, 'i' }
3488};
3489
3490static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3491  { { STATE_EXCSAVE5 }, 'o' }
3492};
3493
3494static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3495  { { OPERAND_art }, 'm' }
3496};
3497
3498static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3499  { { STATE_EXCSAVE5 }, 'm' }
3500};
3501
3502static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3503  { { OPERAND_art }, 'o' }
3504};
3505
3506static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3507  { { STATE_EPC6 }, 'i' }
3508};
3509
3510static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
3511  { { OPERAND_art }, 'i' }
3512};
3513
3514static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
3515  { { STATE_EPC6 }, 'o' }
3516};
3517
3518static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
3519  { { OPERAND_art }, 'm' }
3520};
3521
3522static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
3523  { { STATE_EPC6 }, 'm' }
3524};
3525
3526static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
3527  { { OPERAND_art }, 'o' }
3528};
3529
3530static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
3531  { { STATE_EXCSAVE6 }, 'i' }
3532};
3533
3534static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
3535  { { OPERAND_art }, 'i' }
3536};
3537
3538static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
3539  { { STATE_EXCSAVE6 }, 'o' }
3540};
3541
3542static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
3543  { { OPERAND_art }, 'm' }
3544};
3545
3546static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
3547  { { STATE_EXCSAVE6 }, 'm' }
3548};
3549
3550static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
3551  { { OPERAND_art }, 'o' }
3552};
3553
3554static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
3555  { { STATE_EPC7 }, 'i' }
3556};
3557
3558static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
3559  { { OPERAND_art }, 'i' }
3560};
3561
3562static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
3563  { { STATE_EPC7 }, 'o' }
3564};
3565
3566static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
3567  { { OPERAND_art }, 'm' }
3568};
3569
3570static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
3571  { { STATE_EPC7 }, 'm' }
3572};
3573
3574static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
3575  { { OPERAND_art }, 'o' }
3576};
3577
3578static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
3579  { { STATE_EXCSAVE7 }, 'i' }
3580};
3581
3582static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
3583  { { OPERAND_art }, 'i' }
3584};
3585
3586static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
3587  { { STATE_EXCSAVE7 }, 'o' }
3588};
3589
3590static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
3591  { { OPERAND_art }, 'm' }
3592};
3593
3594static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
3595  { { STATE_EXCSAVE7 }, 'm' }
3596};
3597
3598static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3599  { { OPERAND_art }, 'o' }
3600};
3601
3602static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3603  { { STATE_EPS2 }, 'i' }
3604};
3605
3606static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3607  { { OPERAND_art }, 'i' }
3608};
3609
3610static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3611  { { STATE_EPS2 }, 'o' }
3612};
3613
3614static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3615  { { OPERAND_art }, 'm' }
3616};
3617
3618static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3619  { { STATE_EPS2 }, 'm' }
3620};
3621
3622static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3623  { { OPERAND_art }, 'o' }
3624};
3625
3626static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3627  { { STATE_EPS3 }, 'i' }
3628};
3629
3630static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3631  { { OPERAND_art }, 'i' }
3632};
3633
3634static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3635  { { STATE_EPS3 }, 'o' }
3636};
3637
3638static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3639  { { OPERAND_art }, 'm' }
3640};
3641
3642static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3643  { { STATE_EPS3 }, 'm' }
3644};
3645
3646static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3647  { { OPERAND_art }, 'o' }
3648};
3649
3650static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3651  { { STATE_EPS4 }, 'i' }
3652};
3653
3654static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3655  { { OPERAND_art }, 'i' }
3656};
3657
3658static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3659  { { STATE_EPS4 }, 'o' }
3660};
3661
3662static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3663  { { OPERAND_art }, 'm' }
3664};
3665
3666static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3667  { { STATE_EPS4 }, 'm' }
3668};
3669
3670static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
3671  { { OPERAND_art }, 'o' }
3672};
3673
3674static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
3675  { { STATE_EPS5 }, 'i' }
3676};
3677
3678static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
3679  { { OPERAND_art }, 'i' }
3680};
3681
3682static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
3683  { { STATE_EPS5 }, 'o' }
3684};
3685
3686static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
3687  { { OPERAND_art }, 'm' }
3688};
3689
3690static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
3691  { { STATE_EPS5 }, 'm' }
3692};
3693
3694static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
3695  { { OPERAND_art }, 'o' }
3696};
3697
3698static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
3699  { { STATE_EPS6 }, 'i' }
3700};
3701
3702static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
3703  { { OPERAND_art }, 'i' }
3704};
3705
3706static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
3707  { { STATE_EPS6 }, 'o' }
3708};
3709
3710static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
3711  { { OPERAND_art }, 'm' }
3712};
3713
3714static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
3715  { { STATE_EPS6 }, 'm' }
3716};
3717
3718static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
3719  { { OPERAND_art }, 'o' }
3720};
3721
3722static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
3723  { { STATE_EPS7 }, 'i' }
3724};
3725
3726static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
3727  { { OPERAND_art }, 'i' }
3728};
3729
3730static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
3731  { { STATE_EPS7 }, 'o' }
3732};
3733
3734static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
3735  { { OPERAND_art }, 'm' }
3736};
3737
3738static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
3739  { { STATE_EPS7 }, 'm' }
3740};
3741
3742static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3743  { { OPERAND_art }, 'o' }
3744};
3745
3746static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3747  { { STATE_EXCVADDR }, 'i' }
3748};
3749
3750static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3751  { { OPERAND_art }, 'i' }
3752};
3753
3754static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3755  { { STATE_EXCVADDR }, 'o' }
3756};
3757
3758static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3759  { { OPERAND_art }, 'm' }
3760};
3761
3762static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3763  { { STATE_EXCVADDR }, 'm' }
3764};
3765
3766static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3767  { { OPERAND_art }, 'o' }
3768};
3769
3770static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3771  { { STATE_DEPC }, 'i' }
3772};
3773
3774static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3775  { { OPERAND_art }, 'i' }
3776};
3777
3778static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3779  { { STATE_DEPC }, 'o' }
3780};
3781
3782static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3783  { { OPERAND_art }, 'm' }
3784};
3785
3786static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3787  { { STATE_DEPC }, 'm' }
3788};
3789
3790static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3791  { { OPERAND_art }, 'o' }
3792};
3793
3794static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3795  { { STATE_EXCCAUSE }, 'i' },
3796  { { STATE_XTSYNC }, 'i' }
3797};
3798
3799static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3800  { { OPERAND_art }, 'i' }
3801};
3802
3803static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3804  { { STATE_EXCCAUSE }, 'o' }
3805};
3806
3807static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3808  { { OPERAND_art }, 'm' }
3809};
3810
3811static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3812  { { STATE_EXCCAUSE }, 'm' }
3813};
3814
3815static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3816  { { OPERAND_art }, 'o' }
3817};
3818
3819static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3820  { { STATE_MISC0 }, 'i' }
3821};
3822
3823static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3824  { { OPERAND_art }, 'i' }
3825};
3826
3827static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3828  { { STATE_MISC0 }, 'o' }
3829};
3830
3831static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3832  { { OPERAND_art }, 'm' }
3833};
3834
3835static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3836  { { STATE_MISC0 }, 'm' }
3837};
3838
3839static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3840  { { OPERAND_art }, 'o' }
3841};
3842
3843static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3844  { { STATE_MISC1 }, 'i' }
3845};
3846
3847static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3848  { { OPERAND_art }, 'i' }
3849};
3850
3851static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3852  { { STATE_MISC1 }, 'o' }
3853};
3854
3855static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3856  { { OPERAND_art }, 'm' }
3857};
3858
3859static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3860  { { STATE_MISC1 }, 'm' }
3861};
3862
3863static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3864  { { OPERAND_art }, 'o' }
3865};
3866
3867static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
3868  { { OPERAND_art }, 'o' }
3869};
3870
3871static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
3872  { { STATE_VECBASE }, 'i' }
3873};
3874
3875static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
3876  { { OPERAND_art }, 'i' }
3877};
3878
3879static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
3880  { { STATE_VECBASE }, 'o' }
3881};
3882
3883static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
3884  { { OPERAND_art }, 'm' }
3885};
3886
3887static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
3888  { { STATE_VECBASE }, 'm' }
3889};
3890
3891static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
3892  { { OPERAND_arr }, 'o' },
3893  { { OPERAND_ars }, 'i' },
3894  { { OPERAND_art }, 'i' }
3895};
3896
3897static xtensa_arg_internal Iclass_xt_mul16_args[] = {
3898  { { OPERAND_arr }, 'o' },
3899  { { OPERAND_ars }, 'i' },
3900  { { OPERAND_art }, 'i' }
3901};
3902
3903static xtensa_arg_internal Iclass_xt_mul32_args[] = {
3904  { { OPERAND_arr }, 'o' },
3905  { { OPERAND_ars }, 'i' },
3906  { { OPERAND_art }, 'i' }
3907};
3908
3909static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3910  { { OPERAND_s }, 'i' }
3911};
3912
3913static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3914  { { STATE_PSWOE }, 'o' },
3915  { { STATE_PSCALLINC }, 'o' },
3916  { { STATE_PSOWB }, 'o' },
3917  { { STATE_PSUM }, 'o' },
3918  { { STATE_PSEXCM }, 'o' },
3919  { { STATE_PSINTLEVEL }, 'o' },
3920  { { STATE_EPC1 }, 'i' },
3921  { { STATE_EPC2 }, 'i' },
3922  { { STATE_EPC3 }, 'i' },
3923  { { STATE_EPC4 }, 'i' },
3924  { { STATE_EPC5 }, 'i' },
3925  { { STATE_EPC6 }, 'i' },
3926  { { STATE_EPC7 }, 'i' },
3927  { { STATE_EPS2 }, 'i' },
3928  { { STATE_EPS3 }, 'i' },
3929  { { STATE_EPS4 }, 'i' },
3930  { { STATE_EPS5 }, 'i' },
3931  { { STATE_EPS6 }, 'i' },
3932  { { STATE_EPS7 }, 'i' },
3933  { { STATE_InOCDMode }, 'm' }
3934};
3935
3936static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3937  { { OPERAND_s }, 'i' }
3938};
3939
3940static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3941  { { STATE_PSINTLEVEL }, 'o' }
3942};
3943
3944static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3945  { { OPERAND_art }, 'o' }
3946};
3947
3948static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3949  { { STATE_INTERRUPT }, 'i' }
3950};
3951
3952static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3953  { { OPERAND_art }, 'i' }
3954};
3955
3956static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3957  { { STATE_XTSYNC }, 'o' },
3958  { { STATE_INTERRUPT }, 'm' }
3959};
3960
3961static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
3962  { { OPERAND_art }, 'i' }
3963};
3964
3965static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
3966  { { STATE_XTSYNC }, 'o' },
3967  { { STATE_INTERRUPT }, 'm' }
3968};
3969
3970static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
3971  { { OPERAND_art }, 'o' }
3972};
3973
3974static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
3975  { { STATE_INTENABLE }, 'i' }
3976};
3977
3978static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
3979  { { OPERAND_art }, 'i' }
3980};
3981
3982static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
3983  { { STATE_INTENABLE }, 'o' }
3984};
3985
3986static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
3987  { { OPERAND_art }, 'm' }
3988};
3989
3990static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
3991  { { STATE_INTENABLE }, 'm' }
3992};
3993
3994static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
3995  { { OPERAND_imms }, 'i' },
3996  { { OPERAND_immt }, 'i' }
3997};
3998
3999static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4000  { { STATE_PSEXCM }, 'i' },
4001  { { STATE_PSINTLEVEL }, 'i' }
4002};
4003
4004static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4005  { { OPERAND_imms }, 'i' }
4006};
4007
4008static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4009  { { STATE_PSEXCM }, 'i' },
4010  { { STATE_PSINTLEVEL }, 'i' }
4011};
4012
4013static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4014  { { OPERAND_art }, 'o' }
4015};
4016
4017static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4018  { { STATE_DBREAKA0 }, 'i' }
4019};
4020
4021static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4022  { { OPERAND_art }, 'i' }
4023};
4024
4025static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4026  { { STATE_DBREAKA0 }, 'o' },
4027  { { STATE_XTSYNC }, 'o' }
4028};
4029
4030static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4031  { { OPERAND_art }, 'm' }
4032};
4033
4034static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4035  { { STATE_DBREAKA0 }, 'm' },
4036  { { STATE_XTSYNC }, 'o' }
4037};
4038
4039static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4040  { { OPERAND_art }, 'o' }
4041};
4042
4043static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4044  { { STATE_DBREAKC0 }, 'i' }
4045};
4046
4047static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4048  { { OPERAND_art }, 'i' }
4049};
4050
4051static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4052  { { STATE_DBREAKC0 }, 'o' },
4053  { { STATE_XTSYNC }, 'o' }
4054};
4055
4056static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4057  { { OPERAND_art }, 'm' }
4058};
4059
4060static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4061  { { STATE_DBREAKC0 }, 'm' },
4062  { { STATE_XTSYNC }, 'o' }
4063};
4064
4065static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4066  { { OPERAND_art }, 'o' }
4067};
4068
4069static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4070  { { STATE_DBREAKA1 }, 'i' }
4071};
4072
4073static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4074  { { OPERAND_art }, 'i' }
4075};
4076
4077static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4078  { { STATE_DBREAKA1 }, 'o' },
4079  { { STATE_XTSYNC }, 'o' }
4080};
4081
4082static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4083  { { OPERAND_art }, 'm' }
4084};
4085
4086static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4087  { { STATE_DBREAKA1 }, 'm' },
4088  { { STATE_XTSYNC }, 'o' }
4089};
4090
4091static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4092  { { OPERAND_art }, 'o' }
4093};
4094
4095static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4096  { { STATE_DBREAKC1 }, 'i' }
4097};
4098
4099static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4100  { { OPERAND_art }, 'i' }
4101};
4102
4103static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4104  { { STATE_DBREAKC1 }, 'o' },
4105  { { STATE_XTSYNC }, 'o' }
4106};
4107
4108static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4109  { { OPERAND_art }, 'm' }
4110};
4111
4112static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4113  { { STATE_DBREAKC1 }, 'm' },
4114  { { STATE_XTSYNC }, 'o' }
4115};
4116
4117static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4118  { { OPERAND_art }, 'o' }
4119};
4120
4121static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4122  { { STATE_IBREAKA0 }, 'i' }
4123};
4124
4125static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4126  { { OPERAND_art }, 'i' }
4127};
4128
4129static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4130  { { STATE_IBREAKA0 }, 'o' }
4131};
4132
4133static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4134  { { OPERAND_art }, 'm' }
4135};
4136
4137static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4138  { { STATE_IBREAKA0 }, 'm' }
4139};
4140
4141static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4142  { { OPERAND_art }, 'o' }
4143};
4144
4145static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4146  { { STATE_IBREAKA1 }, 'i' }
4147};
4148
4149static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4150  { { OPERAND_art }, 'i' }
4151};
4152
4153static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4154  { { STATE_IBREAKA1 }, 'o' }
4155};
4156
4157static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4158  { { OPERAND_art }, 'm' }
4159};
4160
4161static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4162  { { STATE_IBREAKA1 }, 'm' }
4163};
4164
4165static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4166  { { OPERAND_art }, 'o' }
4167};
4168
4169static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4170  { { STATE_IBREAKENABLE }, 'i' }
4171};
4172
4173static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4174  { { OPERAND_art }, 'i' }
4175};
4176
4177static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4178  { { STATE_IBREAKENABLE }, 'o' }
4179};
4180
4181static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4182  { { OPERAND_art }, 'm' }
4183};
4184
4185static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4186  { { STATE_IBREAKENABLE }, 'm' }
4187};
4188
4189static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4190  { { OPERAND_art }, 'o' }
4191};
4192
4193static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4194  { { STATE_DEBUGCAUSE }, 'i' },
4195  { { STATE_DBNUM }, 'i' }
4196};
4197
4198static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4199  { { OPERAND_art }, 'i' }
4200};
4201
4202static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4203  { { STATE_DEBUGCAUSE }, 'o' },
4204  { { STATE_DBNUM }, 'o' }
4205};
4206
4207static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4208  { { OPERAND_art }, 'm' }
4209};
4210
4211static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4212  { { STATE_DEBUGCAUSE }, 'm' },
4213  { { STATE_DBNUM }, 'm' }
4214};
4215
4216static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4217  { { OPERAND_art }, 'o' }
4218};
4219
4220static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4221  { { STATE_ICOUNT }, 'i' }
4222};
4223
4224static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4225  { { OPERAND_art }, 'i' }
4226};
4227
4228static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4229  { { STATE_XTSYNC }, 'o' },
4230  { { STATE_ICOUNT }, 'o' }
4231};
4232
4233static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4234  { { OPERAND_art }, 'm' }
4235};
4236
4237static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4238  { { STATE_XTSYNC }, 'o' },
4239  { { STATE_ICOUNT }, 'm' }
4240};
4241
4242static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4243  { { OPERAND_art }, 'o' }
4244};
4245
4246static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4247  { { STATE_ICOUNTLEVEL }, 'i' }
4248};
4249
4250static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4251  { { OPERAND_art }, 'i' }
4252};
4253
4254static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4255  { { STATE_ICOUNTLEVEL }, 'o' }
4256};
4257
4258static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4259  { { OPERAND_art }, 'm' }
4260};
4261
4262static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4263  { { STATE_ICOUNTLEVEL }, 'm' }
4264};
4265
4266static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4267  { { OPERAND_art }, 'o' }
4268};
4269
4270static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4271  { { STATE_DDR }, 'i' }
4272};
4273
4274static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4275  { { OPERAND_art }, 'i' }
4276};
4277
4278static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4279  { { STATE_XTSYNC }, 'o' },
4280  { { STATE_DDR }, 'o' }
4281};
4282
4283static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4284  { { OPERAND_art }, 'm' }
4285};
4286
4287static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4288  { { STATE_XTSYNC }, 'o' },
4289  { { STATE_DDR }, 'm' }
4290};
4291
4292static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
4293  { { OPERAND_ars }, 'm' }
4294};
4295
4296static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
4297  { { STATE_XTSYNC }, 'o' },
4298  { { STATE_InOCDMode }, 'i' },
4299  { { STATE_DDR }, 'o' }
4300};
4301
4302static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
4303  { { OPERAND_ars }, 'm' }
4304};
4305
4306static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
4307  { { STATE_InOCDMode }, 'i' },
4308  { { STATE_DDR }, 'i' }
4309};
4310
4311static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
4312  { { OPERAND_imms }, 'i' }
4313};
4314
4315static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
4316  { { STATE_InOCDMode }, 'm' },
4317  { { STATE_EPC6 }, 'i' },
4318  { { STATE_PSWOE }, 'o' },
4319  { { STATE_PSCALLINC }, 'o' },
4320  { { STATE_PSOWB }, 'o' },
4321  { { STATE_PSUM }, 'o' },
4322  { { STATE_PSEXCM }, 'o' },
4323  { { STATE_PSINTLEVEL }, 'o' },
4324  { { STATE_EPS6 }, 'i' }
4325};
4326
4327static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
4328  { { STATE_InOCDMode }, 'm' }
4329};
4330
4331static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
4332  { { OPERAND_art }, 'i' }
4333};
4334
4335static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
4336  { { STATE_XTSYNC }, 'o' }
4337};
4338
4339static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
4340  { { OPERAND_art }, 'o' }
4341};
4342
4343static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
4344  { { STATE_CCOUNT }, 'i' }
4345};
4346
4347static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
4348  { { OPERAND_art }, 'i' }
4349};
4350
4351static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
4352  { { STATE_XTSYNC }, 'o' },
4353  { { STATE_CCOUNT }, 'o' }
4354};
4355
4356static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
4357  { { OPERAND_art }, 'm' }
4358};
4359
4360static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
4361  { { STATE_XTSYNC }, 'o' },
4362  { { STATE_CCOUNT }, 'm' }
4363};
4364
4365static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
4366  { { OPERAND_art }, 'o' }
4367};
4368
4369static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
4370  { { STATE_CCOMPARE0 }, 'i' }
4371};
4372
4373static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
4374  { { OPERAND_art }, 'i' }
4375};
4376
4377static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
4378  { { STATE_CCOMPARE0 }, 'o' },
4379  { { STATE_INTERRUPT }, 'm' }
4380};
4381
4382static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
4383  { { OPERAND_art }, 'm' }
4384};
4385
4386static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
4387  { { STATE_CCOMPARE0 }, 'm' },
4388  { { STATE_INTERRUPT }, 'm' }
4389};
4390
4391static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
4392  { { OPERAND_art }, 'o' }
4393};
4394
4395static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
4396  { { STATE_CCOMPARE1 }, 'i' }
4397};
4398
4399static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
4400  { { OPERAND_art }, 'i' }
4401};
4402
4403static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
4404  { { STATE_CCOMPARE1 }, 'o' },
4405  { { STATE_INTERRUPT }, 'm' }
4406};
4407
4408static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
4409  { { OPERAND_art }, 'm' }
4410};
4411
4412static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
4413  { { STATE_CCOMPARE1 }, 'm' },
4414  { { STATE_INTERRUPT }, 'm' }
4415};
4416
4417static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
4418  { { OPERAND_art }, 'o' }
4419};
4420
4421static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
4422  { { STATE_CCOMPARE2 }, 'i' }
4423};
4424
4425static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4426  { { OPERAND_art }, 'i' }
4427};
4428
4429static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4430  { { STATE_CCOMPARE2 }, 'o' },
4431  { { STATE_INTERRUPT }, 'm' }
4432};
4433
4434static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4435  { { OPERAND_art }, 'm' }
4436};
4437
4438static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4439  { { STATE_CCOMPARE2 }, 'm' },
4440  { { STATE_INTERRUPT }, 'm' }
4441};
4442
4443static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4444  { { OPERAND_ars }, 'i' }
4445};
4446
4447static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4448  { { STATE_XTSYNC }, 'o' }
4449};
4450
4451static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4452  { { OPERAND_art }, 'o' },
4453  { { OPERAND_ars }, 'i' }
4454};
4455
4456static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4457  { { OPERAND_art }, 'i' },
4458  { { OPERAND_ars }, 'i' }
4459};
4460
4461static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4462  { { STATE_XTSYNC }, 'o' }
4463};
4464
4465static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4466  { { OPERAND_ars }, 'i' }
4467};
4468
4469static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4470  { { OPERAND_art }, 'o' },
4471  { { OPERAND_ars }, 'i' }
4472};
4473
4474static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4475  { { OPERAND_art }, 'i' },
4476  { { OPERAND_ars }, 'i' }
4477};
4478
4479static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
4480  { { OPERAND_arr }, 'o' },
4481  { { OPERAND_ars }, 'i' },
4482  { { OPERAND_art }, 'i' }
4483};
4484
4485static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4486  { { OPERAND_art }, 'o' },
4487  { { OPERAND_ars }, 'i' }
4488};
4489
4490static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
4491  { { OPERAND_arr }, 'o' },
4492  { { OPERAND_ars }, 'i' },
4493  { { OPERAND_tp7 }, 'i' }
4494};
4495
4496static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
4497  { { OPERAND_art }, 'o' },
4498  { { OPERAND_ars }, 'i' },
4499  { { OPERAND_uimm8x4 }, 'i' }
4500};
4501
4502static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
4503  { { OPERAND_art }, 'i' },
4504  { { OPERAND_ars }, 'i' },
4505  { { OPERAND_uimm8x4 }, 'i' }
4506};
4507
4508static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
4509  { { OPERAND_art }, 'm' },
4510  { { OPERAND_ars }, 'i' },
4511  { { OPERAND_uimm8x4 }, 'i' }
4512};
4513
4514static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
4515  { { STATE_SCOMPARE1 }, 'i' },
4516  { { STATE_XTSYNC }, 'i' },
4517  { { STATE_SCOMPARE1 }, 'i' }
4518};
4519
4520static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
4521  { { OPERAND_art }, 'o' }
4522};
4523
4524static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
4525  { { STATE_SCOMPARE1 }, 'i' }
4526};
4527
4528static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
4529  { { OPERAND_art }, 'i' }
4530};
4531
4532static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
4533  { { STATE_SCOMPARE1 }, 'o' }
4534};
4535
4536static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
4537  { { OPERAND_art }, 'm' }
4538};
4539
4540static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
4541  { { STATE_SCOMPARE1 }, 'm' }
4542};
4543
4544static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
4545  { { OPERAND_art }, 'o' }
4546};
4547
4548static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
4549  { { STATE_ATOMCTL }, 'i' }
4550};
4551
4552static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
4553  { { OPERAND_art }, 'i' }
4554};
4555
4556static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
4557  { { STATE_ATOMCTL }, 'o' },
4558  { { STATE_XTSYNC }, 'o' }
4559};
4560
4561static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
4562  { { OPERAND_art }, 'm' }
4563};
4564
4565static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
4566  { { STATE_ATOMCTL }, 'm' },
4567  { { STATE_XTSYNC }, 'o' }
4568};
4569
4570static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
4571  { { OPERAND_arr }, 'o' },
4572  { { OPERAND_ars }, 'i' },
4573  { { OPERAND_art }, 'i' }
4574};
4575
4576static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
4577  { { OPERAND_art }, 'o' }
4578};
4579
4580static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
4581  { { OPERAND_art }, 'i' }
4582};
4583
4584static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
4585  { { OPERAND_art }, 'm' }
4586};
4587
4588static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
4589  { { OPERAND_art }, 'o' },
4590  { { OPERAND_ars }, 'i' }
4591};
4592
4593static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
4594  { { OPERAND_art }, 'i' },
4595  { { OPERAND_ars }, 'i' }
4596};
4597
4598static xtensa_arg_internal Iclass_rur_expstate_args[] = {
4599  { { OPERAND_arr }, 'o' }
4600};
4601
4602static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
4603  { { STATE_EXPSTATE }, 'i' }
4604};
4605
4606static xtensa_arg_internal Iclass_wur_expstate_args[] = {
4607  { { OPERAND_art }, 'i' }
4608};
4609
4610static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
4611  { { STATE_EXPSTATE }, 'o' }
4612};
4613
4614static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
4615  { { OPERAND_art }, 'o' }
4616};
4617
4618static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
4619  INTERFACE_IMPWIRE
4620};
4621
4622static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
4623  { { OPERAND_bitindex }, 'i' }
4624};
4625
4626static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
4627  { { STATE_EXPSTATE }, 'm' }
4628};
4629
4630static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
4631  { { OPERAND_bitindex }, 'i' }
4632};
4633
4634static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
4635  { { STATE_EXPSTATE }, 'm' }
4636};
4637
4638static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
4639  { { OPERAND_art }, 'i' },
4640  { { OPERAND_ars }, 'i' }
4641};
4642
4643static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
4644  { { STATE_EXPSTATE }, 'm' }
4645};
4646
4647static xtensa_iclass_internal iclasses[] = {
4648  { 0, 0 /* xt_iclass_excw */,
4649    0, 0, 0, 0 },
4650  { 0, 0 /* xt_iclass_rfe */,
4651    2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4652  { 0, 0 /* xt_iclass_rfde */,
4653    1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4654  { 0, 0 /* xt_iclass_syscall */,
4655    0, 0, 0, 0 },
4656  { 2, Iclass_xt_iclass_call12_args,
4657    1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
4658  { 2, Iclass_xt_iclass_call8_args,
4659    1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
4660  { 2, Iclass_xt_iclass_call4_args,
4661    1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
4662  { 2, Iclass_xt_iclass_callx12_args,
4663    1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
4664  { 2, Iclass_xt_iclass_callx8_args,
4665    1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
4666  { 2, Iclass_xt_iclass_callx4_args,
4667    1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
4668  { 3, Iclass_xt_iclass_entry_args,
4669    5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
4670  { 2, Iclass_xt_iclass_movsp_args,
4671    2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
4672  { 1, Iclass_xt_iclass_rotw_args,
4673    1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
4674  { 1, Iclass_xt_iclass_retw_args,
4675    5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
4676  { 0, 0 /* xt_iclass_rfwou */,
4677    5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
4678  { 3, Iclass_xt_iclass_l32e_args,
4679    0, 0, 0, 0 },
4680  { 3, Iclass_xt_iclass_s32e_args,
4681    0, 0, 0, 0 },
4682  { 1, Iclass_xt_iclass_rsr_windowbase_args,
4683    1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
4684  { 1, Iclass_xt_iclass_wsr_windowbase_args,
4685    1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
4686  { 1, Iclass_xt_iclass_xsr_windowbase_args,
4687    1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
4688  { 1, Iclass_xt_iclass_rsr_windowstart_args,
4689    1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
4690  { 1, Iclass_xt_iclass_wsr_windowstart_args,
4691    1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
4692  { 1, Iclass_xt_iclass_xsr_windowstart_args,
4693    1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
4694  { 3, Iclass_xt_iclass_add_n_args,
4695    0, 0, 0, 0 },
4696  { 3, Iclass_xt_iclass_addi_n_args,
4697    0, 0, 0, 0 },
4698  { 2, Iclass_xt_iclass_bz6_args,
4699    0, 0, 0, 0 },
4700  { 0, 0 /* xt_iclass_ill_n */,
4701    0, 0, 0, 0 },
4702  { 3, Iclass_xt_iclass_loadi4_args,
4703    0, 0, 0, 0 },
4704  { 2, Iclass_xt_iclass_mov_n_args,
4705    0, 0, 0, 0 },
4706  { 2, Iclass_xt_iclass_movi_n_args,
4707    0, 0, 0, 0 },
4708  { 0, 0 /* xt_iclass_nopn */,
4709    0, 0, 0, 0 },
4710  { 1, Iclass_xt_iclass_retn_args,
4711    0, 0, 0, 0 },
4712  { 3, Iclass_xt_iclass_storei4_args,
4713    0, 0, 0, 0 },
4714  { 3, Iclass_xt_iclass_addi_args,
4715    0, 0, 0, 0 },
4716  { 3, Iclass_xt_iclass_addmi_args,
4717    0, 0, 0, 0 },
4718  { 3, Iclass_xt_iclass_addsub_args,
4719    0, 0, 0, 0 },
4720  { 3, Iclass_xt_iclass_bit_args,
4721    0, 0, 0, 0 },
4722  { 3, Iclass_xt_iclass_bsi8_args,
4723    0, 0, 0, 0 },
4724  { 3, Iclass_xt_iclass_bsi8b_args,
4725    0, 0, 0, 0 },
4726  { 3, Iclass_xt_iclass_bsi8u_args,
4727    0, 0, 0, 0 },
4728  { 3, Iclass_xt_iclass_bst8_args,
4729    0, 0, 0, 0 },
4730  { 2, Iclass_xt_iclass_bsz12_args,
4731    0, 0, 0, 0 },
4732  { 2, Iclass_xt_iclass_call0_args,
4733    0, 0, 0, 0 },
4734  { 2, Iclass_xt_iclass_callx0_args,
4735    0, 0, 0, 0 },
4736  { 4, Iclass_xt_iclass_exti_args,
4737    0, 0, 0, 0 },
4738  { 0, 0 /* xt_iclass_ill */,
4739    0, 0, 0, 0 },
4740  { 1, Iclass_xt_iclass_jump_args,
4741    0, 0, 0, 0 },
4742  { 1, Iclass_xt_iclass_jumpx_args,
4743    0, 0, 0, 0 },
4744  { 3, Iclass_xt_iclass_l16ui_args,
4745    0, 0, 0, 0 },
4746  { 3, Iclass_xt_iclass_l16si_args,
4747    0, 0, 0, 0 },
4748  { 3, Iclass_xt_iclass_l32i_args,
4749    0, 0, 0, 0 },
4750  { 2, Iclass_xt_iclass_l32r_args,
4751    0, 0, 0, 0 },
4752  { 3, Iclass_xt_iclass_l8i_args,
4753    0, 0, 0, 0 },
4754  { 2, Iclass_xt_iclass_movi_args,
4755    0, 0, 0, 0 },
4756  { 3, Iclass_xt_iclass_movz_args,
4757    0, 0, 0, 0 },
4758  { 2, Iclass_xt_iclass_neg_args,
4759    0, 0, 0, 0 },
4760  { 0, 0 /* xt_iclass_nop */,
4761    0, 0, 0, 0 },
4762  { 1, Iclass_xt_iclass_return_args,
4763    0, 0, 0, 0 },
4764  { 0, 0 /* xt_iclass_simcall */,
4765    0, 0, 0, 0 },
4766  { 3, Iclass_xt_iclass_s16i_args,
4767    0, 0, 0, 0 },
4768  { 3, Iclass_xt_iclass_s32i_args,
4769    0, 0, 0, 0 },
4770  { 3, Iclass_xt_iclass_s32nb_args,
4771    0, 0, 0, 0 },
4772  { 3, Iclass_xt_iclass_s8i_args,
4773    0, 0, 0, 0 },
4774  { 1, Iclass_xt_iclass_sar_args,
4775    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
4776  { 1, Iclass_xt_iclass_sari_args,
4777    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
4778  { 2, Iclass_xt_iclass_shifts_args,
4779    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
4780  { 3, Iclass_xt_iclass_shiftst_args,
4781    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
4782  { 2, Iclass_xt_iclass_shiftt_args,
4783    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
4784  { 3, Iclass_xt_iclass_slli_args,
4785    0, 0, 0, 0 },
4786  { 3, Iclass_xt_iclass_srai_args,
4787    0, 0, 0, 0 },
4788  { 3, Iclass_xt_iclass_srli_args,
4789    0, 0, 0, 0 },
4790  { 0, 0 /* xt_iclass_memw */,
4791    0, 0, 0, 0 },
4792  { 0, 0 /* xt_iclass_extw */,
4793    0, 0, 0, 0 },
4794  { 0, 0 /* xt_iclass_isync */,
4795    0, 0, 0, 0 },
4796  { 0, 0 /* xt_iclass_sync */,
4797    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
4798  { 2, Iclass_xt_iclass_rsil_args,
4799    6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
4800  { 1, Iclass_xt_iclass_rsr_sar_args,
4801    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
4802  { 1, Iclass_xt_iclass_wsr_sar_args,
4803    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
4804  { 1, Iclass_xt_iclass_xsr_sar_args,
4805    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
4806  { 1, Iclass_xt_iclass_rsr_memctl_args,
4807    0, 0, 0, 0 },
4808  { 1, Iclass_xt_iclass_wsr_memctl_args,
4809    0, 0, 0, 0 },
4810  { 1, Iclass_xt_iclass_xsr_memctl_args,
4811    0, 0, 0, 0 },
4812  { 1, Iclass_xt_iclass_rsr_litbase_args,
4813    0, 0, 0, 0 },
4814  { 1, Iclass_xt_iclass_wsr_litbase_args,
4815    0, 0, 0, 0 },
4816  { 1, Iclass_xt_iclass_xsr_litbase_args,
4817    0, 0, 0, 0 },
4818  { 1, Iclass_xt_iclass_rsr_configid0_args,
4819    0, 0, 0, 0 },
4820  { 1, Iclass_xt_iclass_wsr_configid0_args,
4821    0, 0, 0, 0 },
4822  { 1, Iclass_xt_iclass_rsr_configid1_args,
4823    0, 0, 0, 0 },
4824  { 1, Iclass_xt_iclass_rsr_ps_args,
4825    6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
4826  { 1, Iclass_xt_iclass_wsr_ps_args,
4827    6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
4828  { 1, Iclass_xt_iclass_xsr_ps_args,
4829    6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
4830  { 1, Iclass_xt_iclass_rsr_epc1_args,
4831    1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
4832  { 1, Iclass_xt_iclass_wsr_epc1_args,
4833    1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
4834  { 1, Iclass_xt_iclass_xsr_epc1_args,
4835    1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
4836  { 1, Iclass_xt_iclass_rsr_excsave1_args,
4837    1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
4838  { 1, Iclass_xt_iclass_wsr_excsave1_args,
4839    1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
4840  { 1, Iclass_xt_iclass_xsr_excsave1_args,
4841    1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
4842  { 1, Iclass_xt_iclass_rsr_epc2_args,
4843    1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
4844  { 1, Iclass_xt_iclass_wsr_epc2_args,
4845    1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
4846  { 1, Iclass_xt_iclass_xsr_epc2_args,
4847    1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
4848  { 1, Iclass_xt_iclass_rsr_excsave2_args,
4849    1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
4850  { 1, Iclass_xt_iclass_wsr_excsave2_args,
4851    1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
4852  { 1, Iclass_xt_iclass_xsr_excsave2_args,
4853    1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
4854  { 1, Iclass_xt_iclass_rsr_epc3_args,
4855    1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
4856  { 1, Iclass_xt_iclass_wsr_epc3_args,
4857    1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
4858  { 1, Iclass_xt_iclass_xsr_epc3_args,
4859    1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
4860  { 1, Iclass_xt_iclass_rsr_excsave3_args,
4861    1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
4862  { 1, Iclass_xt_iclass_wsr_excsave3_args,
4863    1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
4864  { 1, Iclass_xt_iclass_xsr_excsave3_args,
4865    1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
4866  { 1, Iclass_xt_iclass_rsr_epc4_args,
4867    1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
4868  { 1, Iclass_xt_iclass_wsr_epc4_args,
4869    1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
4870  { 1, Iclass_xt_iclass_xsr_epc4_args,
4871    1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
4872  { 1, Iclass_xt_iclass_rsr_excsave4_args,
4873    1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
4874  { 1, Iclass_xt_iclass_wsr_excsave4_args,
4875    1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
4876  { 1, Iclass_xt_iclass_xsr_excsave4_args,
4877    1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
4878  { 1, Iclass_xt_iclass_rsr_epc5_args,
4879    1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
4880  { 1, Iclass_xt_iclass_wsr_epc5_args,
4881    1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
4882  { 1, Iclass_xt_iclass_xsr_epc5_args,
4883    1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
4884  { 1, Iclass_xt_iclass_rsr_excsave5_args,
4885    1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
4886  { 1, Iclass_xt_iclass_wsr_excsave5_args,
4887    1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
4888  { 1, Iclass_xt_iclass_xsr_excsave5_args,
4889    1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
4890  { 1, Iclass_xt_iclass_rsr_epc6_args,
4891    1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
4892  { 1, Iclass_xt_iclass_wsr_epc6_args,
4893    1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
4894  { 1, Iclass_xt_iclass_xsr_epc6_args,
4895    1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
4896  { 1, Iclass_xt_iclass_rsr_excsave6_args,
4897    1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
4898  { 1, Iclass_xt_iclass_wsr_excsave6_args,
4899    1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
4900  { 1, Iclass_xt_iclass_xsr_excsave6_args,
4901    1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
4902  { 1, Iclass_xt_iclass_rsr_epc7_args,
4903    1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
4904  { 1, Iclass_xt_iclass_wsr_epc7_args,
4905    1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
4906  { 1, Iclass_xt_iclass_xsr_epc7_args,
4907    1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
4908  { 1, Iclass_xt_iclass_rsr_excsave7_args,
4909    1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
4910  { 1, Iclass_xt_iclass_wsr_excsave7_args,
4911    1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
4912  { 1, Iclass_xt_iclass_xsr_excsave7_args,
4913    1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
4914  { 1, Iclass_xt_iclass_rsr_eps2_args,
4915    1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
4916  { 1, Iclass_xt_iclass_wsr_eps2_args,
4917    1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
4918  { 1, Iclass_xt_iclass_xsr_eps2_args,
4919    1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
4920  { 1, Iclass_xt_iclass_rsr_eps3_args,
4921    1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
4922  { 1, Iclass_xt_iclass_wsr_eps3_args,
4923    1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
4924  { 1, Iclass_xt_iclass_xsr_eps3_args,
4925    1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
4926  { 1, Iclass_xt_iclass_rsr_eps4_args,
4927    1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
4928  { 1, Iclass_xt_iclass_wsr_eps4_args,
4929    1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
4930  { 1, Iclass_xt_iclass_xsr_eps4_args,
4931    1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
4932  { 1, Iclass_xt_iclass_rsr_eps5_args,
4933    1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
4934  { 1, Iclass_xt_iclass_wsr_eps5_args,
4935    1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
4936  { 1, Iclass_xt_iclass_xsr_eps5_args,
4937    1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
4938  { 1, Iclass_xt_iclass_rsr_eps6_args,
4939    1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
4940  { 1, Iclass_xt_iclass_wsr_eps6_args,
4941    1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
4942  { 1, Iclass_xt_iclass_xsr_eps6_args,
4943    1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
4944  { 1, Iclass_xt_iclass_rsr_eps7_args,
4945    1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
4946  { 1, Iclass_xt_iclass_wsr_eps7_args,
4947    1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
4948  { 1, Iclass_xt_iclass_xsr_eps7_args,
4949    1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
4950  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
4951    1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
4952  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
4953    1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
4954  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
4955    1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
4956  { 1, Iclass_xt_iclass_rsr_depc_args,
4957    1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
4958  { 1, Iclass_xt_iclass_wsr_depc_args,
4959    1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
4960  { 1, Iclass_xt_iclass_xsr_depc_args,
4961    1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
4962  { 1, Iclass_xt_iclass_rsr_exccause_args,
4963    2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
4964  { 1, Iclass_xt_iclass_wsr_exccause_args,
4965    1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
4966  { 1, Iclass_xt_iclass_xsr_exccause_args,
4967    1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
4968  { 1, Iclass_xt_iclass_rsr_misc0_args,
4969    1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
4970  { 1, Iclass_xt_iclass_wsr_misc0_args,
4971    1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
4972  { 1, Iclass_xt_iclass_xsr_misc0_args,
4973    1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
4974  { 1, Iclass_xt_iclass_rsr_misc1_args,
4975    1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
4976  { 1, Iclass_xt_iclass_wsr_misc1_args,
4977    1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
4978  { 1, Iclass_xt_iclass_xsr_misc1_args,
4979    1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
4980  { 1, Iclass_xt_iclass_rsr_prid_args,
4981    0, 0, 0, 0 },
4982  { 1, Iclass_xt_iclass_rsr_vecbase_args,
4983    1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
4984  { 1, Iclass_xt_iclass_wsr_vecbase_args,
4985    1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
4986  { 1, Iclass_xt_iclass_xsr_vecbase_args,
4987    1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
4988  { 3, Iclass_xt_iclass_salt_args,
4989    0, 0, 0, 0 },
4990  { 3, Iclass_xt_mul16_args,
4991    0, 0, 0, 0 },
4992  { 3, Iclass_xt_mul32_args,
4993    0, 0, 0, 0 },
4994  { 1, Iclass_xt_iclass_rfi_args,
4995    20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
4996  { 1, Iclass_xt_iclass_wait_args,
4997    1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
4998  { 1, Iclass_xt_iclass_rsr_interrupt_args,
4999    1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5000  { 1, Iclass_xt_iclass_wsr_intset_args,
5001    2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5002  { 1, Iclass_xt_iclass_wsr_intclear_args,
5003    2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5004  { 1, Iclass_xt_iclass_rsr_intenable_args,
5005    1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5006  { 1, Iclass_xt_iclass_wsr_intenable_args,
5007    1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5008  { 1, Iclass_xt_iclass_xsr_intenable_args,
5009    1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5010  { 2, Iclass_xt_iclass_break_args,
5011    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5012  { 1, Iclass_xt_iclass_break_n_args,
5013    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5014  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
5015    1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5016  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
5017    2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5018  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
5019    2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5020  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
5021    1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5022  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
5023    2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5024  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
5025    2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5026  { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
5027    1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5028  { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
5029    2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5030  { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
5031    2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5032  { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
5033    1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5034  { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
5035    2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5036  { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
5037    2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5038  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
5039    1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5040  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
5041    1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5042  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
5043    1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5044  { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
5045    1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5046  { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
5047    1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5048  { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
5049    1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5050  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
5051    1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5052  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
5053    1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5054  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
5055    1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5056  { 1, Iclass_xt_iclass_rsr_debugcause_args,
5057    2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5058  { 1, Iclass_xt_iclass_wsr_debugcause_args,
5059    2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5060  { 1, Iclass_xt_iclass_xsr_debugcause_args,
5061    2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5062  { 1, Iclass_xt_iclass_rsr_icount_args,
5063    1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5064  { 1, Iclass_xt_iclass_wsr_icount_args,
5065    2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5066  { 1, Iclass_xt_iclass_xsr_icount_args,
5067    2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5068  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
5069    1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5070  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
5071    1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5072  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
5073    1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5074  { 1, Iclass_xt_iclass_rsr_ddr_args,
5075    1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5076  { 1, Iclass_xt_iclass_wsr_ddr_args,
5077    2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5078  { 1, Iclass_xt_iclass_xsr_ddr_args,
5079    2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5080  { 1, Iclass_xt_iclass_lddr32_p_args,
5081    3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
5082  { 1, Iclass_xt_iclass_sddr32_p_args,
5083    2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
5084  { 1, Iclass_xt_iclass_rfdo_args,
5085    9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5086  { 0, 0 /* xt_iclass_rfdd */,
5087    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5088  { 1, Iclass_xt_iclass_wsr_mmid_args,
5089    1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5090  { 1, Iclass_xt_iclass_rsr_ccount_args,
5091    1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5092  { 1, Iclass_xt_iclass_wsr_ccount_args,
5093    2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5094  { 1, Iclass_xt_iclass_xsr_ccount_args,
5095    2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5096  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
5097    1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5098  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
5099    2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5100  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
5101    2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5102  { 1, Iclass_xt_iclass_rsr_ccompare1_args,
5103    1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5104  { 1, Iclass_xt_iclass_wsr_ccompare1_args,
5105    2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5106  { 1, Iclass_xt_iclass_xsr_ccompare1_args,
5107    2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5108  { 1, Iclass_xt_iclass_rsr_ccompare2_args,
5109    1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5110  { 1, Iclass_xt_iclass_wsr_ccompare2_args,
5111    2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5112  { 1, Iclass_xt_iclass_xsr_ccompare2_args,
5113    2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5114  { 1, Iclass_xt_iclass_idtlb_args,
5115    1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
5116  { 2, Iclass_xt_iclass_rdtlb_args,
5117    0, 0, 0, 0 },
5118  { 2, Iclass_xt_iclass_wdtlb_args,
5119    1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
5120  { 1, Iclass_xt_iclass_iitlb_args,
5121    0, 0, 0, 0 },
5122  { 2, Iclass_xt_iclass_ritlb_args,
5123    0, 0, 0, 0 },
5124  { 2, Iclass_xt_iclass_witlb_args,
5125    0, 0, 0, 0 },
5126  { 3, Iclass_xt_iclass_minmax_args,
5127    0, 0, 0, 0 },
5128  { 2, Iclass_xt_iclass_nsa_args,
5129    0, 0, 0, 0 },
5130  { 3, Iclass_xt_iclass_sx_args,
5131    0, 0, 0, 0 },
5132  { 3, Iclass_xt_iclass_l32ai_args,
5133    0, 0, 0, 0 },
5134  { 3, Iclass_xt_iclass_s32ri_args,
5135    0, 0, 0, 0 },
5136  { 3, Iclass_xt_iclass_s32c1i_args,
5137    3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
5138  { 1, Iclass_xt_iclass_rsr_scompare1_args,
5139    1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
5140  { 1, Iclass_xt_iclass_wsr_scompare1_args,
5141    1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
5142  { 1, Iclass_xt_iclass_xsr_scompare1_args,
5143    1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
5144  { 1, Iclass_xt_iclass_rsr_atomctl_args,
5145    1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
5146  { 1, Iclass_xt_iclass_wsr_atomctl_args,
5147    2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
5148  { 1, Iclass_xt_iclass_xsr_atomctl_args,
5149    2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
5150  { 3, Iclass_xt_iclass_div_args,
5151    0, 0, 0, 0 },
5152  { 1, Iclass_xt_iclass_rsr_eraccess_args,
5153    0, 0, 0, 0 },
5154  { 1, Iclass_xt_iclass_wsr_eraccess_args,
5155    0, 0, 0, 0 },
5156  { 1, Iclass_xt_iclass_xsr_eraccess_args,
5157    0, 0, 0, 0 },
5158  { 2, Iclass_xt_iclass_rer_args,
5159    0, 0, 0, 0 },
5160  { 2, Iclass_xt_iclass_wer_args,
5161    0, 0, 0, 0 },
5162  { 1, Iclass_rur_expstate_args,
5163    1, Iclass_rur_expstate_stateArgs, 0, 0 },
5164  { 1, Iclass_wur_expstate_args,
5165    1, Iclass_wur_expstate_stateArgs, 0, 0 },
5166  { 1, Iclass_iclass_READ_IMPWIRE_args,
5167    0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
5168  { 1, Iclass_iclass_SETB_EXPSTATE_args,
5169    1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
5170  { 1, Iclass_iclass_CLRB_EXPSTATE_args,
5171    1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
5172  { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
5173    1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
5174};
5175
5176enum xtensa_iclass_id {
5177  ICLASS_xt_iclass_excw,
5178  ICLASS_xt_iclass_rfe,
5179  ICLASS_xt_iclass_rfde,
5180  ICLASS_xt_iclass_syscall,
5181  ICLASS_xt_iclass_call12,
5182  ICLASS_xt_iclass_call8,
5183  ICLASS_xt_iclass_call4,
5184  ICLASS_xt_iclass_callx12,
5185  ICLASS_xt_iclass_callx8,
5186  ICLASS_xt_iclass_callx4,
5187  ICLASS_xt_iclass_entry,
5188  ICLASS_xt_iclass_movsp,
5189  ICLASS_xt_iclass_rotw,
5190  ICLASS_xt_iclass_retw,
5191  ICLASS_xt_iclass_rfwou,
5192  ICLASS_xt_iclass_l32e,
5193  ICLASS_xt_iclass_s32e,
5194  ICLASS_xt_iclass_rsr_windowbase,
5195  ICLASS_xt_iclass_wsr_windowbase,
5196  ICLASS_xt_iclass_xsr_windowbase,
5197  ICLASS_xt_iclass_rsr_windowstart,
5198  ICLASS_xt_iclass_wsr_windowstart,
5199  ICLASS_xt_iclass_xsr_windowstart,
5200  ICLASS_xt_iclass_add_n,
5201  ICLASS_xt_iclass_addi_n,
5202  ICLASS_xt_iclass_bz6,
5203  ICLASS_xt_iclass_ill_n,
5204  ICLASS_xt_iclass_loadi4,
5205  ICLASS_xt_iclass_mov_n,
5206  ICLASS_xt_iclass_movi_n,
5207  ICLASS_xt_iclass_nopn,
5208  ICLASS_xt_iclass_retn,
5209  ICLASS_xt_iclass_storei4,
5210  ICLASS_xt_iclass_addi,
5211  ICLASS_xt_iclass_addmi,
5212  ICLASS_xt_iclass_addsub,
5213  ICLASS_xt_iclass_bit,
5214  ICLASS_xt_iclass_bsi8,
5215  ICLASS_xt_iclass_bsi8b,
5216  ICLASS_xt_iclass_bsi8u,
5217  ICLASS_xt_iclass_bst8,
5218  ICLASS_xt_iclass_bsz12,
5219  ICLASS_xt_iclass_call0,
5220  ICLASS_xt_iclass_callx0,
5221  ICLASS_xt_iclass_exti,
5222  ICLASS_xt_iclass_ill,
5223  ICLASS_xt_iclass_jump,
5224  ICLASS_xt_iclass_jumpx,
5225  ICLASS_xt_iclass_l16ui,
5226  ICLASS_xt_iclass_l16si,
5227  ICLASS_xt_iclass_l32i,
5228  ICLASS_xt_iclass_l32r,
5229  ICLASS_xt_iclass_l8i,
5230  ICLASS_xt_iclass_movi,
5231  ICLASS_xt_iclass_movz,
5232  ICLASS_xt_iclass_neg,
5233  ICLASS_xt_iclass_nop,
5234  ICLASS_xt_iclass_return,
5235  ICLASS_xt_iclass_simcall,
5236  ICLASS_xt_iclass_s16i,
5237  ICLASS_xt_iclass_s32i,
5238  ICLASS_xt_iclass_s32nb,
5239  ICLASS_xt_iclass_s8i,
5240  ICLASS_xt_iclass_sar,
5241  ICLASS_xt_iclass_sari,
5242  ICLASS_xt_iclass_shifts,
5243  ICLASS_xt_iclass_shiftst,
5244  ICLASS_xt_iclass_shiftt,
5245  ICLASS_xt_iclass_slli,
5246  ICLASS_xt_iclass_srai,
5247  ICLASS_xt_iclass_srli,
5248  ICLASS_xt_iclass_memw,
5249  ICLASS_xt_iclass_extw,
5250  ICLASS_xt_iclass_isync,
5251  ICLASS_xt_iclass_sync,
5252  ICLASS_xt_iclass_rsil,
5253  ICLASS_xt_iclass_rsr_sar,
5254  ICLASS_xt_iclass_wsr_sar,
5255  ICLASS_xt_iclass_xsr_sar,
5256  ICLASS_xt_iclass_rsr_memctl,
5257  ICLASS_xt_iclass_wsr_memctl,
5258  ICLASS_xt_iclass_xsr_memctl,
5259  ICLASS_xt_iclass_rsr_litbase,
5260  ICLASS_xt_iclass_wsr_litbase,
5261  ICLASS_xt_iclass_xsr_litbase,
5262  ICLASS_xt_iclass_rsr_configid0,
5263  ICLASS_xt_iclass_wsr_configid0,
5264  ICLASS_xt_iclass_rsr_configid1,
5265  ICLASS_xt_iclass_rsr_ps,
5266  ICLASS_xt_iclass_wsr_ps,
5267  ICLASS_xt_iclass_xsr_ps,
5268  ICLASS_xt_iclass_rsr_epc1,
5269  ICLASS_xt_iclass_wsr_epc1,
5270  ICLASS_xt_iclass_xsr_epc1,
5271  ICLASS_xt_iclass_rsr_excsave1,
5272  ICLASS_xt_iclass_wsr_excsave1,
5273  ICLASS_xt_iclass_xsr_excsave1,
5274  ICLASS_xt_iclass_rsr_epc2,
5275  ICLASS_xt_iclass_wsr_epc2,
5276  ICLASS_xt_iclass_xsr_epc2,
5277  ICLASS_xt_iclass_rsr_excsave2,
5278  ICLASS_xt_iclass_wsr_excsave2,
5279  ICLASS_xt_iclass_xsr_excsave2,
5280  ICLASS_xt_iclass_rsr_epc3,
5281  ICLASS_xt_iclass_wsr_epc3,
5282  ICLASS_xt_iclass_xsr_epc3,
5283  ICLASS_xt_iclass_rsr_excsave3,
5284  ICLASS_xt_iclass_wsr_excsave3,
5285  ICLASS_xt_iclass_xsr_excsave3,