LXR qemu/target/xtensa/cpu-qom.h

   1/*
   2 * QEMU Xtensa CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions are met:
   9 *     * Redistributions of source code must retain the above copyright
  10 *       notice, this list of conditions and the following disclaimer.
  11 *     * Redistributions in binary form must reproduce the above copyright
  12 *       notice, this list of conditions and the following disclaimer in the
  13 *       documentation and/or other materials provided with the distribution.
  14 *     * Neither the name of the Open Source and Linux Lab nor the
  15 *       names of its contributors may be used to endorse or promote products
  16 *       derived from this software without specific prior written permission.
  17 *
  18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 */
  29#ifndef QEMU_XTENSA_CPU_QOM_H
  30#define QEMU_XTENSA_CPU_QOM_H
  31
  32#include "hw/core/cpu.h"
  33#include "qom/object.h"
  34
  35#define TYPE_XTENSA_CPU "xtensa-cpu"
  36
  37OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
  38                    XTENSA_CPU)
  39
  40typedef struct XtensaConfig XtensaConfig;
  41
  42/**
  43 * XtensaCPUClass:
  44 * @parent_realize: The parent class' realize handler.
  45 * @parent_reset: The parent class' reset handler.
  46 * @config: The CPU core configuration.
  47 *
  48 * An Xtensa CPU model.
  49 */
  50struct XtensaCPUClass {
  51    /*< private >*/
  52    CPUClass parent_class;
  53    /*< public >*/
  54
  55    DeviceRealize parent_realize;
  56    DeviceReset parent_reset;
  57
  58    const XtensaConfig *config;
  59};
  60
  61
  62#endif
  63