1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "cpu.h"
34#include "fpu/softfloat.h"
35#include "qemu/module.h"
36#include "migration/vmstate.h"
37
38
39static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
40{
41 XtensaCPU *cpu = XTENSA_CPU(cs);
42
43 cpu->env.pc = value;
44}
45
46static bool xtensa_cpu_has_work(CPUState *cs)
47{
48#ifndef CONFIG_USER_ONLY
49 XtensaCPU *cpu = XTENSA_CPU(cs);
50
51 return !cpu->env.runstall && cpu->env.pending_irq_level;
52#else
53 return true;
54#endif
55}
56
57#ifdef CONFIG_USER_ONLY
58static bool abi_call0;
59
60void xtensa_set_abi_call0(void)
61{
62 abi_call0 = true;
63}
64
65bool xtensa_abi_call0(void)
66{
67 return abi_call0;
68}
69#endif
70
71static void xtensa_cpu_reset(DeviceState *dev)
72{
73 CPUState *s = CPU(dev);
74 XtensaCPU *cpu = XTENSA_CPU(s);
75 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
76 CPUXtensaState *env = &cpu->env;
77 bool dfpu = xtensa_option_enabled(env->config,
78 XTENSA_OPTION_DFP_COPROCESSOR);
79
80 xcc->parent_reset(dev);
81
82 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
83 env->sregs[LITBASE] &= ~1;
84#ifndef CONFIG_USER_ONLY
85 env->sregs[PS] = xtensa_option_enabled(env->config,
86 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
87 env->pending_irq_level = 0;
88#else
89 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
90 if (xtensa_option_enabled(env->config,
91 XTENSA_OPTION_WINDOWED_REGISTER) &&
92 !xtensa_abi_call0()) {
93 env->sregs[PS] |= PS_WOE;
94 }
95 env->sregs[CPENABLE] = 0xff;
96#endif
97 env->sregs[VECBASE] = env->config->vecbase;
98 env->sregs[IBREAKENABLE] = 0;
99 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
100 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
101 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
102 env->sregs[CONFIGID0] = env->config->configid[0];
103 env->sregs[CONFIGID1] = env->config->configid[1];
104 env->exclusive_addr = -1;
105
106#ifndef CONFIG_USER_ONLY
107 reset_mmu(env);
108 s->halted = env->runstall;
109#endif
110 set_no_signaling_nans(!dfpu, &env->fp_status);
111 set_use_first_nan(!dfpu, &env->fp_status);
112}
113
114static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
115{
116 ObjectClass *oc;
117 char *typename;
118
119 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
120 oc = object_class_by_name(typename);
121 g_free(typename);
122 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
123 object_class_is_abstract(oc)) {
124 return NULL;
125 }
126 return oc;
127}
128
129static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
130{
131 XtensaCPU *cpu = XTENSA_CPU(cs);
132
133 info->private_data = cpu->env.config->isa;
134 info->print_insn = print_insn_xtensa;
135}
136
137static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
138{
139 CPUState *cs = CPU(dev);
140 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
141 Error *local_err = NULL;
142
143#ifndef CONFIG_USER_ONLY
144 xtensa_irq_init(&XTENSA_CPU(dev)->env);
145#endif
146
147 cpu_exec_realizefn(cs, &local_err);
148 if (local_err != NULL) {
149 error_propagate(errp, local_err);
150 return;
151 }
152
153 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
154
155 qemu_init_vcpu(cs);
156
157 xcc->parent_realize(dev, errp);
158}
159
160static void xtensa_cpu_initfn(Object *obj)
161{
162 XtensaCPU *cpu = XTENSA_CPU(obj);
163 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
164 CPUXtensaState *env = &cpu->env;
165
166 cpu_set_cpustate_pointers(cpu);
167 env->config = xcc->config;
168
169#ifndef CONFIG_USER_ONLY
170 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
171 env->system_er = g_malloc(sizeof(*env->system_er));
172 memory_region_init_io(env->system_er, obj, NULL, env, "er",
173 UINT64_C(0x100000000));
174 address_space_init(env->address_space_er, env->system_er, "ER");
175#endif
176}
177
178#ifndef CONFIG_USER_ONLY
179static const VMStateDescription vmstate_xtensa_cpu = {
180 .name = "cpu",
181 .unmigratable = 1,
182};
183
184#include "hw/core/sysemu-cpu-ops.h"
185
186static const struct SysemuCPUOps xtensa_sysemu_ops = {
187 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
188};
189#endif
190
191#include "hw/core/tcg-cpu-ops.h"
192
193static const struct TCGCPUOps xtensa_tcg_ops = {
194 .initialize = xtensa_translate_init,
195 .debug_excp_handler = xtensa_breakpoint_handler,
196
197#ifndef CONFIG_USER_ONLY
198 .tlb_fill = xtensa_cpu_tlb_fill,
199 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
200 .do_interrupt = xtensa_cpu_do_interrupt,
201 .do_transaction_failed = xtensa_cpu_do_transaction_failed,
202 .do_unaligned_access = xtensa_cpu_do_unaligned_access,
203#endif
204};
205
206static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
207{
208 DeviceClass *dc = DEVICE_CLASS(oc);
209 CPUClass *cc = CPU_CLASS(oc);
210 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
211
212 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
213 &xcc->parent_realize);
214
215 device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
216
217 cc->class_by_name = xtensa_cpu_class_by_name;
218 cc->has_work = xtensa_cpu_has_work;
219 cc->dump_state = xtensa_cpu_dump_state;
220 cc->set_pc = xtensa_cpu_set_pc;
221 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
222 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
223 cc->gdb_stop_before_watchpoint = true;
224#ifndef CONFIG_USER_ONLY
225 cc->sysemu_ops = &xtensa_sysemu_ops;
226 dc->vmsd = &vmstate_xtensa_cpu;
227#endif
228 cc->disas_set_info = xtensa_cpu_disas_set_info;
229 cc->tcg_ops = &xtensa_tcg_ops;
230}
231
232static const TypeInfo xtensa_cpu_type_info = {
233 .name = TYPE_XTENSA_CPU,
234 .parent = TYPE_CPU,
235 .instance_size = sizeof(XtensaCPU),
236 .instance_init = xtensa_cpu_initfn,
237 .abstract = true,
238 .class_size = sizeof(XtensaCPUClass),
239 .class_init = xtensa_cpu_class_init,
240};
241
242static void xtensa_cpu_register_types(void)
243{
244 type_register_static(&xtensa_cpu_type_info);
245}
246
247type_init(xtensa_cpu_register_types)
248
