LXR qemu/tcg/riscv/tcg-target.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2018 SiFive, Inc
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef RISCV_TCG_TARGET_H
  26#define RISCV_TCG_TARGET_H
  27
  28#if __riscv_xlen == 32
  29# define TCG_TARGET_REG_BITS 32
  30#elif __riscv_xlen == 64
  31# define TCG_TARGET_REG_BITS 64
  32#endif
  33
  34#define TCG_TARGET_INSN_UNIT_SIZE 4
  35#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
  36#define TCG_TARGET_NB_REGS 32
  37#define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
  38
  39typedef enum {
  40    TCG_REG_ZERO,
  41    TCG_REG_RA,
  42    TCG_REG_SP,
  43    TCG_REG_GP,
  44    TCG_REG_TP,
  45    TCG_REG_T0,
  46    TCG_REG_T1,
  47    TCG_REG_T2,
  48    TCG_REG_S0,
  49    TCG_REG_S1,
  50    TCG_REG_A0,
  51    TCG_REG_A1,
  52    TCG_REG_A2,
  53    TCG_REG_A3,
  54    TCG_REG_A4,
  55    TCG_REG_A5,
  56    TCG_REG_A6,
  57    TCG_REG_A7,
  58    TCG_REG_S2,
  59    TCG_REG_S3,
  60    TCG_REG_S4,
  61    TCG_REG_S5,
  62    TCG_REG_S6,
  63    TCG_REG_S7,
  64    TCG_REG_S8,
  65    TCG_REG_S9,
  66    TCG_REG_S10,
  67    TCG_REG_S11,
  68    TCG_REG_T3,
  69    TCG_REG_T4,
  70    TCG_REG_T5,
  71    TCG_REG_T6,
  72
  73    /* aliases */
  74    TCG_AREG0          = TCG_REG_S0,
  75    TCG_GUEST_BASE_REG = TCG_REG_S1,
  76    TCG_REG_TMP0       = TCG_REG_T6,
  77    TCG_REG_TMP1       = TCG_REG_T5,
  78    TCG_REG_TMP2       = TCG_REG_T4,
  79} TCGReg;
  80
  81/* used for function call generation */
  82#define TCG_REG_CALL_STACK              TCG_REG_SP
  83#define TCG_TARGET_STACK_ALIGN          16
  84#define TCG_TARGET_CALL_ALIGN_ARGS      1
  85#define TCG_TARGET_CALL_STACK_OFFSET    0
  86
  87/* optional instructions */
  88#define TCG_TARGET_HAS_movcond_i32      0
  89#define TCG_TARGET_HAS_div_i32          1
  90#define TCG_TARGET_HAS_rem_i32          1
  91#define TCG_TARGET_HAS_div2_i32         0
  92#define TCG_TARGET_HAS_rot_i32          0
  93#define TCG_TARGET_HAS_deposit_i32      0
  94#define TCG_TARGET_HAS_extract_i32      0
  95#define TCG_TARGET_HAS_sextract_i32     0
  96#define TCG_TARGET_HAS_extract2_i32     0
  97#define TCG_TARGET_HAS_add2_i32         1
  98#define TCG_TARGET_HAS_sub2_i32         1
  99#define TCG_TARGET_HAS_mulu2_i32        0
 100#define TCG_TARGET_HAS_muls2_i32        0
 101#define TCG_TARGET_HAS_muluh_i32        (TCG_TARGET_REG_BITS == 32)
 102#define TCG_TARGET_HAS_mulsh_i32        (TCG_TARGET_REG_BITS == 32)
 103#define TCG_TARGET_HAS_ext8s_i32        1
 104#define TCG_TARGET_HAS_ext16s_i32       1
 105#define TCG_TARGET_HAS_ext8u_i32        1
 106#define TCG_TARGET_HAS_ext16u_i32       1
 107#define TCG_TARGET_HAS_bswap16_i32      0
 108#define TCG_TARGET_HAS_bswap32_i32      0
 109#define TCG_TARGET_HAS_not_i32          1
 110#define TCG_TARGET_HAS_neg_i32          1
 111#define TCG_TARGET_HAS_andc_i32         0
 112#define TCG_TARGET_HAS_orc_i32          0
 113#define TCG_TARGET_HAS_eqv_i32          0
 114#define TCG_TARGET_HAS_nand_i32         0
 115#define TCG_TARGET_HAS_nor_i32          0
 116#define TCG_TARGET_HAS_clz_i32          0
 117#define TCG_TARGET_HAS_ctz_i32          0
 118#define TCG_TARGET_HAS_ctpop_i32        0
 119#define TCG_TARGET_HAS_direct_jump      0
 120#define TCG_TARGET_HAS_brcond2          1
 121#define TCG_TARGET_HAS_setcond2         1
 122#define TCG_TARGET_HAS_qemu_st8_i32     0
 123
 124#if TCG_TARGET_REG_BITS == 64
 125#define TCG_TARGET_HAS_movcond_i64      0
 126#define TCG_TARGET_HAS_div_i64          1
 127#define TCG_TARGET_HAS_rem_i64          1
 128#define TCG_TARGET_HAS_div2_i64         0
 129#define TCG_TARGET_HAS_rot_i64          0
 130#define TCG_TARGET_HAS_deposit_i64      0
 131#define TCG_TARGET_HAS_extract_i64      0
 132#define TCG_TARGET_HAS_sextract_i64     0
 133#define TCG_TARGET_HAS_extract2_i64     0
 134#define TCG_TARGET_HAS_extrl_i64_i32    1
 135#define TCG_TARGET_HAS_extrh_i64_i32    1
 136#define TCG_TARGET_HAS_ext8s_i64        1
 137#define TCG_TARGET_HAS_ext16s_i64       1
 138#define TCG_TARGET_HAS_ext32s_i64       1
 139#define TCG_TARGET_HAS_ext8u_i64        1
 140#define TCG_TARGET_HAS_ext16u_i64       1
 141#define TCG_TARGET_HAS_ext32u_i64       1
 142#define TCG_TARGET_HAS_bswap16_i64      0
 143#define TCG_TARGET_HAS_bswap32_i64      0
 144#define TCG_TARGET_HAS_bswap64_i64      0
 145#define TCG_TARGET_HAS_not_i64          1
 146#define TCG_TARGET_HAS_neg_i64          1
 147#define TCG_TARGET_HAS_andc_i64         0
 148#define TCG_TARGET_HAS_orc_i64          0
 149#define TCG_TARGET_HAS_eqv_i64          0
 150#define TCG_TARGET_HAS_nand_i64         0
 151#define TCG_TARGET_HAS_nor_i64          0
 152#define TCG_TARGET_HAS_clz_i64          0
 153#define TCG_TARGET_HAS_ctz_i64          0
 154#define TCG_TARGET_HAS_ctpop_i64        0
 155#define TCG_TARGET_HAS_add2_i64         1
 156#define TCG_TARGET_HAS_sub2_i64         1
 157#define TCG_TARGET_HAS_mulu2_i64        0
 158#define TCG_TARGET_HAS_muls2_i64        0
 159#define TCG_TARGET_HAS_muluh_i64        1
 160#define TCG_TARGET_HAS_mulsh_i64        1
 161#endif
 162
 163/* not defined -- call should be eliminated at compile time */
 164void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 165
 166#define TCG_TARGET_DEFAULT_MO (0)
 167
 168#ifdef CONFIG_SOFTMMU
 169#define TCG_TARGET_NEED_LDST_LABELS
 170#endif
 171#define TCG_TARGET_NEED_POOL_LABELS
 172
 173#define TCG_TARGET_HAS_MEMORY_BSWAP 0
 174
 175#endif
 176