LXR qemu/tests/tcg/mips/user/ase/dsp/test_dsp_r1_extrv_r

   1#include<stdio.h>
   2#include<assert.h>
   3
   4int main()
   5{
   6    int rt, rs, ach, acl, dsp;
   7    int result;
   8
   9    ach = 0x05;
  10    acl = 0xB4CB;
  11    dsp = 0x07;
  12    rs  = 0x03;
  13    result = 0xA0001699;
  14
  15    __asm
  16        ("wrdsp %1, 0x01\n\t"
  17         "mthi %3, $ac1\n\t"
  18         "mtlo %4, $ac1\n\t"
  19         "extrv_r.w %0, $ac1, %2\n\t"
  20         "rddsp %1\n\t"
  21         : "=r"(rt), "+r"(dsp)
  22         : "r"(rs), "r"(ach), "r"(acl)
  23        );
  24    dsp = (dsp >> 23) & 0x01;
  25    assert(dsp == 1);
  26    assert(result == rt);
  27
  28    /* Clear dspcontrol */
  29    dsp = 0;
  30    __asm
  31        ("wrdsp %0\n\t"
  32         :
  33         : "r"(dsp)
  34        );
  35
  36    rs = 4;
  37    ach = 0x01;
  38    acl = 0xB4CB;
  39    result = 0x10000B4D;
  40    __asm
  41        ("wrdsp %1, 0x01\n\t"
  42         "mthi %3, $ac1\n\t"
  43         "mtlo %4, $ac1\n\t"
  44         "extrv_r.w %0, $ac1, %2\n\t"
  45         "rddsp %1\n\t"
  46         : "=r"(rt), "+r"(dsp)
  47         : "r"(rs), "r"(ach), "r"(acl)
  48        );
  49    dsp = (dsp >> 23) & 0x01;
  50    assert(dsp == 0);
  51    assert(result == rt);
  52
  53    /* Clear dspcontrol */
  54    dsp = 0;
  55    __asm
  56        ("wrdsp %0\n\t"
  57         :
  58         : "r"(dsp)
  59        );
  60
  61    rs = 31;
  62    ach = 0x3fffffff;
  63    acl = 0x2bcdef01;
  64    result = 0x7ffffffe;
  65    __asm
  66        ("wrdsp %1, 0x01\n\t"
  67         "mthi %3, $ac1\n\t"
  68         "mtlo %4, $ac1\n\t"
  69         "extrv_r.w %0, $ac1, %2\n\t"
  70         "rddsp %1\n\t"
  71         : "=r"(rt), "+r"(dsp)
  72         : "r"(rs), "r"(ach), "r"(acl)
  73        );
  74    dsp = (dsp >> 23) & 0x01;
  75    assert(dsp == 0);
  76    assert(result == rt);
  77
  78    return 0;
  79}
  80