1/* 2 * MPC8xx Communication Processor Module. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * (C) Copyright 2000-2006 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * This file contains structures and information for the communication 9 * processor channels. Some CPM control and status is available 10 * throught the MPC8xx internal memory map. See immap.h for details. 11 * This file only contains what I need for the moment, not the total 12 * CPM capabilities. I (or someone else) will add definitions as they 13 * are needed. -- Dan 14 * 15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 16 * bytes of the DP RAM and relocates the I2C parameter area to the 17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 18 * or other use. 19 */ 20#ifndef __CPM_8XX__ 21#define __CPM_8XX__ 22 23#include <linux/config.h> 24#include <asm/8xx_immap.h> 25 26/* CPM Command register. 27*/ 28#define CPM_CR_RST ((ushort)0x8000) 29#define CPM_CR_OPCODE ((ushort)0x0f00) 30#define CPM_CR_CHAN ((ushort)0x00f0) 31#define CPM_CR_FLG ((ushort)0x0001) 32 33/* Some commands (there are more...later) 34*/ 35#define CPM_CR_INIT_TRX ((ushort)0x0000) 36#define CPM_CR_INIT_RX ((ushort)0x0001) 37#define CPM_CR_INIT_TX ((ushort)0x0002) 38#define CPM_CR_HUNT_MODE ((ushort)0x0003) 39#define CPM_CR_STOP_TX ((ushort)0x0004) 40#define CPM_CR_RESTART_TX ((ushort)0x0006) 41#define CPM_CR_SET_GADDR ((ushort)0x0008) 42 43/* Channel numbers. 44*/ 45#define CPM_CR_CH_SCC1 ((ushort)0x0000) 46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ 47#define CPM_CR_CH_SCC2 ((ushort)0x0004) 48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ 49#define CPM_CR_CH_SCC3 ((ushort)0x0008) 50#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ 51#define CPM_CR_CH_SCC4 ((ushort)0x000c) 52#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ 53 54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 55 56/* 57 * DPRAM defines and allocation functions 58 */ 59 60/* The dual ported RAM is multi-functional. Some areas can be (and are 61 * being) used for microcode. There is an area that can only be used 62 * as data ram for buffer descriptors, which is all we use right now. 63 * Currently the first 512 and last 256 bytes are used for microcode. 64 */ 65#ifdef CFG_ALLOC_DPRAM 66 67#define CPM_DATAONLY_BASE ((uint)0x0800) 68#define CPM_DATAONLY_SIZE ((uint)0x0700) 69#define CPM_DP_NOSPACE ((uint)0x7fffffff) 70 71#else 72 73#define CPM_SERIAL_BASE 0x0800 74#define CPM_I2C_BASE 0x0820 75#define CPM_SPI_BASE 0x0840 76#define CPM_FEC_BASE 0x0860 77#define CPM_SERIAL2_BASE 0x08E0 78#define CPM_SCC_BASE 0x0900 79#define CPM_POST_BASE 0x0980 80#define CPM_WLKBD_BASE 0x0a00 81 82#endif 83 84#ifndef CFG_CPM_POST_WORD_ADDR 85#define CPM_POST_WORD_ADDR 0x07FC 86#else 87#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR 88#endif 89 90#ifndef CFG_CPM_BOOTCOUNT_ADDR 91#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) 92#else 93#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR 94#endif 95 96#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ 97 98/* Export the base address of the communication processor registers 99 * and dual port ram. 100 */ 101extern cpm8xx_t *cpmp; /* Pointer to comm processor */ 102 103/* Buffer descriptors used by many of the CPM protocols. 104*/ 105typedef struct cpm_buf_desc { 106 ushort cbd_sc; /* Status and Control */ 107 ushort cbd_datlen; /* Data length in buffer */ 108 uint cbd_bufaddr; /* Buffer address in host memory */ 109} cbd_t; 110 111#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 112#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 113#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 114#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 115#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 116#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 117#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 118#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 119#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 120#define BD_SC_BR ((ushort)0x0020) /* Break received */ 121#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 122#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 123#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 124#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 125 126/* Parameter RAM offsets. 127*/ 128#define PROFF_SCC1 ((uint)0x0000) 129#define PROFF_IIC ((uint)0x0080) 130#define PROFF_SCC2 ((uint)0x0100) 131#define PROFF_SPI ((uint)0x0180) 132#define PROFF_SCC3 ((uint)0x0200) 133#define PROFF_SMC1 ((uint)0x0280) 134#define PROFF_SCC4 ((uint)0x0300) 135#define PROFF_SMC2 ((uint)0x0380) 136 137/* Define enough so I can at least use the serial port as a UART. 138 * The MBX uses SMC1 as the host serial port. 139 */ 140typedef struct smc_uart { 141 ushort smc_rbase; /* Rx Buffer descriptor base address */ 142 ushort smc_tbase; /* Tx Buffer descriptor base address */ 143 u_char smc_rfcr; /* Rx function code */ 144 u_char smc_tfcr; /* Tx function code */ 145 ushort smc_mrblr; /* Max receive buffer length */ 146 uint smc_rstate; /* Internal */ 147 uint smc_idp; /* Internal */ 148 ushort smc_rbptr; /* Internal */ 149 ushort smc_ibc; /* Internal */ 150 uint smc_rxtmp; /* Internal */ 151 uint smc_tstate; /* Internal */ 152 uint smc_tdp; /* Internal */ 153 ushort smc_tbptr; /* Internal */ 154 ushort smc_tbc; /* Internal */ 155 uint smc_txtmp; /* Internal */ 156 ushort smc_maxidl; /* Maximum idle characters */ 157 ushort smc_tmpidl; /* Temporary idle counter */ 158 ushort smc_brklen; /* Last received break length */ 159 ushort smc_brkec; /* rcv'd break condition counter */ 160 ushort smc_brkcr; /* xmt break count register */ 161 ushort smc_rmask; /* Temporary bit mask */ 162} smc_uart_t; 163 164/* Function code bits. 165*/ 166#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 167 168/* SMC uart mode register. 169*/ 170#define SMCMR_REN ((ushort)0x0001) 171#define SMCMR_TEN ((ushort)0x0002) 172#define SMCMR_DM ((ushort)0x000c) 173#define SMCMR_SM_GCI ((ushort)0x0000) 174#define SMCMR_SM_UART ((ushort)0x0020) 175#define SMCMR_SM_TRANS ((ushort)0x0030) 176#define SMCMR_SM_MASK ((ushort)0x0030) 177#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 178#define SMCMR_REVD SMCMR_PM_EVEN 179#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 180#define SMCMR_BS SMCMR_PEN 181#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 182#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 183#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 184 185/* SMC2 as Centronics parallel printer. It is half duplex, in that 186 * it can only receive or transmit. The parameter ram values for 187 * each direction are either unique or properly overlap, so we can 188 * include them in one structure. 189 */ 190typedef struct smc_centronics { 191 ushort scent_rbase; 192 ushort scent_tbase; 193 u_char scent_cfcr; 194 u_char scent_smask; 195 ushort scent_mrblr; 196 uint scent_rstate; 197 uint scent_r_ptr; 198 ushort scent_rbptr; 199 ushort scent_r_cnt; 200 uint scent_rtemp; 201 uint scent_tstate; 202 uint scent_t_ptr; 203 ushort scent_tbptr; 204 ushort scent_t_cnt; 205 uint scent_ttemp; 206 ushort scent_max_sl; 207 ushort scent_sl_cnt; 208 ushort scent_character1; 209 ushort scent_character2; 210 ushort scent_character3; 211 ushort scent_character4; 212 ushort scent_character5; 213 ushort scent_character6; 214 ushort scent_character7; 215 ushort scent_character8; 216 ushort scent_rccm; 217 ushort scent_rccr; 218} smc_cent_t; 219 220/* Centronics Status Mask Register. 221*/ 222#define SMC_CENT_F ((u_char)0x08) 223#define SMC_CENT_PE ((u_char)0x04) 224#define SMC_CENT_S ((u_char)0x02) 225 226/* SMC Event and Mask register. 227*/ 228#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 229#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 230#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 231#define SMCM_BSY ((unsigned char)0x04) 232#define SMCM_TX ((unsigned char)0x02) 233#define SMCM_RX ((unsigned char)0x01) 234 235/* Baud rate generators. 236*/ 237#define CPM_BRG_RST ((uint)0x00020000) 238#define CPM_BRG_EN ((uint)0x00010000) 239#define CPM_BRG_EXTC_INT ((uint)0x00000000) 240#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 241#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 242#define CPM_BRG_ATB ((uint)0x00002000) 243#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 244#define CPM_BRG_DIV16 ((uint)0x00000001) 245 246/* SI Clock Route Register 247*/ 248#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) 249#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) 250#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) 251#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) 252#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) 253#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) 254#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) 255#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) 256 257/* SCCs. 258*/ 259#define SCC_GSMRH_IRP ((uint)0x00040000) 260#define SCC_GSMRH_GDE ((uint)0x00010000) 261#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 262#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 263#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 264#define SCC_GSMRH_REVD ((uint)0x00002000) 265#define SCC_GSMRH_TRX ((uint)0x00001000) 266#define SCC_GSMRH_TTX ((uint)0x00000800) 267#define SCC_GSMRH_CDP ((uint)0x00000400) 268#define SCC_GSMRH_CTSP ((uint)0x00000200) 269#define SCC_GSMRH_CDS ((uint)0x00000100) 270#define SCC_GSMRH_CTSS ((uint)0x00000080) 271#define SCC_GSMRH_TFL ((uint)0x00000040) 272#define SCC_GSMRH_RFW ((uint)0x00000020) 273#define SCC_GSMRH_TXSY ((uint)0x00000010) 274#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 275#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 276#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 277#define SCC_GSMRH_RTSM ((uint)0x00000002) 278#define SCC_GSMRH_RSYN ((uint)0x00000001) 279 280#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 281#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 282#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 283#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 284#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 285#define SCC_GSMRL_TCI ((uint)0x10000000) 286#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 287#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 288#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 289#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 290#define SCC_GSMRL_RINV ((uint)0x02000000) 291#define SCC_GSMRL_TINV ((uint)0x01000000) 292#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 293#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 294#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 295#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 296#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 297#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 298#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 299#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 300#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 301#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 302#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 303#define SCC_GSMRL_TEND ((uint)0x00040000) 304#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 305#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 306#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 307#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 308#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 309#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 310#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 311#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 312#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 313#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 314#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 315#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 316#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 317#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 318#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 319#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 320#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 321#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 322#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 323#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 324#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 325#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 326#define SCC_GSMRL_ENR ((uint)0x00000020) 327#define SCC_GSMRL_ENT ((uint)0x00000010) 328#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 329#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 330#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 331#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 332#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 333#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 334#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 335#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 336#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 337#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 338 339#define SCC_TODR_TOD ((ushort)0x8000) 340 341/* SCC Event and Mask register. 342*/ 343#define SCCM_TXE ((unsigned char)0x10) 344#define SCCM_BSY ((unsigned char)0x04) 345#define SCCM_TX ((unsigned char)0x02) 346#define SCCM_RX ((unsigned char)0x01) 347 348typedef struct scc_param { 349 ushort scc_rbase; /* Rx Buffer descriptor base address */ 350 ushort scc_tbase; /* Tx Buffer descriptor base address */ 351 u_char scc_rfcr; /* Rx function code */ 352 u_char scc_tfcr; /* Tx function code */ 353 ushort scc_mrblr; /* Max receive buffer length */ 354 uint scc_rstate; /* Internal */ 355 uint scc_idp; /* Internal */ 356 ushort scc_rbptr; /* Internal */ 357 ushort scc_ibc; /* Internal */ 358 uint scc_rxtmp; /* Internal */ 359 uint scc_tstate; /* Internal */ 360 uint scc_tdp; /* Internal */ 361 ushort scc_tbptr; /* Internal */ 362 ushort scc_tbc; /* Internal */ 363 uint scc_txtmp; /* Internal */ 364 uint scc_rcrc; /* Internal */ 365 uint scc_tcrc; /* Internal */ 366} sccp_t; 367 368/* Function code bits. 369*/ 370#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 371 372/* CPM Ethernet through SCCx. 373 */ 374typedef struct scc_enet { 375 sccp_t sen_genscc; 376 uint sen_cpres; /* Preset CRC */ 377 uint sen_cmask; /* Constant mask for CRC */ 378 uint sen_crcec; /* CRC Error counter */ 379 uint sen_alec; /* alignment error counter */ 380 uint sen_disfc; /* discard frame counter */ 381 ushort sen_pads; /* Tx short frame pad character */ 382 ushort sen_retlim; /* Retry limit threshold */ 383 ushort sen_retcnt; /* Retry limit counter */ 384 ushort sen_maxflr; /* maximum frame length register */ 385 ushort sen_minflr; /* minimum frame length register */ 386 ushort sen_maxd1; /* maximum DMA1 length */ 387 ushort sen_maxd2; /* maximum DMA2 length */ 388 ushort sen_maxd; /* Rx max DMA */ 389 ushort sen_dmacnt; /* Rx DMA counter */ 390 ushort sen_maxb; /* Max BD byte count */ 391 ushort sen_gaddr1; /* Group address filter */ 392 ushort sen_gaddr2; 393 ushort sen_gaddr3; 394 ushort sen_gaddr4; 395 uint sen_tbuf0data0; /* Save area 0 - current frame */ 396 uint sen_tbuf0data1; /* Save area 1 - current frame */ 397 uint sen_tbuf0rba; /* Internal */ 398 uint sen_tbuf0crc; /* Internal */ 399 ushort sen_tbuf0bcnt; /* Internal */ 400 ushort sen_paddrh; /* physical address (MSB) */ 401 ushort sen_paddrm; 402 ushort sen_paddrl; /* physical address (LSB) */ 403 ushort sen_pper; /* persistence */ 404 ushort sen_rfbdptr; /* Rx first BD pointer */ 405 ushort sen_tfbdptr; /* Tx first BD pointer */ 406 ushort sen_tlbdptr; /* Tx last BD pointer */ 407 uint sen_tbuf1data0; /* Save area 0 - current frame */ 408 uint sen_tbuf1data1; /* Save area 1 - current frame */ 409 uint sen_tbuf1rba; /* Internal */ 410 uint sen_tbuf1crc; /* Internal */ 411 ushort sen_tbuf1bcnt; /* Internal */ 412 ushort sen_txlen; /* Tx Frame length counter */ 413 ushort sen_iaddr1; /* Individual address filter */ 414 ushort sen_iaddr2; 415 ushort sen_iaddr3; 416 ushort sen_iaddr4; 417 ushort sen_boffcnt; /* Backoff counter */ 418 419 /* NOTE: Some versions of the manual have the following items 420 * incorrectly documented. Below is the proper order. 421 */ 422 ushort sen_taddrh; /* temp address (MSB) */ 423 ushort sen_taddrm; 424 ushort sen_taddrl; /* temp address (LSB) */ 425} scc_enet_t; 426 427/********************************************************************** 428 * 429 * Board specific configuration settings. 430 * 431 * Please note that we use the presence of a #define SCC_ENET and/or 432 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. 433 **********************************************************************/ 434 435 436/*** ADS *************************************************************/ 437 438#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) 439/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. 440 */ 441 442#define PROFF_ENET PROFF_SCC1 443#define CPM_CR_ENET CPM_CR_CH_SCC1 444#define SCC_ENET 0 445 446#define PA_ENET_RXD ((ushort)0x0001) 447#define PA_ENET_TXD ((ushort)0x0002) 448#define PA_ENET_TCLK ((ushort)0x0100) 449#define PA_ENET_RCLK ((ushort)0x0200) 450 451#define PB_ENET_TENA ((uint)0x00001000) 452 453#define PC_ENET_CLSN ((ushort)0x0010) 454#define PC_ENET_RENA ((ushort)0x0020) 455 456#define SICR_ENET_MASK ((uint)0x000000ff) 457#define SICR_ENET_CLKRT ((uint)0x0000002c) 458 459/* 68160 PHY control */ 460 461#define PC_ENET_ETHLOOP ((ushort)0x0800) 462#define PC_ENET_TPFLDL ((ushort)0x0400) 463#define PC_ENET_TPSQEL ((ushort)0x0200) 464 465#endif /* MPC860ADS */ 466 467/*** AMX860 **********************************************/ 468 469#if defined(CONFIG_AMX860) 470 471/* This ENET stuff is for the AMX860 with ethernet on SCC1. 472 */ 473 474#define PROFF_ENET PROFF_SCC1 475#define CPM_CR_ENET CPM_CR_CH_SCC1 476#define SCC_ENET 0 477 478#define PA_ENET_RXD ((ushort)0x0001) 479#define PA_ENET_TXD ((ushort)0x0002) 480#define PA_ENET_TCLK ((ushort)0x0400) 481#define PA_ENET_RCLK ((ushort)0x0800) 482 483#define PB_ENET_TENA ((uint)0x00001000) 484 485#define PC_ENET_CLSN ((ushort)0x0010) 486#define PC_ENET_RENA ((ushort)0x0020) 487 488#define SICR_ENET_MASK ((uint)0x000000ff) 489#define SICR_ENET_CLKRT ((uint)0x0000003e) 490 491/* 68160 PHY control */ 492 493#define PB_ENET_ETHLOOP ((uint)0x00020000) 494#define PB_ENET_TPFLDL ((uint)0x00010000) 495#define PB_ENET_TPSQEL ((uint)0x00008000) 496#define PD_ENET_ETH_EN ((ushort)0x0004) 497 498#endif /* CONFIG_AMX860 */ 499 500/*** BSEIP **********************************************************/ 501 502#ifdef CONFIG_BSEIP 503/* This ENET stuff is for the MPC823 with ethernet on SCC2. 504 * This is unique to the BSE ip-Engine board. 505 */ 506#define PROFF_ENET PROFF_SCC2 507#define CPM_CR_ENET CPM_CR_CH_SCC2 508#define SCC_ENET 1 509#define PA_ENET_RXD ((ushort)0x0004) 510#define PA_ENET_TXD ((ushort)0x0008) 511#define PA_ENET_TCLK ((ushort)0x0100) 512#define PA_ENET_RCLK ((ushort)0x0200) 513#define PB_ENET_TENA ((uint)0x00002000) 514#define PC_ENET_CLSN ((ushort)0x0040) 515#define PC_ENET_RENA ((ushort)0x0080) 516 517/* BSE uses port B and C bits for PHY control also. 518*/ 519#define PB_BSE_POWERUP ((uint)0x00000004) 520#define PB_BSE_FDXDIS ((uint)0x00008000) 521#define PC_BSE_LOOPBACK ((ushort)0x0800) 522 523#define SICR_ENET_MASK ((uint)0x0000ff00) 524#define SICR_ENET_CLKRT ((uint)0x00002c00) 525#endif /* CONFIG_BSEIP */ 526 527/*** BSEIP **********************************************************/ 528 529#ifdef CONFIG_FLAGADM 530/* Enet configuration for the FLAGADM */ 531/* Enet on SCC2 */ 532 533#define PROFF_ENET PROFF_SCC2 534#define CPM_CR_ENET CPM_CR_CH_SCC2 535#define SCC_ENET 1 536#define PA_ENET_RXD ((ushort)0x0004) 537#define PA_ENET_TXD ((ushort)0x0008) 538#define PA_ENET_TCLK ((ushort)0x0100) 539#define PA_ENET_RCLK ((ushort)0x0400) 540#define PB_ENET_TENA ((uint)0x00002000) 541#define PC_ENET_CLSN ((ushort)0x0040) 542#define PC_ENET_RENA ((ushort)0x0080) 543 544#define SICR_ENET_MASK ((uint)0x0000ff00) 545#define SICR_ENET_CLKRT ((uint)0x00003400) 546#endif /* CONFIG_FLAGADM */ 547 548/*** C2MON **********************************************************/ 549 550#ifdef CONFIG_C2MON 551 552# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ 553# error "Ethernet on SCC not supported on C2MON Board!" 554# else /* Use FEC for Fast Ethernet */ 555 556#undef SCC_ENET 557#define FEC_ENET 558 559#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 560#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 561#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 562#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 563#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 564#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 565#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 566#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 567#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 568#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 569#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 570#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 571#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 572 573#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 574 575# endif /* CONFIG_FEC_ENET */ 576#endif /* CONFIG_C2MON */ 577 578/*********************************************************************/ 579 580 581/*** CCM and PCU E ***********************************************/ 582 583/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ 584 585#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) 586 587#define FEC_ENET /* use FEC for EThernet */ 588#undef SCC_ENET 589 590#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 591#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 592#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 593#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 594#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 595#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 596#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 597#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 598#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 599#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 600#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 601#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 602#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 603 604#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 605 606#endif /* CONFIG_PCU_E, CONFIG_CCM */ 607 608/*** ELPT860 *********************************************************/ 609 610#ifdef CONFIG_ELPT860 611/* Bits in parallel I/O port registers that have to be set/cleared 612 * to configure the pins for SCC1 use. 613 */ 614# define PROFF_ENET PROFF_SCC1 615# define CPM_CR_ENET CPM_CR_CH_SCC1 616# define SCC_ENET 0 617 618# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 619# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 620# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 621# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ 622 623# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 624# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 625# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 626 627/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to 628 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 629 */ 630# define SICR_ENET_MASK ((uint)0x000000FF) 631# define SICR_ENET_CLKRT ((uint)0x00000025) 632#endif /* CONFIG_ELPT860 */ 633 634/*** ESTEEM 192E **************************************************/ 635#ifdef CONFIG_ESTEEM192E 636/* ESTEEM192E 637 * This ENET stuff is for the MPC850 with ethernet on SCC2. This 638 * is very similar to the RPX-Lite configuration. 639 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. 640 */ 641 642#define PROFF_ENET PROFF_SCC2 643#define CPM_CR_ENET CPM_CR_CH_SCC2 644#define SCC_ENET 1 645 646#define PA_ENET_RXD ((ushort)0x0004) 647#define PA_ENET_TXD ((ushort)0x0008) 648#define PA_ENET_TCLK ((ushort)0x0200) 649#define PA_ENET_RCLK ((ushort)0x0800) 650#define PB_ENET_TENA ((uint)0x00002000) 651#define PC_ENET_CLSN ((ushort)0x0040) 652#define PC_ENET_RENA ((ushort)0x0080) 653 654#define SICR_ENET_MASK ((uint)0x0000ff00) 655#define SICR_ENET_CLKRT ((uint)0x00003d00) 656 657#define PB_ENET_LOOPBACK ((uint)0x00004000) 658#define PB_ENET_FDPLEX_DIS ((uint)0x00008000) 659 660#endif 661 662/*** FADS823 ********************************************************/ 663 664#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) 665/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. 666 */ 667#ifdef CONFIG_SCC2_ENET 668#define PROFF_ENET PROFF_SCC2 669#define CPM_CR_ENET CPM_CR_CH_SCC2 670#define SCC_ENET 1 671#define CPMVEC_ENET CPMVEC_SCC2 672#endif 673 674#ifdef CONFIG_SCC1_ENET 675#define PROFF_ENET PROFF_SCC1 676#define CPM_CR_ENET CPM_CR_CH_SCC1 677#define SCC_ENET 0 678#define CPMVEC_ENET CPMVEC_SCC1 679#endif 680 681#define PA_ENET_RXD ((ushort)0x0004) 682#define PA_ENET_TXD ((ushort)0x0008) 683#define PA_ENET_TCLK ((ushort)0x0400) 684#define PA_ENET_RCLK ((ushort)0x0200) 685 686#define PB_ENET_TENA ((uint)0x00002000) 687 688#define PC_ENET_CLSN ((ushort)0x0040) 689#define PC_ENET_RENA ((ushort)0x0080) 690 691#define SICR_ENET_MASK ((uint)0x0000ff00) 692#define SICR_ENET_CLKRT ((uint)0x00002e00) 693 694#endif /* CONFIG_FADS823FADS */ 695 696/*** FADS850SAR ********************************************************/ 697 698#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) 699/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of 700 * this may be unique to the FADS850SAR configuration. 701 * Note TENA is on Port B. 702 */ 703#define PROFF_ENET PROFF_SCC2 704#define CPM_CR_ENET CPM_CR_CH_SCC2 705#define SCC_ENET 1 706#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 707#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 708#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 709#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 710#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 711#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 712#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 713 714#define SICR_ENET_MASK ((uint)0x0000ff00) 715#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ 716#endif /* CONFIG_FADS850SAR */ 717 718/*** FADS860T********************************************************/ 719 720#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) 721/* 722 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. 723 */ 724#ifdef CONFIG_SCC1_ENET 725 726#define SCC_ENET 0 727 728#define PROFF_ENET PROFF_SCC1 729#define CPM_CR_ENET CPM_CR_CH_SCC1 730 731#define PA_ENET_RXD ((ushort)0x0001) 732#define PA_ENET_TXD ((ushort)0x0002) 733#define PA_ENET_TCLK ((ushort)0x0100) 734#define PA_ENET_RCLK ((ushort)0x0200) 735 736#define PB_ENET_TENA ((uint)0x00001000) 737 738#define PC_ENET_CLSN ((ushort)0x0010) 739#define PC_ENET_RENA ((ushort)0x0020) 740 741#define SICR_ENET_MASK ((uint)0x000000ff) 742#define SICR_ENET_CLKRT ((uint)0x0000002c) 743 744#endif /* CONFIG_SCC1_ETHERNET */ 745 746/* 747 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS 748 * with ethernet on FEC. 749 */ 750 751#ifdef CONFIG_FEC_ENET 752#define FEC_ENET /* Use FEC for Ethernet */ 753#endif /* CONFIG_FEC_ENET */ 754 755#endif /* CONFIG_FADS && CONFIG_MPC86x */ 756 757/*** FPS850L, FPS860L ************************************************/ 758 759#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) 760/* Bits in parallel I/O port registers that have to be set/cleared 761 * to configure the pins for SCC2 use. 762 */ 763#define PROFF_ENET PROFF_SCC2 764#define CPM_CR_ENET CPM_CR_CH_SCC2 765#define SCC_ENET 1 766#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 767#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 768#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 769#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 770 771#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ 772#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 773#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 774 775/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 776 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 777 */ 778#define SICR_ENET_MASK ((uint)0x0000ff00) 779#define SICR_ENET_CLKRT ((uint)0x00002600) 780#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ 781 782/*** GEN860T **********************************************************/ 783#if defined(CONFIG_GEN860T) 784#undef SCC_ENET 785#define FEC_ENET 786 787#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 788#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 789#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 790#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 791#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 792#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 793#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 794#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 795#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 796#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 797#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 798#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 799#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 800#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ 801#endif /* CONFIG_GEN860T */ 802 803/*** GENIETV ********************************************************/ 804 805#if defined(CONFIG_GENIETV) 806/* Ethernet is only on SCC2 */ 807 808#define CONFIG_SCC2_ENET 809#define PROFF_ENET PROFF_SCC2 810#define CPM_CR_ENET CPM_CR_CH_SCC2 811#define SCC_ENET 1 812#define CPMVEC_ENET CPMVEC_SCC2 813 814#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 815#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 816#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 817#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 818 819#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 820 821#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 822#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 823 824#define SICR_ENET_MASK ((uint)0x0000ff00) 825#define SICR_ENET_CLKRT ((uint)0x00002e00) 826 827#endif /* CONFIG_GENIETV */ 828 829/*** GTH ******************************************************/ 830 831#ifdef CONFIG_GTH 832#ifdef CONFIG_FEC_ENET 833#define FEC_ENET /* use FEC for EThernet */ 834#endif /* CONFIG_FEC_ETHERNET */ 835 836/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ 837#define PROFF_ENET PROFF_SCC1 838#define CPM_CR_ENET CPM_CR_CH_SCC1 839#define SCC_ENET 0 840 841#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ 842#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ 843#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ 844#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */ 845 846#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ 847 848#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ 849#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ 850 851/* NOTE. This is reset for 10Mbit port only */ 852#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */ 853 854#define SICR_ENET_MASK ((uint)0x000000ff) 855 856/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */ 857#define SICR_ENET_CLKRT ((uint)0x00000037) 858 859#endif /* CONFIG_GTH */ 860 861/*** HERMES-PRO ******************************************************/ 862 863/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ 864 865#ifdef CONFIG_HERMES 866 867#define FEC_ENET /* use FEC for EThernet */ 868#undef SCC_ENET 869 870 871#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 872#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 873#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 874#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 875#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 876#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 877#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 878#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 879#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 880#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 881#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 882#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 883#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 884 885#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 886 887#endif /* CONFIG_HERMES */ 888 889/*** IAD210 **********************************************************/ 890 891/* The IAD210 uses the FEC on a MPC860P for Ethernet */ 892 893#if defined(CONFIG_IAD210) 894 895# define FEC_ENET /* use FEC for Ethernet */ 896# undef SCC_ENET 897 898# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ 899# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ 900# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ 901# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ 902# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ 903# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ 904# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ 905# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ 906# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ 907# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ 908# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ 909# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ 910# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ 911 912# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ 913 914#endif /* CONFIG_IAD210 */ 915 916/*** ICU862 **********************************************************/ 917 918#if defined(CONFIG_ICU862) 919 920#ifdef CONFIG_FEC_ENET 921#define FEC_ENET /* use FEC for EThernet */ 922#endif /* CONFIG_FEC_ETHERNET */ 923 924#endif /* CONFIG_ICU862 */ 925 926/*** IP860 **********************************************************/ 927 928#if defined(CONFIG_IP860) 929/* Bits in parallel I/O port registers that have to be set/cleared 930 * to configure the pins for SCC1 use. 931 */ 932#define PROFF_ENET PROFF_SCC1 933#define CPM_CR_ENET CPM_CR_CH_SCC1 934#define SCC_ENET 0 935#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 936#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 937#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 938#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ 939 940#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 941#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 942#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 943 944#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ 945#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ 946 947/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 948 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 949 */ 950#define SICR_ENET_MASK ((uint)0x000000ff) 951#define SICR_ENET_CLKRT ((uint)0x0000002C) 952#endif /* CONFIG_IP860 */ 953 954/*** IVMS8 **********************************************************/ 955 956/* The IVMS8 uses the FEC on a MPC860T for Ethernet */ 957 958#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) 959 960#define FEC_ENET /* use FEC for EThernet */ 961#undef SCC_ENET 962 963#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 964 965#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 966 967#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 968#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 969#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 970#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 971#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 972#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 973#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 974#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 975#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 976#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 977#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 978#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 979#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 980 981#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 982 983#endif /* CONFIG_IVMS8, CONFIG_IVML24 */ 984 985/*** KUP4K, KUP4X ****************************************************/ 986/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ 987 988#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 989 990#define FEC_ENET /* use FEC for EThernet */ 991#undef SCC_ENET 992 993#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 994 995#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 996 997#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 998#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 999#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1000#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1001#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1002#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1003#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1004#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1005#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1006#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1007#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1008#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1009#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1010 1011#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1012 1013#endif /* CONFIG_KUP4K */ 1014 1015 1016/*** LANTEC *********************************************************/ 1017 1018#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 1019/* Bits in parallel I/O port registers that have to be set/cleared 1020 * to configure the pins for SCC2 use. 1021 */ 1022#define PROFF_ENET PROFF_SCC2 1023#define CPM_CR_ENET CPM_CR_CH_SCC2 1024#define SCC_ENET 1 1025#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1026#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1027#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1028#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1029 1030#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1031 1032#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ 1033#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1034#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1035 1036/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1037 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1038 */ 1039#define SICR_ENET_MASK ((uint)0x0000FF00) 1040#define SICR_ENET_CLKRT ((uint)0x00002E00) 1041#endif /* CONFIG_LANTEC v2 */ 1042 1043/*** LWMON **********************************************************/ 1044 1045#if defined(CONFIG_LWMON) 1046/* Bits in parallel I/O port registers that have to be set/cleared 1047 * to configure the pins for SCC2 use. 1048 */ 1049#define PROFF_ENET PROFF_SCC2 1050#define CPM_CR_ENET CPM_CR_CH_SCC2 1051#define SCC_ENET 1 1052#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1053#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1054#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ 1055#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1056 1057#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1058 1059#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1060#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1061 1062/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to 1063 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1064 */ 1065#define SICR_ENET_MASK ((uint)0x0000ff00) 1066#define SICR_ENET_CLKRT ((uint)0x00003E00) 1067#endif /* CONFIG_LWMON */ 1068 1069/*** NX823 ***********************************************/ 1070 1071#if defined(CONFIG_NX823) 1072/* Bits in parallel I/O port registers that have to be set/cleared 1073 * to configure the pins for SCC1 use. 1074 */ 1075#define PROFF_ENET PROFF_SCC2 1076#define CPM_CR_ENET CPM_CR_CH_SCC2 1077#define SCC_ENET 1 1078#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1079#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1080#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1081#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1082 1083#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1084 1085#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1086#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1087 1088/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1089 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1090 */ 1091#define SICR_ENET_MASK ((uint)0x0000ff00) 1092#define SICR_ENET_CLKRT ((uint)0x00002f00) 1093 1094#endif /* CONFIG_NX823 */ 1095 1096/*** MBX ************************************************************/ 1097 1098#ifdef CONFIG_MBX 1099/* Bits in parallel I/O port registers that have to be set/cleared 1100 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique 1101 * to the MBX860 board. Any two of the four available clocks could be 1102 * used, and the MPC860 cookbook manual has an example using different 1103 * clock pins. 1104 */ 1105#define PROFF_ENET PROFF_SCC1 1106#define CPM_CR_ENET CPM_CR_CH_SCC1 1107#define SCC_ENET 0 1108#define PA_ENET_RXD ((ushort)0x0001) 1109#define PA_ENET_TXD ((ushort)0x0002) 1110#define PA_ENET_TCLK ((ushort)0x0200) 1111#define PA_ENET_RCLK ((ushort)0x0800) 1112#define PC_ENET_TENA ((ushort)0x0001) 1113#define PC_ENET_CLSN ((ushort)0x0010) 1114#define PC_ENET_RENA ((ushort)0x0020) 1115 1116/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1117 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1118 */ 1119#define SICR_ENET_MASK ((uint)0x000000ff) 1120#define SICR_ENET_CLKRT ((uint)0x0000003d) 1121#endif /* CONFIG_MBX */ 1122 1123/*** MHPC ********************************************************/ 1124 1125#if defined(CONFIG_MHPC) 1126/* This ENET stuff is for the MHPC with ethernet on SCC2. 1127 * Note TENA is on Port B. 1128 */ 1129#define PROFF_ENET PROFF_SCC2 1130#define CPM_CR_ENET CPM_CR_CH_SCC2 1131#define SCC_ENET 1 1132#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1133#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1134#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1135#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1136#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1137#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1138#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1139 1140#define SICR_ENET_MASK ((uint)0x0000ff00) 1141#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ 1142#endif /* CONFIG_MHPC */ 1143 1144/*** NETVIA *******************************************************/ 1145 1146/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ 1147#if ( defined CONFIG_SVM_SC8xx ) 1148# ifndef CONFIG_FEC_ENET 1149 1150#define PROFF_ENET PROFF_SCC2 1151#define CPM_CR_ENET CPM_CR_CH_SCC2 1152#define SCC_ENET 1 1153 1154 /* Bits in parallel I/O port registers that have to be set/cleared 1155 * * * * to configure the pins for SCC2 use. 1156 * * * */ 1157#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1158#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1159#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ 1160#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1161 1162#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1163 1164#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1165#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1166/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1167 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1168 * * * */ 1169#define SICR_ENET_MASK ((uint)0x0000ff00) 1170#define SICR_ENET_CLKRT ((uint)0x00003700) 1171 1172# else /* Use FEC for Fast Ethernet */ 1173 1174#undef SCC_ENET 1175#define FEC_ENET 1176 1177#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1178#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1179#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1180#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1181#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1182#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1183#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1184#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1185#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1186#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1187#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1188#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1189#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1190 1191#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1192 1193# endif /* CONFIG_FEC_ENET */ 1194#endif /* CONFIG_SVM_SC8xx */ 1195 1196 1197#if defined(CONFIG_NETVIA) 1198/* Bits in parallel I/O port registers that have to be set/cleared 1199 * to configure the pins for SCC2 use. 1200 */ 1201#define PROFF_ENET PROFF_SCC2 1202#define CPM_CR_ENET CPM_CR_CH_SCC2 1203#define SCC_ENET 1 1204#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1205#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1206#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1207#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1208 1209#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 1210# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ 1211#elif CONFIG_NETVIA_VERSION >= 2 1212# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ 1213#endif 1214 1215#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ 1216 1217#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1218#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1219 1220/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1221 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1222 */ 1223#define SICR_ENET_MASK ((uint)0x0000ff00) 1224#define SICR_ENET_CLKRT ((uint)0x00002f00) 1225 1226#endif /* CONFIG_NETVIA */ 1227 1228/*** QS850/QS823 ***************************************************/ 1229 1230#if defined(CONFIG_QS850) || defined(CONFIG_QS823) 1231#undef FEC_ENET /* Don't use FEC for EThernet */ 1232 1233#define PROFF_ENET PROFF_SCC2 1234#define CPM_CR_ENET CPM_CR_CH_SCC2 1235#define SCC_ENET 1 1236 1237#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ 1238#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ 1239#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ 1240#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ 1241#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ 1242#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ 1243#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ 1244#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ 1245#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ 1246#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ 1247 1248/* SCC2 TXCLK from CLK2 1249 * SCC2 RXCLK from CLK4 1250 * SCC2 Connected to NMSI */ 1251#define SICR_ENET_MASK ((uint)0x00007F00) 1252#define SICR_ENET_CLKRT ((uint)0x00003D00) 1253 1254#endif /* CONFIG_QS850/QS823 */ 1255 1256/*** QS860T ***************************************************/ 1257 1258#ifdef CONFIG_QS860T 1259#ifdef CONFIG_FEC_ENET 1260#define FEC_ENET /* use FEC for EThernet */ 1261#endif /* CONFIG_FEC_ETHERNET */ 1262 1263/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ 1264#define PROFF_ENET PROFF_SCC1 1265#define CPM_CR_ENET CPM_CR_CH_SCC1 1266#define SCC_ENET 0 1267 1268#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ 1269#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ 1270#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ 1271#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ 1272#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ 1273#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ 1274#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ 1275 1276#define SICR_ENET_MASK ((uint)0x000000ff) 1277/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ 1278#define SICR_ENET_CLKRT ((uint)0x0000003D) 1279 1280#endif /* CONFIG_QS860T */ 1281 1282/*** RPXCLASSIC *****************************************************/ 1283 1284#ifdef CONFIG_RPXCLASSIC 1285 1286#ifdef CONFIG_FEC_ENET 1287 1288# define FEC_ENET /* use FEC for EThernet */ 1289# undef SCC_ENET 1290 1291#else /* ! CONFIG_FEC_ENET */ 1292 1293/* Bits in parallel I/O port registers that have to be set/cleared 1294 * to configure the pins for SCC1 use. 1295 */ 1296#define PROFF_ENET PROFF_SCC1 1297#define CPM_CR_ENET CPM_CR_CH_SCC1 1298#define SCC_ENET 0 1299#define PA_ENET_RXD ((ushort)0x0001) 1300#define PA_ENET_TXD ((ushort)0x0002) 1301#define PA_ENET_TCLK ((ushort)0x0200) 1302#define PA_ENET_RCLK ((ushort)0x0800) 1303#define PB_ENET_TENA ((uint)0x00001000) 1304#define PC_ENET_CLSN ((ushort)0x0010) 1305#define PC_ENET_RENA ((ushort)0x0020) 1306 1307/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1308 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1309 */ 1310#define SICR_ENET_MASK ((uint)0x000000ff) 1311#define SICR_ENET_CLKRT ((uint)0x0000003d) 1312 1313#endif /* CONFIG_FEC_ENET */ 1314 1315#endif /* CONFIG_RPXCLASSIC */ 1316 1317/*** RPXLITE ********************************************************/ 1318 1319#ifdef CONFIG_RPXLITE 1320/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of 1321 * this may be unique to the RPX-Lite configuration. 1322 * Note TENA is on Port B. 1323 */ 1324#define PROFF_ENET PROFF_SCC2 1325#define CPM_CR_ENET CPM_CR_CH_SCC2 1326#define SCC_ENET 1 1327#define PA_ENET_RXD ((ushort)0x0004) 1328#define PA_ENET_TXD ((ushort)0x0008) 1329#define PA_ENET_TCLK ((ushort)0x0200) 1330#define PA_ENET_RCLK ((ushort)0x0800) 1331#if defined(CONFIG_RMU) 1332#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ 1333#else 1334#define PB_ENET_TENA ((uint)0x00002000) 1335#endif 1336#define PC_ENET_CLSN ((ushort)0x0040) 1337#define PC_ENET_RENA ((ushort)0x0080) 1338 1339#define SICR_ENET_MASK ((uint)0x0000ff00) 1340#define SICR_ENET_CLKRT ((uint)0x00003d00) 1341#endif /* CONFIG_RPXLITE */ 1342 1343/*** SM850 *********************************************************/ 1344 1345/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ 1346 1347#ifdef CONFIG_SM850 1348#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ 1349#define CPM_CR_ENET CPM_CR_CH_SCC3 1350#define SCC_ENET 2 1351#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ 1352#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ 1353#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1354#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1355 1356#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1357#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ 1358 1359#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ 1360#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ 1361 1362/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1363 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. 1364 */ 1365#define SICR_ENET_MASK ((uint)0x00FF0000) 1366#define SICR_ENET_CLKRT ((uint)0x00260000) 1367#endif /* CONFIG_SM850 */ 1368 1369/*** SPD823TS ******************************************************/ 1370 1371#ifdef CONFIG_SPD823TS 1372/* Bits in parallel I/O port registers that have to be set/cleared 1373 * to configure the pins for SCC2 use. 1374 */ 1375#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ 1376#define CPM_CR_ENET CPM_CR_CH_SCC2 1377#define SCC_ENET 1 1378#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ 1379#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ 1380#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1381#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1382#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1383#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1384 1385#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1386 1387#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1388#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1389#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ 1390 1391/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1392 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1393 */ 1394#define SICR_ENET_MASK ((uint)0x0000ff00) 1395#define SICR_ENET_CLKRT ((uint)0x00002E00) 1396#endif /* CONFIG_SPD823TS */ 1397 1398/*** SXNI855T ******************************************************/ 1399 1400#if defined(CONFIG_SXNI855T) 1401 1402#ifdef CONFIG_FEC_ENET 1403#define FEC_ENET /* use FEC for Ethernet */ 1404#endif /* CONFIG_FEC_ETHERNET */ 1405 1406#endif /* CONFIG_SXNI855T */ 1407 1408/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ 1409 1410#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ 1411 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ 1412 defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ 1413 defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ 1414 defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ 1415 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ 1416 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) 1417 1418/* Bits in parallel I/O port registers that have to be set/cleared 1419 * to configure the pins for SCC2 use. 1420 */ 1421#define PROFF_ENET PROFF_SCC2 1422#define CPM_CR_ENET CPM_CR_CH_SCC2 1423#define SCC_ENET 1 1424#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1425#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1426#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1427#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1428 1429#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1430 1431#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1432#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1433#if defined(CONFIG_R360MPI) 1434#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1435#endif /* CONFIG_R360MPI */ 1436 1437/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1438 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1439 */ 1440#define SICR_ENET_MASK ((uint)0x0000ff00) 1441#define SICR_ENET_CLKRT ((uint)0x00002600) 1442 1443# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1444#define FEC_ENET 1445# endif /* CONFIG_FEC_ENET */ 1446 1447#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ 1448 1449/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ 1450 1451#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ 1452 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ 1453 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ 1454 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) 1455 1456# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ 1457 1458/* Bits in parallel I/O port registers that have to be set/cleared 1459 * to configure the pins for SCC1 use. 1460 */ 1461#define PROFF_ENET PROFF_SCC1 1462#define CPM_CR_ENET CPM_CR_CH_SCC1 1463#define SCC_ENET 0 1464#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 1465#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 1466#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1467#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1468 1469#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 1470#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 1471#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 1472 1473/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1474 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1475 */ 1476#define SICR_ENET_MASK ((uint)0x000000ff) 1477#define SICR_ENET_CLKRT ((uint)0x00000026) 1478 1479# endif /* CONFIG_SCC1_ENET */ 1480 1481# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1482 1483#define FEC_ENET 1484 1485#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1486#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1487#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1488#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1489#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1490#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1491#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1492#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1493#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1494#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1495#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1496#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1497#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1498 1499#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1500 1501# endif /* CONFIG_FEC_ENET */ 1502#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ 1503 1504/*** V37 **********************************************************/ 1505 1506#ifdef CONFIG_V37 1507/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of 1508 * this may be unique to the Marel V37 configuration. 1509 * Note TENA is on Port B. 1510 */ 1511#define PROFF_ENET PROFF_SCC2 1512#define CPM_CR_ENET CPM_CR_CH_SCC2 1513#define SCC_ENET 1 1514#define PA_ENET_RXD ((ushort)0x0004) 1515#define PA_ENET_TXD ((ushort)0x0008) 1516#define PA_ENET_TCLK ((ushort)0x0400) 1517#define PA_ENET_RCLK ((ushort)0x0200) 1518#define PB_ENET_TENA ((uint)0x00002000) 1519#define PC_ENET_CLSN ((ushort)0x0040) 1520#define PC_ENET_RENA ((ushort)0x0080) 1521 1522#define SICR_ENET_MASK ((uint)0x0000ff00) 1523#define SICR_ENET_CLKRT ((uint)0x00002e00) 1524#endif /* CONFIG_V37 */ 1525 1526 1527/*********************************************************************/ 1528 1529/* SCC Event register as used by Ethernet. 1530*/ 1531#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 1532#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 1533#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 1534#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 1535#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 1536#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 1537 1538/* SCC Mode Register (PSMR) as used by Ethernet. 1539*/ 1540#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 1541#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 1542#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 1543#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 1544#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 1545#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 1546#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 1547#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 1548#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 1549#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 1550#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 1551#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 1552#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 1553 1554/* Buffer descriptor control/status used by Ethernet receive. 1555*/ 1556#define BD_ENET_RX_EMPTY ((ushort)0x8000) 1557#define BD_ENET_RX_WRAP ((ushort)0x2000) 1558#define BD_ENET_RX_INTR ((ushort)0x1000) 1559#define BD_ENET_RX_LAST ((ushort)0x0800) 1560#define BD_ENET_RX_FIRST ((ushort)0x0400) 1561#define BD_ENET_RX_MISS ((ushort)0x0100) 1562#define BD_ENET_RX_LG ((ushort)0x0020) 1563#define BD_ENET_RX_NO ((ushort)0x0010) 1564#define BD_ENET_RX_SH ((ushort)0x0008) 1565#define BD_ENET_RX_CR ((ushort)0x0004) 1566#define BD_ENET_RX_OV ((ushort)0x0002) 1567#define BD_ENET_RX_CL ((ushort)0x0001) 1568#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 1569 1570/* Buffer descriptor control/status used by Ethernet transmit. 1571*/ 1572#define BD_ENET_TX_READY ((ushort)0x8000) 1573#define BD_ENET_TX_PAD ((ushort)0x4000) 1574#define BD_ENET_TX_WRAP ((ushort)0x2000) 1575#define BD_ENET_TX_INTR ((ushort)0x1000) 1576#define BD_ENET_TX_LAST ((ushort)0x0800) 1577#define BD_ENET_TX_TC ((ushort)0x0400) 1578#define BD_ENET_TX_DEF ((ushort)0x0200) 1579#define BD_ENET_TX_HB ((ushort)0x0100) 1580#define BD_ENET_TX_LC ((ushort)0x0080) 1581#define BD_ENET_TX_RL ((ushort)0x0040) 1582#define BD_ENET_TX_RCMASK ((ushort)0x003c) 1583#define BD_ENET_TX_UN ((ushort)0x0002) 1584#define BD_ENET_TX_CSL ((ushort)0x0001) 1585#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 1586 1587/* SCC as UART 1588*/ 1589typedef struct scc_uart { 1590 sccp_t scc_genscc; 1591 uint scc_res1; /* Reserved */ 1592 uint scc_res2; /* Reserved */ 1593 ushort scc_maxidl; /* Maximum idle chars */ 1594 ushort scc_idlc; /* temp idle counter */ 1595 ushort scc_brkcr; /* Break count register */ 1596 ushort scc_parec; /* receive parity error counter */ 1597 ushort scc_frmec; /* receive framing error counter */ 1598 ushort scc_nosec; /* receive noise counter */ 1599 ushort scc_brkec; /* receive break condition counter */ 1600 ushort scc_brkln; /* last received break length */ 1601 ushort scc_uaddr1; /* UART address character 1 */ 1602 ushort scc_uaddr2; /* UART address character 2 */ 1603 ushort scc_rtemp; /* Temp storage */ 1604 ushort scc_toseq; /* Transmit out of sequence char */ 1605 ushort scc_char1; /* control character 1 */ 1606 ushort scc_char2; /* control character 2 */ 1607 ushort scc_char3; /* control character 3 */ 1608 ushort scc_char4; /* control character 4 */ 1609 ushort scc_char5; /* control character 5 */ 1610 ushort scc_char6; /* control character 6 */ 1611 ushort scc_char7; /* control character 7 */ 1612 ushort scc_char8; /* control character 8 */ 1613 ushort scc_rccm; /* receive control character mask */ 1614 ushort scc_rccr; /* receive control character register */ 1615 ushort scc_rlbc; /* receive last break character */ 1616} scc_uart_t; 1617 1618/* SCC Event and Mask registers when it is used as a UART. 1619*/ 1620#define UART_SCCM_GLR ((ushort)0x1000) 1621#define UART_SCCM_GLT ((ushort)0x0800) 1622#define UART_SCCM_AB ((ushort)0x0200) 1623#define UART_SCCM_IDL ((ushort)0x0100) 1624#define UART_SCCM_GRA ((ushort)0x0080) 1625#define UART_SCCM_BRKE ((ushort)0x0040) 1626#define UART_SCCM_BRKS ((ushort)0x0020) 1627#define UART_SCCM_CCR ((ushort)0x0008) 1628#define UART_SCCM_BSY ((ushort)0x0004) 1629#define UART_SCCM_TX ((ushort)0x0002) 1630#define UART_SCCM_RX ((ushort)0x0001) 1631 1632/* The SCC PSMR when used as a UART. 1633*/ 1634#define SCU_PSMR_FLC ((ushort)0x8000) 1635#define SCU_PSMR_SL ((ushort)0x4000) 1636#define SCU_PSMR_CL ((ushort)0x3000) 1637#define SCU_PSMR_UM ((ushort)0x0c00) 1638#define SCU_PSMR_FRZ ((ushort)0x0200) 1639#define SCU_PSMR_RZS ((ushort)0x0100) 1640#define SCU_PSMR_SYN ((ushort)0x0080) 1641#define SCU_PSMR_DRT ((ushort)0x0040) 1642#define SCU_PSMR_PEN ((ushort)0x0010) 1643#define SCU_PSMR_RPM ((ushort)0x000c) 1644#define SCU_PSMR_REVP ((ushort)0x0008) 1645#define SCU_PSMR_TPM ((ushort)0x0003) 1646#define SCU_PSMR_TEVP ((ushort)0x0003) 1647 1648/* CPM Transparent mode SCC. 1649 */ 1650typedef struct scc_trans { 1651 sccp_t st_genscc; 1652 uint st_cpres; /* Preset CRC */ 1653 uint st_cmask; /* Constant mask for CRC */ 1654} scc_trans_t; 1655 1656#define BD_SCC_TX_LAST ((ushort)0x0800) 1657 1658/* IIC parameter RAM. 1659*/ 1660typedef struct iic { 1661 ushort iic_rbase; /* Rx Buffer descriptor base address */ 1662 ushort iic_tbase; /* Tx Buffer descriptor base address */ 1663 u_char iic_rfcr; /* Rx function code */ 1664 u_char iic_tfcr; /* Tx function code */ 1665 ushort iic_mrblr; /* Max receive buffer length */ 1666 uint iic_rstate; /* Internal */ 1667 uint iic_rdp; /* Internal */ 1668 ushort iic_rbptr; /* Internal */ 1669 ushort iic_rbc; /* Internal */ 1670 uint iic_rxtmp; /* Internal */ 1671 uint iic_tstate; /* Internal */ 1672 uint iic_tdp; /* Internal */ 1673 ushort iic_tbptr; /* Internal */ 1674 ushort iic_tbc; /* Internal */ 1675 uint iic_txtmp; /* Internal */ 1676 uint iic_res; /* reserved */ 1677 ushort iic_rpbase; /* Relocation pointer */ 1678 ushort iic_res2; /* reserved */ 1679} iic_t; 1680 1681/* SPI parameter RAM. 1682*/ 1683typedef struct spi { 1684 ushort spi_rbase; /* Rx Buffer descriptor base address */ 1685 ushort spi_tbase; /* Tx Buffer descriptor base address */ 1686 u_char spi_rfcr; /* Rx function code */ 1687 u_char spi_tfcr; /* Tx function code */ 1688 ushort spi_mrblr; /* Max receive buffer length */ 1689 uint spi_rstate; /* Internal */ 1690 uint spi_rdp; /* Internal */ 1691 ushort spi_rbptr; /* Internal */ 1692 ushort spi_rbc; /* Internal */ 1693 uint spi_rxtmp; /* Internal */ 1694 uint spi_tstate; /* Internal */ 1695 uint spi_tdp; /* Internal */ 1696 ushort spi_tbptr; /* Internal */ 1697 ushort spi_tbc; /* Internal */ 1698 uint spi_txtmp; /* Internal */ 1699 uint spi_res; 1700 ushort spi_rpbase; /* Relocation pointer */ 1701 ushort spi_res2; 1702} spi_t; 1703 1704/* SPI Mode register. 1705*/ 1706#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 1707#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 1708#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 1709#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 1710#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 1711#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 1712#define SPMODE_EN ((ushort)0x0100) /* Enable */ 1713#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 1714#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 1715 1716#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 1717#define SPMODE_PM(x) ((x) &0xF) 1718 1719/* HDLC parameter RAM. 1720*/ 1721 1722typedef struct hdlc_pram_s { 1723 /* 1724 * SCC parameter RAM 1725 */ 1726 ushort rbase; /* Rx Buffer descriptor base address */ 1727 ushort tbase; /* Tx Buffer descriptor base address */ 1728 uchar rfcr; /* Rx function code */ 1729 uchar tfcr; /* Tx function code */ 1730 ushort mrblr; /* Rx buffer length */ 1731 ulong rstate; /* Rx internal state */ 1732 ulong rptr; /* Rx internal data pointer */ 1733 ushort rbptr; /* rb BD Pointer */ 1734 ushort rcount; /* Rx internal byte count */ 1735 ulong rtemp; /* Rx temp */ 1736 ulong tstate; /* Tx internal state */ 1737 ulong tptr; /* Tx internal data pointer */ 1738 ushort tbptr; /* Tx BD pointer */ 1739 ushort tcount; /* Tx byte count */ 1740 ulong ttemp; /* Tx temp */ 1741 ulong rcrc; /* temp receive CRC */ 1742 ulong tcrc; /* temp transmit CRC */ 1743 /* 1744 * HDLC specific parameter RAM 1745 */ 1746 uchar res[4]; /* reserved */ 1747 ulong c_mask; /* CRC constant */ 1748 ulong c_pres; /* CRC preset */ 1749 ushort disfc; /* discarded frame counter */ 1750 ushort crcec; /* CRC error counter */ 1751 ushort abtsc; /* abort sequence counter */ 1752 ushort nmarc; /* nonmatching address rx cnt */ 1753 ushort retrc; /* frame retransmission cnt */ 1754 ushort mflr; /* maximum frame length reg */ 1755 ushort max_cnt; /* maximum length counter */ 1756 ushort rfthr; /* received frames threshold */ 1757 ushort rfcnt; /* received frames count */ 1758 ushort hmask; /* user defined frm addr mask */ 1759 ushort haddr1; /* user defined frm address 1 */ 1760 ushort haddr2; /* user defined frm address 2 */ 1761 ushort haddr3; /* user defined frm address 3 */ 1762 ushort haddr4; /* user defined frm address 4 */ 1763 ushort tmp; /* temp */ 1764 ushort tmp_mb; /* temp */ 1765} hdlc_pram_t; 1766 1767/* CPM interrupts. There are nearly 32 interrupts generated by CPM 1768 * channels or devices. All of these are presented to the PPC core 1769 * as a single interrupt. The CPM interrupt handler dispatches its 1770 * own handlers, in a similar fashion to the PPC core handler. We 1771 * use the table as defined in the manuals (i.e. no special high 1772 * priority and SCC1 == SCCa, etc...). 1773 */ 1774#define CPMVEC_NR 32 1775#define CPMVEC_OFFSET 0x00010000 1776#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) 1777#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) 1778#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) 1779#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) 1780#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) 1781#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) 1782#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) 1783#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) 1784#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) 1785#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) 1786#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) 1787#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) 1788#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) 1789#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) 1790#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) 1791#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) 1792#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) 1793#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) 1794#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) 1795#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) 1796#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) 1797#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) 1798#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) 1799#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) 1800#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) 1801#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) 1802#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) 1803#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) 1804#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) 1805 1806extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); 1807 1808/* CPM interrupt configuration vector. 1809*/ 1810#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 1811#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 1812#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 1813#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 1814#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 1815#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 1816#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 1817#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 1818#endif /* __CPM_8XX__ */ 1819