LXR uboot/include/ns9750

   1/***********************************************************************
   2 *
   3 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
   4 * All rights reserved.
   5 *
   6 * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
   7 * @Author: Markus Pietrek
   8 * @Descr: Definitions for Memory Control Module
   9 * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 *
  26 ***********************************************************************/
  27
  28#ifndef FS_NS9750_MEM_H
  29#define FS_NS9750_SYS_H
  30
  31#define NS9750_MEM_MODULE_BASE          (0xA0700000)
  32
  33#define get_mem_reg_addr(c) \
  34        ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
  35
  36/* the register addresses */
  37
  38#define NS9750_MEM_CTRL                 (0x0000)
  39#define NS9750_MEM_STATUS               (0x0004)
  40#define NS9750_MEM_CFG                  (0x0008)
  41#define NS9750_MEM_DYN_CTRL             (0x0020)
  42#define NS9750_MEM_DYN_REFRESH          (0x0024)
  43#define NS9750_MEM_DYN_READ_CFG         (0x0028)
  44#define NS9750_MEM_DYN_TRP              (0x0030)
  45#define NS9750_MEM_DYN_TRAS             (0x0034)
  46#define NS9750_MEM_DYN_TSREX            (0x0038)
  47#define NS9750_MEM_DYN_TAPR             (0x003C)
  48#define NS9750_MEM_DYN_TDAL             (0x0040)
  49#define NS9750_MEM_DYN_TWR              (0x0044)
  50#define NS9750_MEM_DYN_TRC              (0x0048)
  51#define NS9750_MEM_DYN_TRFC             (0x004C)
  52#define NS9750_MEM_DYN_TXSR             (0x0050)
  53#define NS9750_MEM_DYN_TRRD             (0x0054)
  54#define NS9750_MEM_DYN_TMRD             (0x0058)
  55#define NS9750_MEM_STAT_EXT_WAIT        (0x0080)
  56#define NS9750_MEM_DYN_CFG_BASE         (0x0100)
  57#define NS9750_MEM_DYN_RAS_CAS_BASE     (0x0104)
  58#define NS9750_MEM_STAT_CFG_BASE        (0x0200)
  59#define NS9750_MEM_STAT_WAIT_WEN_BASE   (0x0204)
  60#define NS9750_MEM_STAT_WAIT_OEN_BASE   (0x0208)
  61#define NS9750_MEM_STAT_WAIT_RD_BASE    (0x020C)
  62#define NS9750_MEM_STAT_WAIT_PAGE_BASE  (0x0210)
  63#define NS9750_MEM_STAT_WAIR_WR_BASE    (0x0214)
  64#define NS9750_MEM_STAT_WAIT_TURN_BASE  (0x0218)
  65
  66/* the vectored register addresses */
  67
  68#define NS9750_MEM_DYN_CFG(c)           (NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
  69#define NS9750_MEM_DYN_RAS_CAS(c)       (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
  70#define NS9750_MEM_STAT_CFG(c)          (NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
  71#define NS9750_MEM_STAT_WAIT_WEN(c)     (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
  72#define NS9750_MEM_STAT_WAIT_OEN(c)     (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
  73#define NS9750_MEM_STAT_RD(c)           (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
  74#define NS9750_MEM_STAT_PAGE(c)         (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
  75#define NS9750_MEM_STAT_WR(c)           (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
  76#define NS9750_MEM_STAT_TURN(c)         (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
  77
  78/* register bit fields */
  79
  80#define NS9750_MEM_CTRL_L               (0x00000004)
  81#define NS9750_MEM_CTRL_M               (0x00000002)
  82#define NS9750_MEM_CTRL_E               (0x00000001)
  83
  84#define NS9750_MEM_STAT_SA              (0x00000004)
  85#define NS9750_MEM_STAT_S               (0x00000002)
  86#define NS9750_MEM_STAT_B               (0x00000001)
  87
  88#define NS9750_MEM_CFG_CLK              (0x00000010)
  89#define NS9750_MEM_CFG_N                (0x00000001)
  90
  91#define NS9750_MEM_DYN_CTRL_NRP         (0x00004000)
  92#define NS9750_MEM_DYN_CTRL_DP          (0x00002000)
  93#define NS9750_MEM_DYN_CTRL_I_MA        (0x00000180)
  94#define NS9750_MEM_DYN_CTRL_I_NORMAL    (0x00000000)
  95#define NS9750_MEM_DYN_CTRL_I_MODE      (0x00000080)
  96#define NS9750_MEM_DYN_CTRL_I_PALL      (0x00000100)
  97#define NS9750_MEM_DYN_CTRL_I_NOP       (0x00000180)
  98#define NS9750_MEM_DYN_CTRL_SR          (0x00000002)
  99#define NS9750_MEM_DYN_CTRL_CE          (0x00000001)
 100
 101
 102#define NS9750_MEM_DYN_REFRESH_MA       (0x000007FF)
 103
 104#define NS9750_MEM_DYN_READ_CFG_MA      (0x00000003)
 105#define NS9750_MEM_DYN_READ_CFG_DELAY0  (0x00000001)
 106#define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
 107#define NS9750_MEM_DYN_READ_CFG_DELAY2  (0x00000003)
 108
 109#define NS9750_MEM_DYN_TRP_MA           (0x0000000F)
 110
 111#define NS9750_MEM_DYN_TRAS_MA          (0x0000000F)
 112
 113#define NS9750_MEM_DYN_TSREX_MA         (0x0000000F)
 114
 115#define NS9750_MEM_DYN_TAPR_MA          (0x0000000F)
 116
 117#define NS9750_MEM_DYN_TDAL_MA          (0x0000000F)
 118
 119#define NS9750_MEM_DYN_TWR_MA           (0x0000000F)
 120
 121#define NS9750_MEM_DYN_TRC_MA           (0x0000001F)
 122
 123#define NS9750_MEM_DYN_TRFC_MA          (0x0000001F)
 124
 125#define NS9750_MEM_DYN_TXSR_MA          (0x0000001F)
 126
 127#define NS9750_MEM_DYN_TRRD_MA          (0x0000000F)
 128
 129#define NS9750_MEM_DYN_TMRD_MA          (0x0000000F)
 130
 131#define NS9750_MEM_STAT_EXTW_WAIT_MA    (0x0000003F)
 132
 133#define NS9750_MEM_DYN_CFG_P            (0x00100000)
 134#define NS9750_MEM_DYN_CFG_BDMC         (0x00080000)
 135#define NS9750_MEM_DYN_CFG_AM           (0x00004000)
 136#define NS9750_MEM_DYN_CFG_AM_MA        (0x00001F80)
 137#define NS9750_MEM_DYN_CFG_MD           (0x00000018)
 138
 139#define NS9750_MEM_DYN_RAS_CAS_CAS_MA   (0x00000300)
 140#define NS9750_MEM_DYN_RAS_CAS_CAS_1    (0x00000100)
 141#define NS9750_MEM_DYN_RAS_CAS_CAS_2    (0x00000200)
 142#define NS9750_MEM_DYN_RAS_CAS_CAS_3    (0x00000300)
 143#define NS9750_MEM_DYN_RAS_CAS_RAS_MA   (0x00000003)
 144#define NS9750_MEM_DYN_RAS_CAS_RAS_1    (0x00000001)
 145#define NS9750_MEM_DYN_RAS_CAS_RAS_2    (0x00000002)
 146#define NS9750_MEM_DYN_RAS_CAS_RAS_3    (0x00000003)
 147
 148#define NS9750_MEM_STAT_CFG_PSMC        (0x00100000)
 149#define NS9750_MEM_STAT_CFG_BSMC        (0x00080000)
 150#define NS9750_MEM_STAT_CFG_EW          (0x00000100)
 151#define NS9750_MEM_STAT_CFG_PB          (0x00000080)
 152#define NS9750_MEM_STAT_CFG_PC          (0x00000040)
 153#define NS9750_MEM_STAT_CFG_PM          (0x00000008)
 154#define NS9750_MEM_STAT_CFG_MW_MA       (0x00000003)
 155#define NS9750_MEM_STAT_CFG_MW_8        (0x00000000)
 156#define NS9750_MEM_STAT_CFG_MW_16       (0x00000001)
 157#define NS9750_MEM_STAT_CFG_MW_32       (0x00000002)
 158
 159#define NS9750_MEM_STAT_WAIT_WEN_MA     (0x0000000F)
 160
 161#define NS9750_MEM_STAT_WAIT_OEN_MA     (0x0000000F)
 162
 163#define NS9750_MEM_STAT_WAIT_RD_MA      (0x0000001F)
 164
 165#define NS9750_MEM_STAT_WAIT_PAGE_MA    (0x0000001F)
 166
 167#define NS9750_MEM_STAT_WAIT_WR_MA      (0x0000001F)
 168
 169#define NS9750_MEM_STAT_WAIT_TURN_MA    (0x0000000F)
 170
 171
 172#endif /* FS_NS9750_MEM_H */
 173