1 AMCC Ocotea Board 2 3 Last Update: March 2, 2004 4======================================================================= 5 6This file contains some handy info regarding U-Boot and the AMCC 7Ocotea 440gx evalutation board. See the README.ppc440 for additional 8information. 9 10 11SWITCH SETTINGS & JUMPERS 12========================== 13 14Here's what I've been using successfully. If you feel inclined to 15change things ... please read the docs! 16 17DIPSW U46 U80 18------------------------ 19SW 1 off off 20SW 2 on off 21SW 3 off off 22SW 4 off off 23SW 5 off off 24SW 6 on on 25SW 7 on off 26SW 8 on off 27 28J41: strapped 29J42: open 30 31All others are factory default. 32 33 34I2C Information 35===================== 36 37See README.ebony for information. 38 39PCI 40=========================== 41 42Untested at the time of writing. 43 44PPC440GX Ethernet EMACs 45=========================== 46 47All EMAC ports have been tested and are known to work 48with EPS Group 4. 49 50Special note about the Cicada CIS8201: 51 The CIS8201 Gigabit PHY comes up in GMII mode by default. 52 One must hit an extended register to allow use of RGMII mode. 53 This has been done in the 440gx_enet.c file with a #ifdef/endif 54 pair. 55 56AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. 57The addresses contained in the config header file are from my particular 58board and you _*should*_ change them to reflect your board either in the 59config file and/or in your environment variables. I found the addresses on 60labels on the bottom side of the board. 61 62 63BDI2k or JTAG Debugging 64=========================== 65 66For ease of debugging you can swap the small boot flash and external SRAM 67by changing U46:3 to on. You can then use the sram as your boot flash by 68loading the sram via the jtag debugger. 69 70 71Regards, 72--Travis 73<tsawyer@sandburst.com> 74