LXR uboot/board/freescale/m5329evb/mii.c

   1/*
   2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/fec.h>
  26#include <asm/immap.h>
  27
  28#include <config.h>
  29#include <net.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
  34#undef MII_DEBUG
  35#undef ET_DEBUG
  36
  37int fecpin_setclear(struct eth_device *dev, int setclear)
  38{
  39        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  40
  41        if (setclear) {
  42                gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
  43                gpio->par_feci2c |=
  44                    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
  45        } else {
  46                gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
  47                gpio->par_feci2c &=
  48                    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
  49        }
  50        return 0;
  51}
  52
  53#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
  54#include <miiphy.h>
  55
  56/* Make MII read/write commands for the FEC. */
  57#define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
  58
  59#define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
  60
  61/* PHY identification */
  62#define PHY_ID_LXT970           0x78100000      /* LXT970 */
  63#define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
  64#define PHY_ID_82555            0x02a80150      /* Intel 82555 */
  65#define PHY_ID_QS6612           0x01814400      /* QS6612 */
  66#define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
  67#define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
  68#define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
  69#define PHY_ID_DP83848VV        0x20005C90      /* National 83848 */
  70#define PHY_ID_DP83849          0x20005CA2      /* National 82849 */
  71
  72#define STR_ID_LXT970           "LXT970"
  73#define STR_ID_LXT971           "LXT971"
  74#define STR_ID_82555            "Intel82555"
  75#define STR_ID_QS6612           "QS6612"
  76#define STR_ID_AMD79C784        "AMD79C784"
  77#define STR_ID_LSI80225         "LSI80225"
  78#define STR_ID_LSI80225B        "LSI80225/B"
  79#define STR_ID_DP83848VV        "N83848"
  80#define STR_ID_DP83849          "N83849"
  81
  82/****************************************************************************
  83 * mii_init -- Initialize the MII for MII command without ethernet
  84 * This function is a subset of eth_init
  85 ****************************************************************************
  86 */
  87void mii_reset(struct fec_info_s *info)
  88{
  89        volatile fec_t *fecp = (fec_t *) (info->miibase);
  90        int i;
  91
  92        fecp->ecr = FEC_ECR_RESET;
  93        for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  94                udelay(1);
  95        }
  96        if (i == FEC_RESET_DELAY) {
  97                printf("FEC_RESET_DELAY timeout\n");
  98        }
  99}
 100
 101/* send command to phy using mii, wait for result */
 102uint mii_send(uint mii_cmd)
 103{
 104        struct fec_info_s *info;
 105        struct eth_device *dev;
 106        volatile fec_t *ep;
 107        uint mii_reply;
 108        int j = 0;
 109
 110        /* retrieve from register structure */
 111        dev = eth_get_dev();
 112        info = dev->priv;
 113
 114        ep = (fec_t *) info->miibase;
 115
 116        ep->mmfr = mii_cmd;     /* command to phy */
 117
 118        /* wait for mii complete */
 119        while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
 120                udelay(1);
 121                j++;
 122        }
 123        if (j >= MCFFEC_TOUT_LOOP) {
 124                printf("MII not complete\n");
 125                return -1;
 126        }
 127
 128        mii_reply = ep->mmfr;   /* result from phy */
 129        ep->eir = FEC_EIR_MII;  /* clear MII complete */
 130#ifdef ET_DEBUG
 131        printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 132               __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
 133#endif
 134
 135        return (mii_reply & 0xffff);    /* data read from phy */
 136}
 137#endif                          /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 138
 139#if defined(CFG_DISCOVER_PHY)
 140int mii_discover_phy(struct eth_device *dev)
 141{
 142#define MAX_PHY_PASSES 11
 143        struct fec_info_s *info = dev->priv;
 144        int phyaddr, pass;
 145        uint phyno, phytype;
 146
 147        if (info->phyname_init)
 148                return info->phy_addr;
 149
 150        phyaddr = -1;           /* didn't find a PHY yet */
 151        for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 152                if (pass > 1) {
 153                        /* PHY may need more time to recover from reset.
 154                         * The LXT970 needs 50ms typical, no maximum is
 155                         * specified, so wait 10ms before try again.
 156                         * With 11 passes this gives it 100ms to wake up.
 157                         */
 158                        udelay(10000);  /* wait 10ms */
 159                }
 160
 161                for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 162
 163                        phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
 164#ifdef ET_DEBUG
 165                        printf("PHY type 0x%x pass %d type\n", phytype, pass);
 166#endif
 167                        if (phytype != 0xffff) {
 168                                phyaddr = phyno;
 169                                phytype <<= 16;
 170                                phytype |=
 171                                    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
 172
 173                                switch (phytype & 0xffffffff) {
 174                                case PHY_ID_DP83848VV:
 175                                        strcpy(info->phy_name,
 176                                               STR_ID_DP83848VV);
 177                                        info->phyname_init = 1;
 178                                        break;
 179                                default:
 180                                        strcpy(info->phy_name, "unknown");
 181                                        info->phyname_init = 1;
 182                                        break;
 183                                }
 184
 185#ifdef ET_DEBUG
 186                                printf("PHY @ 0x%x pass %d type ", phyno, pass);
 187                                switch (phytype & 0xffffffff) {
 188                                case PHY_ID_DP83848VV:
 189                                        printf(STR_ID_DP83848VV);
 190                                        break;
 191                                default:
 192                                        printf("0x%08x\n", phytype);
 193                                        break;
 194                                }
 195#endif
 196                        }
 197                }
 198        }
 199        if (phyaddr < 0)
 200                printf("No PHY device found.\n");
 201
 202        return phyaddr;
 203}
 204#endif                          /* CFG_DISCOVER_PHY */
 205
 206void mii_init(void) __attribute__((weak,alias("__mii_init")));
 207
 208void __mii_init(void)
 209{
 210        volatile fec_t *fecp;
 211        struct fec_info_s *info;
 212        struct eth_device *dev;
 213        int miispd = 0, i = 0;
 214        u16 autoneg = 0;
 215
 216        /* retrieve from register structure */
 217        dev = eth_get_dev();
 218        info = dev->priv;
 219
 220        fecp = (fec_t *) info->miibase;
 221
 222        fecpin_setclear(dev, 1);
 223
 224        mii_reset(info);
 225
 226        /* We use strictly polling mode only */
 227        fecp->eimr = 0;
 228
 229        /* Clear any pending interrupt */
 230        fecp->eir = 0xffffffff;
 231
 232        /* Set MII speed */
 233        miispd = (gd->bus_clk / 1000000) / 5;
 234        fecp->mscr = miispd << 1;
 235
 236        info->phy_addr = mii_discover_phy(dev);
 237
 238#define AUTONEGLINK             (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
 239        while (i < MCFFEC_TOUT_LOOP) {
 240                autoneg = 0;
 241                miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
 242                i++;
 243
 244                if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
 245                        break;
 246
 247                udelay(500);
 248        }
 249        if (i >= MCFFEC_TOUT_LOOP) {
 250                printf("Auto Negotiation not complete\n");
 251        }
 252
 253        /* adapt to the half/full speed settings */
 254        info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
 255        info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
 256}
 257
 258/*****************************************************************************
 259 * Read and write a MII PHY register, routines used by MII Utilities
 260 *
 261 * FIXME: These routines are expected to return 0 on success, but mii_send
 262 *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 263 *        no PHY connected...
 264 *        For now always return 0.
 265 * FIXME: These routines only work after calling eth_init() at least once!
 266 *        Otherwise they hang in mii_send() !!! Sorry!
 267 *****************************************************************************/
 268
 269int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
 270                       unsigned short *value)
 271{
 272        short rdreg;            /* register working value */
 273
 274#ifdef MII_DEBUG
 275        printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
 276#endif
 277        rdreg = mii_send(mk_mii_read(addr, reg));
 278
 279        *value = rdreg;
 280
 281#ifdef MII_DEBUG
 282        printf("0x%04x\n", *value);
 283#endif
 284
 285        return 0;
 286}
 287
 288int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
 289                        unsigned short value)
 290{
 291        short rdreg;            /* register working value */
 292
 293#ifdef MII_DEBUG
 294        printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 295#endif
 296
 297        rdreg = mii_send(mk_mii_write(addr, reg, value));
 298
 299#ifdef MII_DEBUG
 300        printf("0x%04x\n", value);
 301#endif
 302
 303        return 0;
 304}
 305
 306#endif                          /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
 307