LXR uboot/cpu/arm920t/s3c24x0/speed.c

   1/*
   2 * (C) Copyright 2001-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2002
   6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/* This code should work for both the S3C2400 and the S3C2410
  28 * as they seem to have the same PLL and clock machinery inside.
  29 * The different address mapping is handled by the s3c24xx.h files below.
  30 */
  31
  32#include <common.h>
  33#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
  34
  35#if defined(CONFIG_S3C2400)
  36#include <s3c2400.h>
  37#elif defined(CONFIG_S3C2410)
  38#include <s3c2410.h>
  39#endif
  40
  41#define MPLL 0
  42#define UPLL 1
  43
  44/* ------------------------------------------------------------------------- */
  45/* NOTE: This describes the proper use of this file.
  46 *
  47 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  48 *
  49 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  50 * the specified bus in HZ.
  51 */
  52/* ------------------------------------------------------------------------- */
  53
  54static ulong get_PLLCLK(int pllreg)
  55{
  56    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  57    ulong r, m, p, s;
  58
  59    if (pllreg == MPLL)
  60        r = clk_power->MPLLCON;
  61    else if (pllreg == UPLL)
  62        r = clk_power->UPLLCON;
  63    else
  64        hang();
  65
  66    m = ((r & 0xFF000) >> 12) + 8;
  67    p = ((r & 0x003F0) >> 4) + 2;
  68    s = r & 0x3;
  69
  70    return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
  71}
  72
  73/* return FCLK frequency */
  74ulong get_FCLK(void)
  75{
  76    return(get_PLLCLK(MPLL));
  77}
  78
  79/* return HCLK frequency */
  80ulong get_HCLK(void)
  81{
  82    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  83
  84    return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
  85}
  86
  87/* return PCLK frequency */
  88ulong get_PCLK(void)
  89{
  90    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  91
  92    return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
  93}
  94
  95/* return UCLK frequency */
  96ulong get_UCLK(void)
  97{
  98    return(get_PLLCLK(UPLL));
  99}
 100
 101#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
 102