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8
9
10static int cc_to_error[16] = {
11
12
13 0,
14 USB_ST_CRC_ERR,
15 USB_ST_BIT_ERR,
16 USB_ST_CRC_ERR,
17 USB_ST_STALLED,
18 -1,
19 USB_ST_BIT_ERR,
20 USB_ST_BIT_ERR,
21 USB_ST_BUF_ERR,
22 USB_ST_BUF_ERR,
23 -1,
24 -1,
25 USB_ST_BUF_ERR,
26 USB_ST_BUF_ERR,
27 -1,
28 -1
29};
30
31
32
33#define ED_NEW 0x00
34#define ED_UNLINK 0x01
35#define ED_OPER 0x02
36#define ED_DEL 0x04
37#define ED_URB_DEL 0x08
38
39
40struct ed {
41 __u32 hwINFO;
42 __u32 hwTailP;
43 __u32 hwHeadP;
44 __u32 hwNextED;
45
46 struct ed *ed_prev;
47 __u8 int_period;
48 __u8 int_branch;
49 __u8 int_load;
50 __u8 int_interval;
51 __u8 state;
52 __u8 type;
53 __u16 last_iso;
54 struct ed *ed_rm_list;
55
56 struct usb_device *usb_dev;
57 __u32 unused[3];
58} __attribute((aligned(16)));
59typedef struct ed ed_t;
60
61
62#define TD_CC 0xf0000000
63#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
64#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
65#define TD_EC 0x0C000000
66#define TD_T 0x03000000
67#define TD_T_DATA0 0x02000000
68#define TD_T_DATA1 0x03000000
69#define TD_T_TOGGLE 0x00000000
70#define TD_R 0x00040000
71#define TD_DI 0x00E00000
72#define TD_DI_SET(X) (((X) & 0x07)<< 21)
73#define TD_DP 0x00180000
74#define TD_DP_SETUP 0x00000000
75#define TD_DP_IN 0x00100000
76#define TD_DP_OUT 0x00080000
77
78#define TD_ISO 0x00010000
79#define TD_DEL 0x00020000
80
81
82#define TD_CC_NOERROR 0x00
83#define TD_CC_CRC 0x01
84#define TD_CC_BITSTUFFING 0x02
85#define TD_CC_DATATOGGLEM 0x03
86#define TD_CC_STALL 0x04
87#define TD_DEVNOTRESP 0x05
88#define TD_PIDCHECKFAIL 0x06
89#define TD_UNEXPECTEDPID 0x07
90#define TD_DATAOVERRUN 0x08
91#define TD_DATAUNDERRUN 0x09
92#define TD_BUFFEROVERRUN 0x0C
93#define TD_BUFFERUNDERRUN 0x0D
94#define TD_NOTACCESSED 0x0F
95
96#define MAXPSW 1
97
98struct td {
99 __u32 hwINFO;
100 __u32 hwCBP;
101 __u32 hwNextTD;
102 __u32 hwBE;
103
104 __u16 hwPSW[MAXPSW];
105 __u8 unused;
106 __u8 index;
107 struct ed *ed;
108 struct td *next_dl_td;
109 struct usb_device *usb_dev;
110 int transfer_len;
111 __u32 data;
112
113 __u32 unused2[2];
114} __attribute((aligned(32)));
115typedef struct td td_t;
116
117#define OHCI_ED_SKIP (1 << 14)
118
119
120
121
122
123
124
125#define NUM_INTS 32
126struct ohci_hcca {
127 __u32 int_table[NUM_INTS];
128#if defined(CONFIG_MPC5200)
129 __u16 pad1;
130 __u16 frame_no;
131#else
132 __u16 frame_no;
133 __u16 pad1;
134#endif
135 __u32 done_head;
136 u8 reserved_for_hc[116];
137} __attribute((aligned(256)));
138
139
140
141
142#define MAX_ROOT_PORTS 15
143
144
145
146
147
148
149struct ohci_regs {
150
151 __u32 revision;
152 __u32 control;
153 __u32 cmdstatus;
154 __u32 intrstatus;
155 __u32 intrenable;
156 __u32 intrdisable;
157
158 __u32 hcca;
159 __u32 ed_periodcurrent;
160 __u32 ed_controlhead;
161 __u32 ed_controlcurrent;
162 __u32 ed_bulkhead;
163 __u32 ed_bulkcurrent;
164 __u32 donehead;
165
166 __u32 fminterval;
167 __u32 fmremaining;
168 __u32 fmnumber;
169 __u32 periodicstart;
170 __u32 lsthresh;
171
172 struct ohci_roothub_regs {
173 __u32 a;
174 __u32 b;
175 __u32 status;
176 __u32 portstatus[MAX_ROOT_PORTS];
177 } roothub;
178} __attribute((aligned(32)));
179
180
181
182
183
184
185#define OHCI_CTRL_CBSR (3 << 0)
186#define OHCI_CTRL_PLE (1 << 2)
187#define OHCI_CTRL_IE (1 << 3)
188#define OHCI_CTRL_CLE (1 << 4)
189#define OHCI_CTRL_BLE (1 << 5)
190#define OHCI_CTRL_HCFS (3 << 6)
191#define OHCI_CTRL_IR (1 << 8)
192#define OHCI_CTRL_RWC (1 << 9)
193#define OHCI_CTRL_RWE (1 << 10)
194
195
196# define OHCI_USB_RESET (0 << 6)
197# define OHCI_USB_RESUME (1 << 6)
198# define OHCI_USB_OPER (2 << 6)
199# define OHCI_USB_SUSPEND (3 << 6)
200
201
202
203
204#define OHCI_HCR (1 << 0)
205#define OHCI_CLF (1 << 1)
206#define OHCI_BLF (1 << 2)
207#define OHCI_OCR (1 << 3)
208#define OHCI_SOC (3 << 16)
209
210
211
212
213
214
215
216#define OHCI_INTR_SO (1 << 0)
217#define OHCI_INTR_WDH (1 << 1)
218#define OHCI_INTR_SF (1 << 2)
219#define OHCI_INTR_RD (1 << 3)
220#define OHCI_INTR_UE (1 << 4)
221#define OHCI_INTR_FNO (1 << 5)
222#define OHCI_INTR_RHSC (1 << 6)
223#define OHCI_INTR_OC (1 << 30)
224#define OHCI_INTR_MIE (1 << 31)
225
226
227struct virt_root_hub {
228 int devnum;
229 void *dev;
230 void *int_addr;
231 int send;
232 int interval;
233};
234
235
236
237
238#define RH_INTERFACE 0x01
239#define RH_ENDPOINT 0x02
240#define RH_OTHER 0x03
241
242#define RH_CLASS 0x20
243#define RH_VENDOR 0x40
244
245
246#define RH_GET_STATUS 0x0080
247#define RH_CLEAR_FEATURE 0x0100
248#define RH_SET_FEATURE 0x0300
249#define RH_SET_ADDRESS 0x0500
250#define RH_GET_DESCRIPTOR 0x0680
251#define RH_SET_DESCRIPTOR 0x0700
252#define RH_GET_CONFIGURATION 0x0880
253#define RH_SET_CONFIGURATION 0x0900
254#define RH_GET_STATE 0x0280
255#define RH_GET_INTERFACE 0x0A80
256#define RH_SET_INTERFACE 0x0B00
257#define RH_SYNC_FRAME 0x0C80
258
259#define RH_SET_EP 0x2000
260
261
262#define RH_PORT_CONNECTION 0x00
263#define RH_PORT_ENABLE 0x01
264#define RH_PORT_SUSPEND 0x02
265#define RH_PORT_OVER_CURRENT 0x03
266#define RH_PORT_RESET 0x04
267#define RH_PORT_POWER 0x08
268#define RH_PORT_LOW_SPEED 0x09
269
270#define RH_C_PORT_CONNECTION 0x10
271#define RH_C_PORT_ENABLE 0x11
272#define RH_C_PORT_SUSPEND 0x12
273#define RH_C_PORT_OVER_CURRENT 0x13
274#define RH_C_PORT_RESET 0x14
275
276
277#define RH_C_HUB_LOCAL_POWER 0x00
278#define RH_C_HUB_OVER_CURRENT 0x01
279
280#define RH_DEVICE_REMOTE_WAKEUP 0x00
281#define RH_ENDPOINT_STALL 0x01
282
283#define RH_ACK 0x01
284#define RH_REQ_ERR -1
285#define RH_NACK 0x00
286
287
288
289
290#define RH_PS_CCS 0x00000001
291#define RH_PS_PES 0x00000002
292#define RH_PS_PSS 0x00000004
293#define RH_PS_POCI 0x00000008
294#define RH_PS_PRS 0x00000010
295#define RH_PS_PPS 0x00000100
296#define RH_PS_LSDA 0x00000200
297#define RH_PS_CSC 0x00010000
298#define RH_PS_PESC 0x00020000
299#define RH_PS_PSSC 0x00040000
300#define RH_PS_OCIC 0x00080000
301#define RH_PS_PRSC 0x00100000
302
303
304#define RH_HS_LPS 0x00000001
305#define RH_HS_OCI 0x00000002
306#define RH_HS_DRWE 0x00008000
307#define RH_HS_LPSC 0x00010000
308#define RH_HS_OCIC 0x00020000
309#define RH_HS_CRWE 0x80000000
310
311
312#define RH_B_DR 0x0000ffff
313#define RH_B_PPCM 0xffff0000
314
315
316#define RH_A_NDP (0xff << 0)
317#define RH_A_PSM (1 << 8)
318#define RH_A_NPS (1 << 9)
319#define RH_A_DT (1 << 10)
320#define RH_A_OCPM (1 << 11)
321#define RH_A_NOCP (1 << 12)
322#define RH_A_POTPGT (0xff << 24)
323
324
325#define N_URB_TD 48
326typedef struct {
327 ed_t *ed;
328 __u16 length;
329 __u16 td_cnt;
330 int state;
331 unsigned long pipe;
332 int actual_length;
333 td_t *td[N_URB_TD];
334} urb_priv_t;
335#define URB_DEL 1
336
337
338
339
340
341
342
343
344typedef struct ohci {
345 struct ohci_hcca *hcca;
346
347
348 int irq;
349 int disabled;
350 int sleeping;
351 unsigned long flags;
352
353 struct ohci_regs *regs;
354
355 ed_t *ed_rm_list[2];
356 ed_t *ed_bulktail;
357 ed_t *ed_controltail;
358 int intrstatus;
359 __u32 hc_control;
360 struct usb_device *dev[32];
361 struct virt_root_hub rh;
362
363 const char *slot_name;
364} ohci_t;
365
366#define NUM_EDS 8
367
368struct ohci_device {
369 ed_t ed[NUM_EDS];
370 int ed_cnt;
371};
372
373
374
375static int ep_link(ohci_t * ohci, ed_t * ed);
376static int ep_unlink(ohci_t * ohci, ed_t * ed);
377static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
378
379
380
381
382#define NUM_TD 64
383
384
385td_t gtd[NUM_TD + 1];
386
387td_t *ptd;
388
389
390static inline struct td *td_alloc(struct usb_device *usb_dev)
391{
392 int i;
393 struct td *td;
394
395 td = NULL;
396 for (i = 0; i < NUM_TD; i++) {
397 if (ptd[i].usb_dev == NULL) {
398 td = &ptd[i];
399 td->usb_dev = usb_dev;
400 break;
401 }
402 }
403
404 return td;
405}
406
407static inline void ed_free(struct ed *ed)
408{
409 ed->usb_dev = NULL;
410}
411