LXR uboot/include/configs/DK1S10.h

   1/*
   2 * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
   3 * Stephan Linz <linz@li-pro.net>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27/***********************************************************************
  28 * Include the whole NIOS CPU configuration.
  29 *
  30 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
  31 *
  32 ***********************************************************************/
  33
  34#if     defined(CONFIG_NIOS_SAFE_32)
  35#include <configs/DK1S10_safe_32.h>
  36#elif   defined(CONFIG_NIOS_STANDARD_32)
  37#include <configs/DK1S10_standard_32.h>
  38#elif   defined(CONFIG_NIOS_MTX_LDK_20)
  39#include <configs/DK1S10_mtx_ldk_20.h>
  40#else
  41#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
  42#endif
  43
  44/*------------------------------------------------------------------------
  45 * BOARD/CPU -- TOP-LEVEL
  46 *----------------------------------------------------------------------*/
  47#define CONFIG_NIOS             1               /* NIOS-32 core         */
  48#define CONFIG_DK1S10           1               /* Stratix DK-1S10 board*/
  49#define CONFIG_SYS_CLK_FREQ     CFG_NIOS_CPU_CLK/* 50 MHz core clock    */
  50#define CFG_HZ                  1000            /* 1 msec time tick     */
  51#undef  CFG_CLKS_IN_HZ
  52#define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
  53
  54/*------------------------------------------------------------------------
  55 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  56 *----------------------------------------------------------------------*/
  57#if     (CFG_NIOS_CPU_SDRAM_SIZE != 0)
  58
  59#define CFG_SDRAM_BASE          CFG_NIOS_CPU_SDRAM_BASE
  60#define CFG_SDRAM_SIZE          CFG_NIOS_CPU_SDRAM_SIZE
  61
  62#else
  63#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
  64#endif
  65
  66#if     defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
  67
  68#define CFG_SRAM_BASE           CFG_NIOS_CPU_SRAM_BASE
  69#define CFG_SRAM_SIZE           CFG_NIOS_CPU_SRAM_SIZE
  70
  71#else
  72
  73#undef  CFG_SRAM_BASE
  74#undef  CFG_SRAM_SIZE
  75
  76#endif
  77
  78#define CFG_VECT_BASE           CFG_NIOS_CPU_VEC_BASE
  79
  80/*------------------------------------------------------------------------
  81 * MEMORY ORGANIZATION - For the most part, you can put things pretty
  82 * much anywhere. This is pretty flexible for Nios. So here we make some
  83 * arbitrary choices & assume that the monitor is placed at the end of
  84 * a memory resource (so you must make sure TEXT_BASE is chosen
  85 * appropriately).
  86 *
  87 *      -The heap is placed below the monitor.
  88 *      -Global data is placed below the heap.
  89 *      -The stack is placed below global data (&grows down).
  90 *----------------------------------------------------------------------*/
  91#define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256k         */
  92#define CFG_GBL_DATA_SIZE       128             /* Global data size rsvd*/
  93#define CFG_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
  94
  95#define CFG_MONITOR_BASE        TEXT_BASE
  96#define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  97#define CFG_GBL_DATA_OFFSET     (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  98#define CFG_INIT_SP             CFG_GBL_DATA_OFFSET
  99
 100/*------------------------------------------------------------------------
 101 * FLASH (AM29LV065D)
 102 *----------------------------------------------------------------------*/
 103#if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 104
 105#define CFG_FLASH_BASE          CFG_NIOS_CPU_FLASH_BASE
 106#define CFG_FLASH_SIZE          CFG_NIOS_CPU_FLASH_SIZE
 107#define CFG_MAX_FLASH_SECT      128             /* Max # sects per bank */
 108#define CFG_MAX_FLASH_BANKS     1               /* Max # of flash banks */
 109#define CFG_FLASH_ERASE_TOUT    8000            /* Erase timeout (msec) */
 110#define CFG_FLASH_WRITE_TOUT    100             /* Write timeout (msec) */
 111#define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size      */
 112
 113#else
 114#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
 115#endif
 116
 117/*------------------------------------------------------------------------
 118 * ENVIRONMENT
 119 *----------------------------------------------------------------------*/
 120#if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 121
 122#define CONFIG_ENV_IS_IN_FLASH  1               /* Environment in flash */
 123
 124#if     defined(CONFIG_NIOS_STANDARD_32)
 125#define CONFIG_ENV_ADDR         CFG_FLASH_BASE  /* Mem addr of env      */
 126#elif   defined(CONFIG_NIOS_MTX_LDK_20)
 127#define CONFIG_ENV_ADDR         (CFG_FLASH_BASE + CFG_MONITOR_LEN)
 128#else
 129#error *** CFG_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR
 130#endif
 131
 132#define CONFIG_ENV_SIZE         (64 * 1024)     /* 64 KByte (1 sector)  */
 133#define CONFIG_ENV_OVERWRITE                    /* Serial/eth change Ok */
 134
 135#else
 136#define CONFIG_ENV_IS_NOWHERE   1               /* NO Environment       */
 137#endif
 138
 139/*------------------------------------------------------------------------
 140 * CONSOLE
 141 *----------------------------------------------------------------------*/
 142#if     (CFG_NIOS_CPU_UART_NUMS != 0)
 143
 144#define CFG_NIOS_CONSOLE        CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
 145#define CONFIG_LOADS_ECHO       1        /* echo on for serial download */
 146
 147#if     (CFG_NIOS_CPU_UART0_BR != 0)
 148#define CFG_NIOS_FIXEDBAUD      1                  /* Baudrate is fixed */
 149#define CONFIG_BAUDRATE         CFG_NIOS_CPU_UART0_BR
 150#else
 151#undef  CFG_NIOS_FIXEDBAUD
 152#define CONFIG_BAUDRATE         115200
 153#endif
 154
 155#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 156
 157#else
 158#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
 159#endif
 160
 161/*------------------------------------------------------------------------
 162 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 163 * so an avalon bus timer is required.
 164 *----------------------------------------------------------------------*/
 165#if     (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
 166
 167#if     (CFG_NIOS_CPU_TICK_TIMER == 0)
 168
 169#define CFG_NIOS_TMRBASE        CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick   */
 170#define CFG_NIOS_TMRIRQ         CFG_NIOS_CPU_TIMER0_IRQ
 171
 172#if     (CFG_NIOS_CPU_TIMER0_FP == 1)               /* fixed period */
 173
 174#if     (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
 175#define CFG_NIOS_TMRMS          (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
 176#else
 177#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
 178#endif
 179
 180#undef  CFG_NIOS_TMRCNT /* no preloadable counter value */
 181
 182#elif   (CFG_NIOS_CPU_TIMER0_FP == 0)               /* variable period */
 183
 184#if     (CFG_HZ <= 1000)
 185#define CFG_NIOS_TMRMS          (1000 / CFG_HZ)
 186#else
 187#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
 188#endif
 189
 190#define CFG_NIOS_TMRCNT         (CONFIG_SYS_CLK_FREQ / CFG_HZ)
 191
 192#else
 193#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
 194#endif
 195
 196#elif   (CFG_NIOS_CPU_TICK_TIMER == 1)
 197
 198#define CFG_NIOS_TMRBASE        CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick   */
 199#define CFG_NIOS_TMRIRQ         CFG_NIOS_CPU_TIMER1_IRQ
 200
 201#if     (CFG_NIOS_CPU_TIMER1_FP == 1)               /* fixed period */
 202
 203#if     (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
 204#define CFG_NIOS_TMRMS          (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
 205#else
 206#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
 207#endif
 208
 209#undef  CFG_NIOS_TMRCNT /* no preloadable counter value */
 210
 211#elif   (CFG_NIOS_CPU_TIMER1_FP == 0)               /* variable period */
 212
 213#if     (CFG_HZ <= 1000)
 214#define CFG_NIOS_TMRMS          (1000 / CFG_HZ)
 215#else
 216#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
 217#endif
 218
 219#define CFG_NIOS_TMRCNT         (CONFIG_SYS_CLK_FREQ / CFG_HZ)
 220
 221#else
 222#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
 223#endif
 224
 225#endif  /* CFG_NIOS_CPU_TICK_TIMER */
 226
 227#else
 228#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
 229#endif
 230
 231/*------------------------------------------------------------------------
 232 * Ethernet -- needs work!
 233 *----------------------------------------------------------------------*/
 234#if     (CFG_NIOS_CPU_LAN_NUMS == 1)
 235
 236#if     (CFG_NIOS_CPU_LAN0_TYPE == 0)           /* LAN91C111            */
 237
 238#define CONFIG_DRIVER_SMC91111                  /* Using SMC91c111      */
 239#undef  CONFIG_SMC91111_EXT_PHY                 /* Internal PHY         */
 240#define CONFIG_SMC91111_BASE    (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 241
 242#if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 243#define CONFIG_SMC_USE_32_BIT   1
 244#else   /* no */
 245#undef  CONFIG_SMC_USE_32_BIT
 246#endif
 247
 248#elif   (CFG_NIOS_CPU_LAN0_TYPE == 1)           /* CS8900A              */
 249
 250        /********************************************/
 251        /* !!! CS8900 is __not__ tested on NIOS !!! */
 252        /********************************************/
 253#define CONFIG_DRIVER_CS8900                    /* Using CS8900         */
 254#define CS8900_BASE             (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 255
 256#if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 257#undef  CS8900_BUS16
 258#define CS8900_BUS32            1
 259#else   /* no */
 260#define CS8900_BUS16            1
 261#undef  CS8900_BUS32
 262#endif
 263
 264#else
 265#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 266#endif
 267
 268#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 269#define CONFIG_NETMASK          255.255.255.0
 270#define CONFIG_IPADDR           192.168.2.21
 271#define CONFIG_SERVERIP         192.168.2.16
 272
 273#else
 274#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
 275#endif
 276
 277/*------------------------------------------------------------------------
 278 * STATUS LEDs
 279 *----------------------------------------------------------------------*/
 280#if     (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
 281
 282#if     (CFG_NIOS_CPU_LED_PIO == 0)
 283
 284#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
 285
 286#elif   (CFG_NIOS_CPU_LED_PIO == 1)
 287
 288#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
 289
 290#elif   (CFG_NIOS_CPU_LED_PIO == 2)
 291
 292#define STATUS_LED_BASE                 CFG_NIOS_CPU_PIO2
 293#define STATUS_LED_BITS                 CFG_NIOS_CPU_PIO2_BITS
 294#define STATUS_LED_ACTIVE               1 /* LED on for bit == 1 */
 295
 296#if     (CFG_NIOS_CPU_PIO2_TYPE == 1)
 297#define STATUS_LED_WRONLY               1
 298#else
 299#undef  STATUS_LED_WRONLY
 300#endif
 301
 302#elif   (CFG_NIOS_CPU_LED_PIO == 3)
 303
 304#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
 305
 306#elif   (CFG_NIOS_CPU_LED_PIO == 4)
 307
 308#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
 309
 310#elif   (CFG_NIOS_CPU_LED_PIO == 5)
 311
 312#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
 313
 314#elif   (CFG_NIOS_CPU_LED_PIO == 6)
 315
 316#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
 317
 318#elif   (CFG_NIOS_CPU_LED_PIO == 7)
 319
 320#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
 321
 322#elif   (CFG_NIOS_CPU_LED_PIO == 8)
 323
 324#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
 325
 326#elif   (CFG_NIOS_CPU_LED_PIO == 9)
 327
 328#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
 329
 330#else
 331#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
 332#endif
 333
 334#define CONFIG_STATUS_LED               1 /* enable status led driver */
 335
 336#define STATUS_LED_BIT                  (1 << 0)        /* LED[0] */
 337#define STATUS_LED_STATE                STATUS_LED_BLINKING
 338#define STATUS_LED_BOOT_STATE           STATUS_LED_OFF
 339#define STATUS_LED_PERIOD               (CFG_HZ / 10)   /* ca. 1 Hz */
 340#define STATUS_LED_BOOT                 0               /* boot LED */
 341
 342#if     (STATUS_LED_BITS > 1)
 343#define STATUS_LED_BIT1                 (1 << 1)        /* LED[1] */
 344#define STATUS_LED_STATE1               STATUS_LED_OFF
 345#define STATUS_LED_PERIOD1              (CFG_HZ / 50)   /* ca. 5 Hz */
 346#define STATUS_LED_RED                  1               /* fail LED */
 347#endif
 348
 349#if     (STATUS_LED_BITS > 2)
 350#define STATUS_LED_BIT2                 (1 << 2)        /* LED[2] */
 351#define STATUS_LED_STATE2               STATUS_LED_OFF
 352#define STATUS_LED_PERIOD2              (CFG_HZ / 10)   /* ca. 1 Hz */
 353#define STATUS_LED_YELLOW               2               /* info LED */
 354#endif
 355
 356#if     (STATUS_LED_BITS > 3)
 357#define STATUS_LED_BIT3                 (1 << 3)        /* LED[3] */
 358#define STATUS_LED_STATE3               STATUS_LED_OFF
 359#define STATUS_LED_PERIOD3              (CFG_HZ / 10)   /* ca. 1 Hz */
 360#define STATUS_LED_GREEN                3               /* info LED */
 361#endif
 362
 363#define STATUS_LED_PAR                  1 /* makes status_led.h happy */
 364
 365#endif  /* CFG_NIOS_CPU_PIO_NUMS */
 366
 367/*------------------------------------------------------------------------
 368 * SEVEN SEGMENT LED DISPLAY
 369 *----------------------------------------------------------------------*/
 370#if     (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
 371
 372#if     (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
 373
 374#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
 375
 376#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
 377
 378#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
 379
 380#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
 381
 382#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
 383
 384#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
 385
 386#define SEVENSEG_BASE                   CFG_NIOS_CPU_PIO3
 387#define SEVENSEG_BITS                   CFG_NIOS_CPU_PIO3_BITS
 388#define SEVENSEG_ACTIVE                 0 /* LED on for bit == 1 */
 389
 390#if     (CFG_NIOS_CPU_PIO3_TYPE == 1)
 391#define SEVENSEG_WRONLY                 1
 392#else
 393#undef  SEVENSEG_WRONLY
 394#endif
 395
 396#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
 397
 398#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
 399
 400#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
 401
 402#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
 403
 404#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
 405
 406#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
 407
 408#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
 409
 410#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
 411
 412#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
 413
 414#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
 415
 416#elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
 417
 418#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
 419
 420#else
 421#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
 422#endif
 423
 424#define CONFIG_SEVENSEG                 1 /* enable seven segment led driver */
 425
 426/*
 427 * Dual 7-Segment Display pin assignment -- read more in your
 428 * "Nios Development Board Reference Manual"
 429 *
 430 *
 431 *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
 432 *         ______               ______
 433 *        |  D14 |             |  D6  |
 434 *        |      |             |      |
 435 *      D9|      |D13        D1|      |D5
 436 *        |______|             |______|                  ___
 437 *        |  D8  |             |  D0  |                 | A |
 438 *        |      |             |      |                F|___|B
 439 *     D10|      |D12        D2|      |D4               | G |
 440 *        |______|             |______|                E|___|C
 441 *           D11  *               D3   *                  D  *
 442 *                D15                  D7                    DP
 443 *
 444 */
 445#define SEVENSEG_DIGIT_HI_LO_EQUAL      1       /* high nibble equal low nibble */
 446#define SEVENSEG_DIGIT_A                (1 << 6) /* bit 6 is segment A */
 447#define SEVENSEG_DIGIT_B                (1 << 5) /* bit 5 is segment B */
 448#define SEVENSEG_DIGIT_C                (1 << 4) /* bit 4 is segment C */
 449#define SEVENSEG_DIGIT_D                (1 << 3) /* bit 3 is segment D */
 450#define SEVENSEG_DIGIT_E                (1 << 2) /* bit 2 is segment E */
 451#define SEVENSEG_DIGIT_F                (1 << 1) /* bit 1 is segment F */
 452#define SEVENSEG_DIGIT_G                (1 << 0) /* bit 0 is segment G */
 453#define SEVENSEG_DIGIT_DP               (1 << 7) /* bit 7 is decimal point */
 454
 455#endif  /* CFG_NIOS_CPU_PIO_NUMS */
 456
 457/*
 458 * BOOTP options
 459 */
 460#define CONFIG_BOOTP_BOOTFILESIZE
 461#define CONFIG_BOOTP_BOOTPATH
 462#define CONFIG_BOOTP_GATEWAY
 463#define CONFIG_BOOTP_HOSTNAME
 464
 465
 466/*
 467 * Command line configuration.
 468 */
 469#include <config_cmd_default.h>
 470
 471#define CONFIG_CMD_CDP
 472#define CONFIG_CMD_DHCP
 473#define CONFIG_CMD_DIAG
 474#define CONFIG_CMD_DISPLAY
 475#define CONFIG_CMD_EXT2
 476#define CONFIG_CMD_IMMAP
 477#define CONFIG_CMD_IRQ
 478#define CONFIG_CMD_PING
 479#define CONFIG_CMD_PORTIO
 480#define CONFIG_CMD_REGINFO
 481#define CONFIG_CMD_REISER
 482#define CONFIG_CMD_SAVES
 483#define CONFIG_CMD_SDRAM
 484#define CONFIG_CMD_SNTP
 485
 486#undef CONFIG_CMD_NFS
 487#undef CONFIG_CMD_XIMG
 488
 489/*------------------------------------------------------------------------
 490 * KGDB
 491 *----------------------------------------------------------------------*/
 492#if defined(CONFIG_CMD_KGDB)
 493#define CONFIG_KGDB_BAUDRATE    9600
 494#endif
 495
 496/*------------------------------------------------------------------------
 497 * MISC
 498 *----------------------------------------------------------------------*/
 499#define CFG_LONGHELP                        /* undef to save memory     */
 500#define CFG_PROMPT              "DK1S10 > " /* Monitor Command Prompt   */
 501#define CFG_CBSIZE              256         /* Console I/O Buffer Size  */
 502#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 503#define CFG_MAXARGS             16          /* max number of command args*/
 504#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size */
 505
 506/* Default load address */
 507#if     (CFG_SRAM_SIZE != 0)
 508
 509/* default in SRAM */
 510#define CFG_LOAD_ADDR           CFG_SRAM_BASE
 511
 512#elif   (CFG_SDRAM_SIZE != 0)
 513
 514/* default in SDRAM */
 515#if     (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
 516#define CFG_LOAD_ADDR           (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
 517#else
 518#define CFG_LOAD_ADDR           CFG_SDRAM_BASE
 519#endif
 520
 521#else
 522#undef  CFG_LOAD_ADDR           /* force error break */
 523#endif
 524
 525
 526/* MEM test area */
 527#if     (CFG_SDRAM_SIZE != 0)
 528
 529/* SDRAM begin to stack area (1MB stack) */
 530#if     (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
 531#define CFG_MEMTEST_START       (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
 532#define CFG_MEMTEST_END         (CFG_INIT_SP - (1024 * 1024))
 533#else
 534#define CFG_MEMTEST_START       CFG_SDRAM_BASE
 535#define CFG_MEMTEST_END         (CFG_INIT_SP - (1024 * 1024))
 536#endif
 537
 538#else
 539#undef  CFG_MEMTEST_START       /* force error break */
 540#undef  CFG_MEMTEST_END
 541#endif
 542
 543/*
 544 * JFFS2 partitions
 545 *
 546 */
 547/* No command line, one static partition, whole device */
 548#undef CONFIG_JFFS2_CMDLINE
 549#define CONFIG_JFFS2_DEV                "nor0"
 550#define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 551#define CONFIG_JFFS2_PART_OFFSET        0x00000000
 552
 553/* mtdparts command line support */
 554/*
 555#define CONFIG_JFFS2_CMDLINE
 556#define MTDIDS_DEFAULT          ""
 557#define MTDPARTS_DEFAULT        ""
 558*/
 559
 560#endif  /* __CONFIG_H */
 561