1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 37#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ 38 39#undef CONFIG_8xx_CONS_SMC1 40#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 41#undef CONFIG_8xx_CONS_NONE 42#define CONFIG_BAUDRATE 115200 43 44#define CONFIG_BOOTCOUNT_LIMIT 45 46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 48#define CONFIG_BOARD_TYPES 1 /* support board types */ 49 50#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 51 52#undef CONFIG_BOOTARGS 53 54#define CONFIG_EXTRA_ENV_SETTINGS \ 55 "netdev=eth0\0" \ 56 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 57 "nfsroot=${serverip}:${rootpath}\0" \ 58 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 59 "addip=setenv bootargs ${bootargs} " \ 60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 61 ":${hostname}:${netdev}:off panic=1\0" \ 62 "flash_nfs=run nfsargs addip;" \ 63 "bootm ${kernel_addr}\0" \ 64 "flash_self=run ramargs addip;" \ 65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 67 "rootpath=/opt/eldk/ppc_8xx\0" \ 68 "hostname=FPS850L\0" \ 69 "bootfile=FPS850L/uImage\0" \ 70 "fdt_addr=40040000\0" \ 71 "kernel_addr=40060000\0" \ 72 "ramdisk_addr=40200000\0" \ 73 "u-boot=FPS850L/u-image.bin\0" \ 74 "load=tftp 200000 ${u-boot}\0" \ 75 "update=prot off 40000000 +${filesize};" \ 76 "era 40000000 +${filesize};" \ 77 "cp.b 200000 40000000 ${filesize};" \ 78 "sete filesize;save\0" \ 79 "" 80#define CONFIG_BOOTCOMMAND "run flash_self" 81 82#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 83#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 84 85#undef CONFIG_WATCHDOG /* watchdog disabled */ 86 87/* 88 * BOOTP options 89 */ 90#define CONFIG_BOOTP_SUBNETMASK 91#define CONFIG_BOOTP_GATEWAY 92#define CONFIG_BOOTP_HOSTNAME 93#define CONFIG_BOOTP_BOOTPATH 94#define CONFIG_BOOTP_BOOTFILESIZE 95#define CONFIG_BOOTP_SUBNETMASK 96#define CONFIG_BOOTP_GATEWAY 97#define CONFIG_BOOTP_HOSTNAME 98#define CONFIG_BOOTP_NISDOMAIN 99#define CONFIG_BOOTP_BOOTPATH 100#define CONFIG_BOOTP_DNS 101#define CONFIG_BOOTP_DNS2 102#define CONFIG_BOOTP_SEND_HOSTNAME 103#define CONFIG_BOOTP_NTPSERVER 104#define CONFIG_BOOTP_TIMEOFFSET 105 106#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 107 108/* 109 * Command line configuration. 110 */ 111#include <config_cmd_default.h> 112 113#define CONFIG_CMD_ASKENV 114#define CONFIG_CMD_DATE 115#define CONFIG_CMD_DHCP 116#define CONFIG_CMD_JFFS2 117#define CONFIG_CMD_NFS 118#define CONFIG_CMD_SNTP 119 120 121#define CONFIG_NETCONSOLE 122 123 124/* 125 * Miscellaneous configurable options 126 */ 127#define CFG_LONGHELP /* undef to save memory */ 128#define CFG_PROMPT "=> " /* Monitor Command Prompt */ 129 130#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 131#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 132#ifdef CFG_HUSH_PARSER 133#define CFG_PROMPT_HUSH_PS2 "> " 134#endif 135 136#if defined(CONFIG_CMD_KGDB) 137#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 138#else 139#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 140#endif 141#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 142#define CFG_MAXARGS 16 /* max number of command args */ 143#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 144 145#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ 146#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 147 148#define CFG_LOAD_ADDR 0x100000 /* default load address */ 149 150#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ 151 152#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 153 154/* 155 * Low Level Configuration Settings 156 * (address mappings, register initial values, etc.) 157 * You should know what you are doing if you make changes here. 158 */ 159/*----------------------------------------------------------------------- 160 * Internal Memory Mapped Register 161 */ 162#define CFG_IMMR 0xFFF00000 163 164/*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167#define CFG_INIT_RAM_ADDR CFG_IMMR 168#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 169#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 170#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 171#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 172 173/*----------------------------------------------------------------------- 174 * Start addresses for the final memory configuration 175 * (Set up by the startup code) 176 * Please note that CFG_SDRAM_BASE _must_ start at 0 177 */ 178#define CFG_SDRAM_BASE 0x00000000 179#define CFG_FLASH_BASE 0x40000000 180#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 181#define CFG_MONITOR_BASE CFG_FLASH_BASE 182#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 183 184/* 185 * For booting Linux, the board info and command line data 186 * have to be in the first 8 MB of memory, since this is 187 * the maximum mapped by the Linux kernel during initialization. 188 */ 189#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 190 191/*----------------------------------------------------------------------- 192 * FLASH organization 193 */ 194 195/* use CFI flash driver */ 196#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ 197#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 198#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } 199#define CFG_FLASH_EMPTY_INFO 200#define CFG_FLASH_USE_BUFFER_WRITE 1 201#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ 202#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 203 204#define CONFIG_ENV_IS_IN_FLASH 1 205#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 206#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 207 208/* Address and size of Redundant Environment Sector */ 209#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 210#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 211 212#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ 213 214#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 215 216/*----------------------------------------------------------------------- 217 * Dynamic MTD partition support 218 */ 219#define CONFIG_JFFS2_CMDLINE 220#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 221 222#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 223 "128k(dtb)," \ 224 "1664k(kernel)," \ 225 "2m(rootfs)," \ 226 "4m(data)" 227 228/*----------------------------------------------------------------------- 229 * Hardware Information Block 230 */ 231#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 232#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 233#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 234 235/*----------------------------------------------------------------------- 236 * Cache Configuration 237 */ 238#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 239#if defined(CONFIG_CMD_KGDB) 240#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 241#endif 242 243/*----------------------------------------------------------------------- 244 * SYPCR - System Protection Control 11-9 245 * SYPCR can only be written once after reset! 246 *----------------------------------------------------------------------- 247 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 248 */ 249#if defined(CONFIG_WATCHDOG) 250#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 251 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 252#else 253#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 254#endif 255 256/*----------------------------------------------------------------------- 257 * SIUMCR - SIU Module Configuration 11-6 258 *----------------------------------------------------------------------- 259 * PCMCIA config., multi-function pin tri-state 260 */ 261#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 262 263/*----------------------------------------------------------------------- 264 * TBSCR - Time Base Status and Control 11-26 265 *----------------------------------------------------------------------- 266 * Clear Reference Interrupt Status, Timebase freezing enabled 267 */ 268#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 269 270/*----------------------------------------------------------------------- 271 * RTCSC - Real-Time Clock Status and Control Register 11-27 272 *----------------------------------------------------------------------- 273 */ 274#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 275 276/*----------------------------------------------------------------------- 277 * PISCR - Periodic Interrupt Status and Control 11-31 278 *----------------------------------------------------------------------- 279 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 280 */ 281#define CFG_PISCR (PISCR_PS | PISCR_PITF) 282 283/*----------------------------------------------------------------------- 284 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 285 *----------------------------------------------------------------------- 286 * Reset PLL lock status sticky bit, timer expired status bit and timer 287 * interrupt status bit - leave PLL multiplication factor unchanged ! 288 */ 289#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 290 291/*----------------------------------------------------------------------- 292 * SCCR - System Clock and reset Control Register 15-27 293 *----------------------------------------------------------------------- 294 * Set clock output, timebase and RTC source and divider, 295 * power management and some other internal clocks 296 */ 297#define SCCR_MASK SCCR_EBDF11 298#define CFG_SCCR (SCCR_TBS | \ 299 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 300 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 301 SCCR_DFALCD00) 302 303/*----------------------------------------------------------------------- 304 * PCMCIA stuff 305 *----------------------------------------------------------------------- 306 * 307 */ 308#define CFG_PCMCIA_MEM_ADDR (0xE0000000) 309#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) 310#define CFG_PCMCIA_DMA_ADDR (0xE4000000) 311#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) 312#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) 313#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 314#define CFG_PCMCIA_IO_ADDR (0xEC000000) 315#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) 316 317/*----------------------------------------------------------------------- 318 * 319 *----------------------------------------------------------------------- 320 * 321 */ 322#define CFG_DER 0 323 324/* 325 * Init Memory Controller: 326 * 327 * BR0/1 and OR0/1 (FLASH) 328 */ 329 330#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 331#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 332 333/* used to re-map FLASH both when starting from SRAM or FLASH: 334 * restrict access enough to keep SRAM working (if any) 335 * but not too much to meddle with FLASH accesses 336 */ 337#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ 338#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 339 340/* 341 * FLASH timing: 342 */ 343#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 344 OR_SCY_3_CLK | OR_EHTR | OR_BI) 345 346#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) 347#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 348#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 349 350#define CFG_OR1_REMAP CFG_OR0_REMAP 351#define CFG_OR1_PRELIM CFG_OR0_PRELIM 352#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 353 354/* 355 * BR2/3 and OR2/3 (SDRAM) 356 * 357 */ 358#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 359#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 360#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 361 362/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 363#define CFG_OR_TIMING_SDRAM 0x00000A00 364 365#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) 366#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 367 368#define CFG_OR3_PRELIM CFG_OR2_PRELIM 369#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 370 371/* 372 * Memory Periodic Timer Prescaler 373 * 374 * The Divider for PTA (refresh timer) configuration is based on an 375 * example SDRAM configuration (64 MBit, one bank). The adjustment to 376 * the number of chip selects (NCS) and the actually needed refresh 377 * rate is done by setting MPTPR. 378 * 379 * PTA is calculated from 380 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 381 * 382 * gclk CPU clock (not bus clock!) 383 * Trefresh Refresh cycle * 4 (four word bursts used) 384 * 385 * 4096 Rows from SDRAM example configuration 386 * 1000 factor s -> ms 387 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 388 * 4 Number of refresh cycles per period 389 * 64 Refresh cycle in ms per number of rows 390 * -------------------------------------------- 391 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 392 * 393 * 50 MHz => 50.000.000 / Divider = 98 394 * 66 Mhz => 66.000.000 / Divider = 129 395 * 80 Mhz => 80.000.000 / Divider = 156 396 */ 397 398#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 399#define CFG_MAMR_PTA 98 400 401/* 402 * For 16 MBit, refresh rates could be 31.3 us 403 * (= 64 ms / 2K = 125 / quad bursts). 404 * For a simpler initialization, 15.6 us is used instead. 405 * 406 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 407 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 408 */ 409#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 410#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 411 412/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 413#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 414#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 415 416/* 417 * MAMR settings for SDRAM 418 */ 419 420/* 8 column SDRAM */ 421#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 422 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 423 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 424/* 9 column SDRAM */ 425#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 426 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 427 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 428 429 430/* 431 * Internal Definitions 432 * 433 * Boot Flags 434 */ 435#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 436#define BOOTFLAG_WARM 0x02 /* Software reboot */ 437 438#endif /* __CONFIG_H */ 439