1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* ------------------------------------------------------------------------- */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC824X 1 39#define CONFIG_MPC8240 1 40#define CONFIG_OXC 1 41 42#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 43 44#define CONFIG_IDENT_STRING " [oxc] " 45 46#define CONFIG_WATCHDOG 1 47#define CONFIG_SHOW_ACTIVITY 1 48#define CONFIG_SHOW_BOOT_PROGRESS 1 49 50#define CONFIG_CONS_INDEX 1 51#define CONFIG_BAUDRATE 9600 52#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 53 54 55/* 56 * BOOTP options 57 */ 58#define CONFIG_BOOTP_BOOTFILESIZE 59#define CONFIG_BOOTP_BOOTPATH 60#define CONFIG_BOOTP_GATEWAY 61#define CONFIG_BOOTP_HOSTNAME 62 63 64/* 65 * Command line configuration. 66 */ 67#include <config_cmd_default.h> 68 69#define CONFIG_CMD_ELF 70 71 72/* 73 * Miscellaneous configurable options 74 */ 75#define CFG_LONGHELP 1 /* undef to save memory */ 76#define CFG_PROMPT "=> " /* Monitor Command Prompt */ 77#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 78#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 79#define CFG_MAXARGS 16 /* max number of command args */ 80#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 81#define CFG_LOAD_ADDR 0x00100000 /* default load address */ 82#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ 83 84#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ 85 86/*----------------------------------------------------------------------- 87 * Boot options 88 */ 89 90#define CONFIG_SERVERIP 10.0.0.1 91#define CONFIG_GATEWAYIP 10.0.0.1 92#define CONFIG_NETMASK 255.255.255.0 93#define CONFIG_LOADADDR 0x10000 94#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf" 95#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000" 96#define CONFIG_BOOTDELAY 10 97 98#define CFG_OXC_GENERATE_IP 1 /* Generate IP automatically */ 99#define CFG_OXC_IPMASK 0x0A000000 /* 10.0.0.x */ 100 101/*----------------------------------------------------------------------- 102 * PCI stuff 103 */ 104 105#define CONFIG_PCI /* include pci support */ 106 107#define CONFIG_NET_MULTI /* Multi ethernet cards support */ 108 109#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */ 110#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 111 112#define PCI_ENET0_IOADDR 0x80000000 113#define PCI_ENET0_MEMADDR 0x80000000 114#define PCI_ENET1_IOADDR 0x81000000 115#define PCI_ENET1_MEMADDR 0x81000000 116 117/*----------------------------------------------------------------------- 118 * FLASH 119 */ 120 121#define CFG_FLASH_PRELIMBASE 0xFF800000 122#define CFG_FLASH_BASE (0-flash_info[0].size) 123 124#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 125#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ 126 127#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 128#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 129 130/*----------------------------------------------------------------------- 131 * RAM 132 */ 133 134#define CFG_SDRAM_BASE 0x00000000 135#define CFG_MAX_RAM_SIZE 0x10000000 136 137#define CFG_RESET_ADDRESS 0xFFF00100 138 139#define CFG_MONITOR_BASE TEXT_BASE 140#define CFG_MONITOR_LEN 0x00030000 141 142#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE) 143# define CFG_RAMBOOT 1 144#else 145# undef CFG_RAMBOOT 146#endif 147 148#define CFG_INIT_RAM_ADDR 0x40000000 149#define CFG_INIT_RAM_END 0x1000 150 151#define CFG_GBL_DATA_SIZE 128 152#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 153#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 154 155#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 156 157#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ 158#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ 159 160/*----------------------------------------------------------------------- 161 * Memory mapping 162 */ 163 164#define CFG_CPLD_BASE 0xff000000 /* CPLD registers */ 165#define CFG_CPLD_WATCHDOG (CFG_CPLD_BASE) /* Watchdog */ 166#define CFG_CPLD_RESET (CFG_CPLD_BASE + 0x040000) /* Minor resets */ 167#define CFG_UART_BASE (CFG_CPLD_BASE + 0x700000) /* debug UART */ 168 169/*----------------------------------------------------------------------- 170 * NS16550 Configuration 171 */ 172 173#define CFG_NS16550 174#define CFG_NS16550_SERIAL 175#define CFG_NS16550_REG_SIZE -4 176#define CFG_NS16550_CLK 1843200 177#define CFG_NS16550_COM1 CFG_UART_BASE 178 179/*----------------------------------------------------------------------- 180 * I2C Bus 181 */ 182 183#define CONFIG_I2C 1 /* I2C support on ... */ 184#define CONFIG_HARD_I2C 1 /* ... hardware one */ 185#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 186#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ 187 188#define CFG_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */ 189#define CFG_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */ 190#define CFG_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */ 191 192/*----------------------------------------------------------------------- 193 * Environment 194 */ 195 196#define CONFIG_ENV_IS_IN_FLASH 1 197#define CONFIG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */ 198#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ 199#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ 200#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */ 201 202/* 203 * Low Level Configuration Settings 204 * (address mappings, register initial values, etc.) 205 * You should know what you are doing if you make changes here. 206 */ 207 208#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 209#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 210 211#define CFG_EUMB_ADDR 0xFC000000 212 213/* MCCR1 */ 214#define CFG_ROMNAL 0 /* rom/flash next access time */ 215#define CFG_ROMFAL 19 /* rom/flash access time */ 216 217/* MCCR2 */ 218#define CFG_ASRISE 15 /* ASRISE=15 clocks */ 219#define CFG_ASFALL 3 /* ASFALL=3 clocks */ 220#define CFG_REFINT 1000 /* REFINT=1000 clocks */ 221 222/* MCCR3 */ 223#define CFG_BSTOPRE 0x35c /* Burst To Precharge */ 224#define CFG_REFREC 7 /* Refresh to activate interval */ 225#define CFG_RDLAT 4 /* data latency from read command */ 226 227/* MCCR4 */ 228#define CFG_PRETOACT 2 /* Precharge to activate interval */ 229#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ 230#define CFG_ACTORW 2 /* Activate to R/W */ 231#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 232#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ 233#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */ 234#define CFG_REGISTERD_TYPE_BUFFER 1 235 236/* memory bank settings*/ 237/* 238 * only bits 20-29 are actually used from these vales to set the 239 * start/end address the upper two bits will be 0, and the lower 20 240 * bits will be set to 0x00000 for a start address, or 0xfffff for an 241 * end address 242 */ 243#define CFG_BANK0_START 0x00000000 244#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) 245#define CFG_BANK0_ENABLE 1 246#define CFG_BANK1_START 0x00000000 247#define CFG_BANK1_END 0x00000000 248#define CFG_BANK1_ENABLE 0 249#define CFG_BANK2_START 0x00000000 250#define CFG_BANK2_END 0x00000000 251#define CFG_BANK2_ENABLE 0 252#define CFG_BANK3_START 0x00000000 253#define CFG_BANK3_END 0x00000000 254#define CFG_BANK3_ENABLE 0 255#define CFG_BANK4_START 0x00000000 256#define CFG_BANK4_END 0x00000000 257#define CFG_BANK4_ENABLE 0 258#define CFG_BANK5_START 0x00000000 259#define CFG_BANK5_END 0x00000000 260#define CFG_BANK5_ENABLE 0 261#define CFG_BANK6_START 0x00000000 262#define CFG_BANK6_END 0x00000000 263#define CFG_BANK6_ENABLE 0 264#define CFG_BANK7_START 0x00000000 265#define CFG_BANK7_END 0x00000000 266#define CFG_BANK7_ENABLE 0 267/* 268 * Memory bank enable bitmask, specifying which of the banks defined above 269 are actually present. MSB is for bank #7, LSB is for bank #0. 270 */ 271#define CFG_BANK_ENABLE 0x01 272 273#define CFG_ODCR 0xff /* configures line driver impedances, */ 274 /* see 8240 book for bit definitions */ 275#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ 276 /* currently accessed page in memory */ 277 /* see 8240 book for details */ 278 279/* SDRAM 0 - 256MB */ 280#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 281#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 282 283/* stack in DCACHE @ 1GB (no backing mem) */ 284#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 285#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 286 287/* PCI memory */ 288#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 289#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 290 291/* Flash, config addrs, etc */ 292#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 293#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 294 295#define CFG_DBAT0L CFG_IBAT0L 296#define CFG_DBAT0U CFG_IBAT0U 297#define CFG_DBAT1L CFG_IBAT1L 298#define CFG_DBAT1U CFG_IBAT1U 299#define CFG_DBAT2L CFG_IBAT2L 300#define CFG_DBAT2U CFG_IBAT2U 301#define CFG_DBAT3L CFG_IBAT3L 302#define CFG_DBAT3U CFG_IBAT3U 303 304/* 305 * For booting Linux, the board info and command line data 306 * have to be in the first 8 MB of memory, since this is 307 * the maximum mapped by the Linux kernel during initialization. 308 */ 309#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 310 311/*----------------------------------------------------------------------- 312 * Cache Configuration 313 */ 314#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ 315#if defined(CONFIG_CMD_KGDB) 316# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 317#endif 318 319/* 320 * Internal Definitions 321 * 322 * Boot Flags 323 */ 324#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 325#define BOOTFLAG_WARM 0x02 /* Software reboot */ 326 327#endif /* __CONFIG_H */ 328