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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38#undef CFG_DEVICE_NULLDEV
39#undef CONFIG_SILENT_CONSOLE
40#undef CFG_CONSOLE_INFO_QUIET
41#undef DEBUG_FLASH
42#undef FLASH_DEBUG
43#undef DEBUG_ENV
44
45#define CFG_DIRECT_FLASH_TFTP 1
46#define CONFIG_ENV_OVERWRITE 1
47
48
49
50
51
52#define CONFIG_MPC850 1
53#define CONFIG_QS850 1
54#define CONFIG_SCC2_ENET 1
55
56
57#undef CONFIG_CLOCK_16MHZ
58#undef CONFIG_CLOCK_33MHZ
59#undef CONFIG_CLOCK_50MHZ
60#define CONFIG_CLOCK_66MHZ 1
61#undef CONFIG_CLOCK_80MHZ
62
63#ifdef CONFIG_CLOCK_16MHZ
64#define CONFIG_CLOCK_MULT 512
65#endif
66
67#ifdef CONFIG_CLOCK_33MHZ
68#define CONFIG_CLOCK_MULT 1024
69#endif
70
71#ifdef CONFIG_CLOCK_50MHZ
72#define CONFIG_CLOCK_MULT 1525
73#endif
74
75#ifdef CONFIG_CLOCK_66MHZ
76#define CONFIG_CLOCK_MULT 2048
77#endif
78
79#ifdef CONFIG_CLOCK_80MHZ
80#define CONFIG_CLOCK_MULT 2441
81#endif
82
83
84#define CONFIG_FLASH_4MB 1
85#undef CONFIG_FLASH_8MB
86
87#define CONFIG_CLOCK_BASE 32768
88
89#define CONFIG_8xx_CONS_SMC1 1
90#undef CONFIG_8xx_CONS_SMC2
91#undef CONFIG_8xx_CONS_NONE
92
93#define CONFIG_BAUDRATE 38400
94
95#undef CONFIG_CLOCKS_IN_MHZ
96
97
98#define CONFIG_IPADDR 192.168.1.99
99#define CONFIG_SERVERIP 192.168.1.19
100
101
102#define CONFIG_PREBOOT "echo '';" \
103 "echo 'type:';" \
104 "echo 'run boot_nfs to boot to NFS';" \
105 "echo 'run boot_flash to boot to flash';" \
106 "echo '';" \
107 "echo 'run flash_rootfs to install a new rootfs';" \
108 "echo 'run flash_env to clear the env sector';" \
109 "echo 'run flash_rw to clear the rw fs';" \
110 "echo 'run flash_uboot to install a new u-boot';" \
111 "echo 'run flash_kernel to install a new kernel';"
112
113
114#define CONFIG_BOOTDELAY 5
115#define CONFIG_BOOTCOMMAND "run boot_nfs"
116
117#undef CONFIG_BOOTARGS
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138#ifdef CONFIG_FLASH_4MB
139#define CONFIG_EXTRA_ENV_SETTINGS \
140 "serial#=QS850\0" \
141 "hostname=qs850\0" \
142 "netdev=eth0\0" \
143 "ethaddr=00:01:02:B4:36:56\0" \
144 "rootpath=/exports/rootfs\0" \
145 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
146 \
147 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
148 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
149 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
150 \
151 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
152 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
153 \
154 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
155 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
156 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
157 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
158 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
159#endif
160
161
162#ifdef CONFIG_FLASH_8MB
163#define CONFIG_EXTRA_ENV_SETTINGS \
164 "serial#=QS850\0" \
165 "hostname=qs850\0" \
166 "netdev=eth0\0" \
167 "ethaddr=00:01:02:B4:36:56\0" \
168 "rootpath=/exports/rootfs\0" \
169 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
170 \
171 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
172 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
173 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
174 \
175 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
176 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
177 \
178 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
179 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
180 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
181 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
182 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
183#endif
184
185#define CONFIG_LOADS_ECHO 1
186#undef CFG_LOADS_BAUD_CHANGE
187#undef CONFIG_WATCHDOG
188#undef CONFIG_STATUS_LED
189#undef CONFIG_CAN_DRIVER
190
191
192
193
194#define CONFIG_BOOTP_SUBNETMASK
195#define CONFIG_BOOTP_GATEWAY
196#define CONFIG_BOOTP_HOSTNAME
197#define CONFIG_BOOTP_BOOTPATH
198#define CONFIG_BOOTP_BOOTFILESIZE
199
200#undef CONFIG_MAC_PARTITION
201#undef CONFIG_DOS_PARTITION
202
203#define CONFIG_RTC_MPC8xx
204
205
206
207
208
209
210#define CONFIG_CMD_BDI
211#define CONFIG_CMD_BOOTD
212#define CONFIG_CMD_CONSOLE
213#define CONFIG_CMD_DATE
214#define CONFIG_CMD_ENV
215#define CONFIG_CMD_FLASH
216#define CONFIG_CMD_IMI
217#define CONFIG_CMD_IMMAP
218#define CONFIG_CMD_MEMORY
219#define CONFIG_CMD_NET
220#define CONFIG_CMD_RUN
221
222
223
224
225
226#define CONFIG_ENV_IS_IN_FLASH 1
227#define CONFIG_ENV_SECT_SIZE 0x20000
228#define CONFIG_ENV_SIZE 0x2000
229#define CONFIG_ENV_ADDR 0xffee0000
230
231
232
233
234#define CFG_LONGHELP
235#define CFG_PROMPT "=> "
236
237#define CFG_HUSH_PARSER 1
238#define CFG_PROMPT_HUSH_PS2 "> "
239
240#if defined(CONFIG_CMD_KGDB)
241#define CFG_CBSIZE 1024
242#else
243#define CFG_CBSIZE 256
244#endif
245#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
246#define CFG_MAXARGS 16
247#define CFG_BARGSIZE CFG_CBSIZE
248
249#define CFG_MEMTEST_START 0x0400000
250#define CFG_MEMTEST_END 0x0C00000
251
252#define CFG_LOAD_ADDR 0x400000
253
254#define CFG_HZ 1000
255
256#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
257
258
259
260
261
262
263
264
265
266
267#define CFG_IMMR 0xFF000000
268
269
270
271
272#define CFG_INIT_RAM_ADDR CFG_IMMR
273#define CFG_INIT_RAM_END 0x2F00
274#define CFG_GBL_DATA_SIZE 64
275#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
276#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
277
278
279
280
281
282
283#define CFG_SDRAM_BASE 0x00000000
284#define CFG_FLASH_BASE 0xFF800000
285
286#define FLASH_BASE0_4M_PRELIM 0xFFC00000
287#define FLASH_BASE0_8M_PRELIM 0xFF800000
288
289#define CFG_MONITOR_LEN (192 << 10)
290#define CFG_MONITOR_BASE 0xFFF00000
291#define CFG_MALLOC_LEN (128 << 10)
292
293
294
295
296
297
298#define CFG_BOOTMAPSZ (8 << 20)
299
300
301
302
303
304#undef CFG_FLASH_16BIT
305#define CFG_MAX_FLASH_BANKS 1
306#define CFG_MAX_FLASH_SECT 71
307
308#define CFG_FLASH_ERASE_TOUT 120000
309#define CFG_FLASH_WRITE_TOUT 500
310
311
312
313
314#define CFG_CACHELINE_SIZE 16
315#if defined(CONFIG_CMD_KGDB)
316#define CFG_CACHELINE_SHIFT 4
317#endif
318
319
320
321
322
323
324
325
326#ifdef CONFIG_WATCHDOG
327#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
328#else
329#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
330#endif
331
332
333
334
335
336#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
337
338
339
340
341
342#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
343
344
345
346
347
348#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
349
350
351
352
353
354#define CFG_PISCR (PISCR_PS | PISCR_PITF)
355
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361
362
363#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
364#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
365
366
367
368
369
370#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
371#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
372#define CFG_BRGCLK_PRESCALE 1
373#endif
374
375#if defined(CONFIG_CLOCK_66MHZ)
376#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
377#define CFG_BRGCLK_PRESCALE 4
378#endif
379
380#if defined(CONFIG_CLOCK_80MHZ)
381#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
382#define CFG_BRGCLK_PRESCALE 4
383#endif
384
385#define SCCR_MASK CFG_SCCR
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403#define CFG_DER 0
404
405
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410
411
412
413
414#define CFG_PRELIM_OR_AM
415#define CFG_OR_TIMING_FLASH
416
417
418
419
420
421
422
423
424
425
426#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
427#define CFG_BR0_PRELIM (vBR0_BA | BR_V)
428
429
430
431#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
432
433#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
434
435#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
436#endif
437
438#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
439
440
441#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
442#endif
443
444#if defined(CONFIG_CLOCK_16MHZ)
445
446#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
447#endif
448
449
450
451
452
453
454
455
456
457#define SDRAM_BASE 0x00000000
458#define SDRAM_PRELIM_OR_AM 0xF8000000
459
460
461
462
463
464#define vOR1_AM ((0xF800 << 16) + (0 << 15))
465#define vBR1_BA ((0x0000 << 16) + (0 << 15))
466#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
467#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
468
469
470
471
472
473#if defined(CONFIG_CLOCK_80MHZ)
474#define vMAMR_PTA (19 << 24)
475#endif
476
477#if defined(CONFIG_CLOCK_66MHZ)
478#define vMAMR_PTA (16 << 24)
479#endif
480
481#if defined(CONFIG_CLOCK_50MHZ)
482#define vMAMR_PTA (195 << 24)
483#endif
484
485#if defined(CONFIG_CLOCK_33MHZ)
486#define vMAMR_PTA (131 << 24)
487#endif
488
489#if defined(CONFIG_CLOCK_16MHZ)
490#define vMAMR_PTA (65 << 24)
491#endif
492
493
494#define SDRAM_16M_MAX_SIZE 0x01000000
495#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
496MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
497
498
499#define SDRAM_32M_MAX_SIZE 0x02000000
500#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
501MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
502
503
504
505
506#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
507
508#define CFG_MPTPR 0x02
509#endif
510
511#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
512
513#define CFG_MPTPR 0x04
514#endif
515
516
517
518
519
520
521#define CFG_OR2_PRELIM 0xFFF00000
522#define CFG_BR2_PRELIM 0xF0200000
523
524
525
526
527
528
529#define CFG_OR3_PRELIM 0xFFF00000
530#define CFG_BR3_PRELIM 0xF0300000
531
532
533
534
535
536
537#define CFG_OR4_PRELIM 0xFFF00000
538#define CFG_BR4_PRELIM 0xF0400000
539
540
541
542
543
544
545
546#define CFG_OR5_PRELIM 0xFFF00000
547#define CFG_BR5_PRELIM 0xF0500000
548
549
550
551
552
553
554#define CFG_OR6_PRELIM 0xFFF00000
555#define CFG_BR6_PRELIM 0xF0600000
556
557
558
559
560
561
562#define CFG_OR7_PRELIM 0xFFF00000
563#define CFG_BR7_PRELIM 0xF0700000
564
565
566
567
568
569
570#define BOOTFLAG_COLD 0x01
571#define BOOTFLAG_WARM 0x02
572
573
574
575
576#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
577#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
578#endif
579
580#endif
581