LXR uboot/include/configs/mgsuvd.h

   1/*
   2 * (C) Copyright 2007
   3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  37#define CONFIG_MGSUVD           1       /* ...on a mgsuvd board */
  38
  39/* Do boardspecific init */
  40#define CONFIG_BOARD_EARLY_INIT_R       1
  41
  42#define CONFIG_8xx_GCLK_FREQ            66000000
  43
  44#define CFG_SMC_UCODE_PATCH     1       /* Relocate SMC1 */
  45#define CFG_SMC_DPMEM_OFFSET    0x1fc0
  46#define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  47
  48#define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  49
  50#define CONFIG_BOOTCOUNT_LIMIT
  51
  52#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  53
  54#define CONFIG_BOARD_TYPES      1       /* support board types          */
  55
  56#define CONFIG_PREBOOT  "echo;" \
  57        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  58        "echo"
  59
  60#undef  CONFIG_BOOTARGS
  61
  62#define CONFIG_EXTRA_ENV_SETTINGS                                               \
  63        "netdev=eth0\0"                                                         \
  64        "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"     \
  65        "nfsargs=setenv bootargs root=/dev/nfs rw "                             \
  66                "nfsroot=${serverip}:${rootpath}\0"                             \
  67        "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
  68        "addip=setenv bootargs ${bootargs} "                                    \
  69                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"              \
  70                ":${hostname}:${netdev}:off panic=1\0"                          \
  71        "flash_nfs=run nfsargs addip;"                                          \
  72                "bootm ${kernel_addr}\0"                                        \
  73        "flash_self=run ramargs addip;"                                         \
  74                "bootm ${kernel_addr} ${ramdisk_addr}\0"                        \
  75        "net_nfs=tftp ${kernel_addr} ${bootfile}; "                             \
  76                "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"      \
  77                "bootm ${kernel_addr} - ${fdt_addr}\0"                          \
  78        "rootpath=/opt/eldk/ppc_8xx\0"                                          \
  79        "bootfile=/tftpboot/mgsuvd/uImage\0"                                    \
  80        "fdt_addr=400000\0"                                                     \
  81        "kernel_addr=200000\0"                                                  \
  82        "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0"                                \
  83        "load=tftp 200000 ${u-boot}\0"                                          \
  84        "update=protect off f0000000 +${filesize};"                             \
  85                "erase f0000000 +${filesize};"                                  \
  86                "cp.b 200000 f0000000 ${filesize};"                             \
  87                "protect on f0000000 +${filesize}\0"                            \
  88        ""
  89#define CONFIG_BOOTCOMMAND      "run flash_self"
  90
  91#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  92#undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  93
  94#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  95
  96/*
  97 * BOOTP options
  98 */
  99#define CONFIG_BOOTP_SUBNETMASK
 100#define CONFIG_BOOTP_GATEWAY
 101#define CONFIG_BOOTP_HOSTNAME
 102#define CONFIG_BOOTP_BOOTPATH
 103#define CONFIG_BOOTP_BOOTFILESIZE
 104
 105#undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 106
 107#define CONFIG_TIMESTAMP                /* but print image timestmps    */
 108
 109/*
 110 * Command line configuration.
 111 */
 112#include <config_cmd_default.h>
 113
 114#define CONFIG_CMD_ASKENV
 115#define CONFIG_CMD_DHCP
 116#define CONFIG_CMD_NFS
 117#define CONFIG_CMD_PING
 118
 119/*
 120 * Miscellaneous configurable options
 121 */
 122#define CFG_LONGHELP                    /* undef to save memory         */
 123#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 124
 125#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 126#define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 127#ifdef  CFG_HUSH_PARSER
 128#define CFG_PROMPT_HUSH_PS2     "> "
 129#endif
 130
 131#if defined(CONFIG_CMD_KGDB)
 132#define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 133#else
 134#define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 135#endif
 136#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 137#define CFG_MAXARGS             16      /* max number of command args   */
 138#define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 139
 140#define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 141#define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 142
 143#define CFG_LOAD_ADDR           0x100000        /* default load address */
 144
 145#define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 146
 147#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 148
 149/*
 150 * Low Level Configuration Settings
 151 * (address mappings, register initial values, etc.)
 152 * You should know what you are doing if you make changes here.
 153 */
 154/*-----------------------------------------------------------------------
 155 * Internal Memory Mapped Register
 156 */
 157#define CFG_IMMR                0xFFF00000
 158
 159/*-----------------------------------------------------------------------
 160 * Definitions for initial stack pointer and data area (in DPRAM)
 161 */
 162#define CFG_INIT_RAM_ADDR       CFG_IMMR
 163#define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 164#define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 165#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 166#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 167
 168/*-----------------------------------------------------------------------
 169 * Start addresses for the final memory configuration
 170 * (Set up by the startup code)
 171 * Please note that CFG_SDRAM_BASE _must_ start at 0
 172 */
 173#define CFG_SDRAM_BASE          0x00000000
 174#define CFG_FLASH_BASE          0xf0000000
 175#define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 176#define CFG_MONITOR_BASE        CFG_FLASH_BASE
 177#define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc()  */
 178
 179/*
 180 * For booting Linux, the board info and command line data
 181 * have to be in the first 8 MB of memory, since this is
 182 * the maximum mapped by the Linux kernel during initialization.
 183 */
 184#define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 185
 186/*-----------------------------------------------------------------------
 187 * FLASH organization
 188 */
 189#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 190#define CFG_FLASH_SIZE          32
 191#define CFG_FLASH_CFI
 192#define CONFIG_FLASH_CFI_DRIVER
 193#define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 194
 195
 196#define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 197#define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 198
 199#define CONFIG_ENV_IS_IN_FLASH  1
 200#define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 201#define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 202#define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 203
 204/* Address and size of Redundant Environment Sector     */
 205#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 206#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 207
 208/*-----------------------------------------------------------------------
 209 * Cache Configuration
 210 */
 211#define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 212#if defined(CONFIG_CMD_KGDB)
 213#define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 214#endif
 215
 216/*-----------------------------------------------------------------------
 217 * SYPCR - System Protection Control                            11-9
 218 * SYPCR can only be written once after reset!
 219 *-----------------------------------------------------------------------
 220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 221 */
 222#define CFG_SYPCR       0xffffff89
 223
 224/*-----------------------------------------------------------------------
 225 * SIUMCR - SIU Module Configuration                            11-6
 226 *-----------------------------------------------------------------------
 227 */
 228#define CFG_SIUMCR      0x00610480
 229
 230/*-----------------------------------------------------------------------
 231 * TBSCR - Time Base Status and Control                         11-26
 232 *-----------------------------------------------------------------------
 233 * Clear Reference Interrupt Status, Timebase freezing enabled
 234 */
 235#define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 236
 237/*-----------------------------------------------------------------------
 238 * PISCR - Periodic Interrupt Status and Control                11-31
 239 *-----------------------------------------------------------------------
 240 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 241 */
 242#define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 243
 244/*-----------------------------------------------------------------------
 245 * SCCR - System Clock and reset Control Register               15-27
 246 *-----------------------------------------------------------------------
 247 * Set clock output, timebase and RTC source and divider,
 248 * power management and some other internal clocks
 249 */
 250#define SCCR_MASK       0x01800000
 251#define CFG_SCCR        0x01800000
 252
 253#define CFG_DER 0
 254
 255/*
 256 * Init Memory Controller:
 257 *
 258 * BR0/1 and OR0/1 (FLASH)
 259 */
 260
 261#define FLASH_BASE0_PRELIM      0xf0000000      /* FLASH bank #0        */
 262
 263/* used to re-map FLASH both when starting from SRAM or FLASH:
 264 * restrict access enough to keep SRAM working (if any)
 265 * but not too much to meddle with FLASH accesses
 266 */
 267#define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 268#define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 269
 270/*
 271 * FLASH timing: Default value of OR0 after reset
 272 */
 273#define CFG_OR0_PRELIM  0xfe000954
 274#define CFG_BR0_PRELIM  0xf0000401
 275
 276/*
 277 * BR1 and OR1 (SDRAM)
 278 *
 279 */
 280#define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 281#define SDRAM_MAX_SIZE          (64 << 20)      /* max 64 MB per bank   */
 282
 283/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 284#define CFG_OR_TIMING_SDRAM     0x00000A00
 285
 286#define CFG_OR1_PRELIM  0xfc000800
 287#define CFG_BR1_PRELIM  (0x000000C0 | 0x01)
 288
 289#define CFG_MPTPR       0x0200
 290/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
 291   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
 292#define CFG_MBMR        0x10964111
 293#define CFG_MAR         0x00000088
 294
 295/*
 296 * 4096 Rows from SDRAM example configuration
 297 * 1000 factor s -> ms
 298 * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 299 * 4    Number of refresh cycles per period
 300 * 64   Refresh cycle in ms per number of rows
 301 */
 302#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
 303
 304/* GPIO/PIGGY on CS3 initialization values
 305*/
 306#define CFG_PIGGY_BASE  (0x30000000)
 307#define CFG_OR3_PRELIM  (0xfe000d24)
 308#define CFG_BR3_PRELIM  (0x30000401)
 309
 310/*
 311 * Internal Definitions
 312 *
 313 * Boot Flags
 314 */
 315#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 316#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 317
 318#define CONFIG_SCC3_ENET
 319#define CONFIG_ETHPRIME         "SCC ETHERNET"
 320#define CONFIG_HAS_ETH0
 321
 322/* pass open firmware flat tree */
 323#define CONFIG_OF_LIBFDT        1
 324#define CONFIG_OF_BOARD_SETUP   1
 325
 326#define OF_CPU                  "PowerPC,866@0"
 327#define OF_SOC                  "soc@fff00000"
 328#define OF_TBCLK                (bd->bi_busfreq / 4)
 329#define OF_STDOUT_PATH          "/soc/cpm/serial@a80"
 330
 331#endif  /* __CONFIG_H */
 332