uboot/board/hymod/hymod.c
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   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 *
  23 * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
  24 */
  25
  26#include <common.h>
  27#include <mpc8260.h>
  28#include <mpc8260_irq.h>
  29#include <ioports.h>
  30#include <i2c.h>
  31#include <asm/iopin_8260.h>
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35/* ------------------------------------------------------------------------- */
  36
  37/* imports from eeprom.c */
  38extern int hymod_eeprom_read (int, hymod_eeprom_t *);
  39extern void hymod_eeprom_print (hymod_eeprom_t *);
  40
  41/* imports from env.c */
  42extern void hymod_check_env (void);
  43
  44/* ------------------------------------------------------------------------- */
  45
  46/*
  47 * I/O Port configuration table
  48 *
  49 * if conf is 1, then that port pin will be configured at boot time
  50 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  51 */
  52
  53const iop_conf_t iop_conf_tab[4][32] = {
  54
  55        /* Port A configuration */
  56        {
  57                /* cnf par sor dir odr dat */
  58                {   1,  1,  1,  0,  0,  0   },  /* PA31: FCC1 MII COL */
  59                {   1,  1,  1,  0,  0,  0   },  /* PA30: FCC1 MII CRS */
  60                {   1,  1,  1,  1,  0,  0   },  /* PA29: FCC1 MII TX_ER */
  61                {   1,  1,  1,  1,  0,  0   },  /* PA28: FCC1 MII TX_EN */
  62                {   1,  1,  1,  0,  0,  0   },  /* PA27: FCC1 MII RX_DV */
  63                {   1,  1,  1,  0,  0,  0   },  /* PA26: FCC1 MII RX_ER */
  64                {   1,  0,  0,  1,  0,  0   },  /* PA25: FCC2 MII MDIO */
  65                {   1,  0,  0,  1,  0,  0   },  /* PA24: FCC2 MII MDC */
  66                {   1,  0,  0,  1,  0,  0   },  /* PA23: FCC3 MII MDIO */
  67                {   1,  0,  0,  1,  0,  0   },  /* PA22: FCC3 MII MDC */
  68                {   1,  1,  0,  1,  0,  0   },  /* PA21: FCC1 MII TxD[3] */
  69                {   1,  1,  0,  1,  0,  0   },  /* PA20: FCC1 MII TxD[2] */
  70                {   1,  1,  0,  1,  0,  0   },  /* PA19: FCC1 MII TxD[1] */
  71                {   1,  1,  0,  1,  0,  0   },  /* PA18: FCC1 MII TxD[0] */
  72                {   1,  1,  0,  0,  0,  0   },  /* PA17: FCC1 MII RxD[3] */
  73                {   1,  1,  0,  0,  0,  0   },  /* PA16: FCC1 MII RxD[2] */
  74                {   1,  1,  0,  0,  0,  0   },  /* PA15: FCC1 MII RxD[1] */
  75                {   1,  1,  0,  0,  0,  0   },  /* PA14: FCC1 MII RxD[0] */
  76                {   1,  0,  0,  1,  0,  0   },  /* PA13: FCC1 MII MDIO */
  77                {   1,  0,  0,  1,  0,  0   },  /* PA12: FCC1 MII MDC */
  78                {   1,  0,  0,  1,  0,  0   },  /* PA11: SEL_CD */
  79                {   1,  0,  0,  0,  0,  0   },  /* PA10: FLASH STS1 */
  80                {   1,  0,  0,  0,  0,  0   },  /* PA09: FLASH STS0 */
  81                {   1,  0,  0,  0,  0,  0   },  /* PA08: FLASH ~PE */
  82                {   1,  0,  0,  0,  0,  0   },  /* PA07: WATCH ~HRESET */
  83                {   1,  0,  0,  0,  1,  0   },  /* PA06: VC DONE */
  84                {   1,  0,  0,  1,  1,  0   },  /* PA05: VC INIT */
  85                {   1,  0,  0,  1,  0,  0   },  /* PA04: VC ~PROG */
  86                {   1,  0,  0,  1,  0,  0   },  /* PA03: VM ENABLE */
  87                {   1,  0,  0,  0,  1,  0   },  /* PA02: VM DONE */
  88                {   1,  0,  0,  1,  1,  0   },  /* PA01: VM INIT */
  89                {   1,  0,  0,  1,  0,  0   }   /* PA00: VM ~PROG */
  90        },
  91
  92        /* Port B configuration */
  93        {
  94                /* cnf par sor dir odr dat */
  95                {   1,  1,  0,  1,  0,  0   },  /* PB31: FCC2 MII TX_ER */
  96                {   1,  1,  0,  0,  0,  0   },  /* PB30: FCC2 MII RX_DV */
  97                {   1,  1,  1,  1,  0,  0   },  /* PB29: FCC2 MII TX_EN */
  98                {   1,  1,  0,  0,  0,  0   },  /* PB28: FCC2 MII RX_ER */
  99                {   1,  1,  0,  0,  0,  0   },  /* PB27: FCC2 MII COL */
 100                {   1,  1,  0,  0,  0,  0   },  /* PB26: FCC2 MII CRS */
 101                {   1,  1,  0,  1,  0,  0   },  /* PB25: FCC2 MII TxD[3] */
 102                {   1,  1,  0,  1,  0,  0   },  /* PB24: FCC2 MII TxD[2] */
 103                {   1,  1,  0,  1,  0,  0   },  /* PB23: FCC2 MII TxD[1] */
 104                {   1,  1,  0,  1,  0,  0   },  /* PB22: FCC2 MII TxD[0] */
 105                {   1,  1,  0,  0,  0,  0   },  /* PB21: FCC2 MII RxD[0] */
 106                {   1,  1,  0,  0,  0,  0   },  /* PB20: FCC2 MII RxD[1] */
 107                {   1,  1,  0,  0,  0,  0   },  /* PB19: FCC2 MII RxD[2] */
 108                {   1,  1,  0,  0,  0,  0   },  /* PB18: FCC2 MII RxD[3] */
 109                {   1,  1,  0,  0,  0,  0   },  /* PB17: FCC3 MII RX_DV */
 110                {   1,  1,  0,  0,  0,  0   },  /* PB16: FCC3 MII RX_ER */
 111                {   1,  1,  0,  1,  0,  0   },  /* PB15: FCC3 MII TX_ER */
 112                {   1,  1,  0,  1,  0,  0   },  /* PB14: FCC3 MII TX_EN */
 113                {   1,  1,  0,  0,  0,  0   },  /* PB13: FCC3 MII COL */
 114                {   1,  1,  0,  0,  0,  0   },  /* PB12: FCC3 MII CRS */
 115                {   1,  1,  0,  0,  0,  0   },  /* PB11: FCC3 MII RxD[3] */
 116                {   1,  1,  0,  0,  0,  0   },  /* PB10: FCC3 MII RxD[2] */
 117                {   1,  1,  0,  0,  0,  0   },  /* PB09: FCC3 MII RxD[1] */
 118                {   1,  1,  0,  0,  0,  0   },  /* PB08: FCC3 MII RxD[0] */
 119                {   1,  1,  0,  1,  0,  0   },  /* PB07: FCC3 MII TxD[3] */
 120                {   1,  1,  0,  1,  0,  0   },  /* PB06: FCC3 MII TxD[2] */
 121                {   1,  1,  0,  1,  0,  0   },  /* PB05: FCC3 MII TxD[1] */
 122                {   1,  1,  0,  1,  0,  0   },  /* PB04: FCC3 MII TxD[0] */
 123                {   0,  0,  0,  0,  0,  0   },  /* PB03: pin doesn't exist */
 124                {   0,  0,  0,  0,  0,  0   },  /* PB02: pin doesn't exist */
 125                {   0,  0,  0,  0,  0,  0   },  /* PB01: pin doesn't exist */
 126                {   0,  0,  0,  0,  0,  0   }   /* PB00: pin doesn't exist */
 127        },
 128
 129        /* Port C configuration */
 130        {
 131                /* cnf par sor dir odr dat */
 132                {   1,  0,  0,  0,  0,  0   },  /* PC31: MEZ ~IACK */
 133                {   0,  0,  0,  0,  0,  0   },  /* PC30: ? */
 134                {   1,  1,  0,  0,  0,  0   },  /* PC29: CLK SCCx */
 135                {   1,  1,  0,  0,  0,  0   },  /* PC28: CLK4 */
 136                {   1,  1,  0,  0,  0,  0   },  /* PC27: CLK SCCF */
 137                {   1,  1,  0,  0,  0,  0   },  /* PC26: CLK 32K */
 138                {   1,  1,  0,  0,  0,  0   },  /* PC25: BRG4/CLK7 */
 139                {   0,  0,  0,  0,  0,  0   },  /* PC24: ? */
 140                {   1,  1,  0,  0,  0,  0   },  /* PC23: CLK SCCx */
 141                {   1,  1,  0,  0,  0,  0   },  /* PC22: FCC1 MII RX_CLK */
 142                {   1,  1,  0,  0,  0,  0   },  /* PC21: FCC1 MII TX_CLK */
 143                {   1,  1,  0,  0,  0,  0   },  /* PC20: CLK SCCF */
 144                {   1,  1,  0,  0,  0,  0   },  /* PC19: FCC2 MII RX_CLK */
 145                {   1,  1,  0,  0,  0,  0   },  /* PC18: FCC2 MII TX_CLK */
 146                {   1,  1,  0,  0,  0,  0   },  /* PC17: FCC3 MII RX_CLK */
 147                {   1,  1,  0,  0,  0,  0   },  /* PC16: FCC3 MII TX_CLK */
 148                {   1,  0,  0,  0,  0,  0   },  /* PC15: SCC1 UART ~CTS */
 149                {   1,  0,  0,  0,  0,  0   },  /* PC14: SCC1 UART ~CD */
 150                {   1,  0,  0,  0,  0,  0   },  /* PC13: SCC2 UART ~CTS */
 151                {   1,  0,  0,  0,  0,  0   },  /* PC12: SCC2 UART ~CD */
 152                {   1,  0,  0,  1,  0,  0   },  /* PC11: SCC1 UART ~DTR */
 153                {   1,  0,  0,  1,  0,  0   },  /* PC10: SCC1 UART ~DSR */
 154                {   1,  0,  0,  1,  0,  0   },  /* PC09: SCC2 UART ~DTR */
 155                {   1,  0,  0,  1,  0,  0   },  /* PC08: SCC2 UART ~DSR */
 156                {   1,  0,  0,  0,  0,  0   },  /* PC07: TEMP ~ALERT */
 157                {   1,  0,  0,  0,  0,  0   },  /* PC06: FCC3 INT */
 158                {   1,  0,  0,  0,  0,  0   },  /* PC05: FCC2 INT */
 159                {   1,  0,  0,  0,  0,  0   },  /* PC04: FCC1 INT */
 160                {   0,  1,  1,  1,  0,  0   },  /* PC03: SDMA IDMA2 ~DACK */
 161                {   0,  1,  1,  0,  0,  0   },  /* PC02: SDMA IDMA2 ~DONE */
 162                {   0,  1,  0,  0,  0,  0   },  /* PC01: SDMA IDMA2 ~DREQ */
 163                {   1,  1,  0,  1,  0,  0   }   /* PC00: BRG7 */
 164        },
 165
 166        /* Port D configuration */
 167        {
 168                /* cnf par sor dir odr dat */
 169                {   1,  1,  0,  0,  0,  0   },  /* PD31: SCC1 UART RxD */
 170                {   1,  1,  1,  1,  0,  0   },  /* PD30: SCC1 UART TxD */
 171                {   1,  0,  0,  1,  0,  0   },  /* PD29: SCC1 UART ~RTS */
 172                {   1,  1,  0,  0,  0,  0   },  /* PD28: SCC2 UART RxD */
 173                {   1,  1,  0,  1,  0,  0   },  /* PD27: SCC2 UART TxD */
 174                {   1,  0,  0,  1,  0,  0   },  /* PD26: SCC2 UART ~RTS */
 175                {   1,  0,  0,  0,  0,  0   },  /* PD25: SCC1 UART ~RI */
 176                {   1,  0,  0,  0,  0,  0   },  /* PD24: SCC2 UART ~RI */
 177                {   1,  0,  0,  1,  0,  0   },  /* PD23: CLKGEN PD */
 178                {   1,  0,  0,  0,  0,  0   },  /* PD22: USER3 */
 179                {   1,  0,  0,  0,  0,  0   },  /* PD21: USER2 */
 180                {   1,  0,  0,  0,  0,  0   },  /* PD20: USER1 */
 181                {   1,  1,  1,  0,  0,  0   },  /* PD19: SPI ~SEL */
 182                {   1,  1,  1,  0,  0,  0   },  /* PD18: SPI CLK */
 183                {   1,  1,  1,  0,  0,  0   },  /* PD17: SPI MOSI */
 184                {   1,  1,  1,  0,  0,  0   },  /* PD16: SPI MISO */
 185                {   1,  1,  1,  0,  1,  0   },  /* PD15: I2C SDA */
 186                {   1,  1,  1,  0,  1,  0   },  /* PD14: I2C SCL */
 187                {   1,  0,  0,  1,  0,  1   },  /* PD13: TEMP ~STDBY */
 188                {   1,  0,  0,  1,  0,  1   },  /* PD12: FCC3 ~RESET */
 189                {   1,  0,  0,  1,  0,  1   },  /* PD11: FCC2 ~RESET */
 190                {   1,  0,  0,  1,  0,  1   },  /* PD10: FCC1 ~RESET */
 191                {   1,  0,  0,  0,  0,  0   },  /* PD09: PD9 */
 192                {   1,  0,  0,  0,  0,  0   },  /* PD08: PD8 */
 193                {   1,  0,  0,  1,  0,  1   },  /* PD07: PD7 */
 194                {   1,  0,  0,  1,  0,  1   },  /* PD06: PD6 */
 195                {   1,  0,  0,  1,  0,  1   },  /* PD05: PD5 */
 196                {   1,  0,  0,  1,  0,  1   },  /* PD04: PD4 */
 197                {   0,  0,  0,  0,  0,  0   },  /* PD03: pin doesn't exist */
 198                {   0,  0,  0,  0,  0,  0   },  /* PD02: pin doesn't exist */
 199                {   0,  0,  0,  0,  0,  0   },  /* PD01: pin doesn't exist */
 200                {   0,  0,  0,  0,  0,  0   }   /* PD00: pin doesn't exist */
 201        }
 202};
 203
 204/* ------------------------------------------------------------------------- */
 205
 206/*
 207 * AMI FS6377 Clock Generator configuration table
 208 *
 209 * the "fs6377_regs[]" table entries correspond to FS6377 registers
 210 * 0 - 15 (total of 16 bytes).
 211 *
 212 * the data is written to the FS6377 via the i2c bus using address in
 213 * "fs6377_addr" (address is 7 bits - R/W bit not included).
 214 *
 215 * The fs6377 has four clock outputs: A, B, C and D.
 216 *
 217 * Outputs C and D can each provide two different clock outputs C1/D1 or
 218 * C2/D2 depending on the state of the SEL_CD input which is connected to
 219 * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
 220 * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
 221 *
 222 * PA11 defaults to output low (or 0) in the i/o port config table above.
 223 *
 224 * Output A provides a 100MHz for the High Speed Serial chips. Output B
 225 * provides a 3.6864MHz clock for more accurate asynchronous serial bit
 226 * rates. Output C is routed to the mezzanine connector but is currently
 227 * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
 228 * alt-input and display mezzanine boards for their video chips. The
 229 * alt-input board requires a clock of 24.576MHz and this is available on
 230 * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
 231 * is available on D2 (PA11=SEL_CD=1).
 232 *
 233 * So the default is a clock suitable for the alt-input board. PA11 is toggled
 234 * later in misc_init_r(), if a display board is detected.
 235 */
 236
 237uchar fs6377_addr = 0x5c;
 238
 239uchar fs6377_regs[16] = {
 240         12,  75,  64,  25, 144, 128,  25, 192,
 241          0,  16, 135, 192, 224,  64,  64, 192
 242};
 243
 244/* ------------------------------------------------------------------------- */
 245
 246/*
 247 * special board initialisation, after clocks and timebase have been
 248 * set up but before environment and serial are initialised.
 249 *
 250 * added so that very early initialisations can be done using the i2c
 251 * driver (which requires the clocks, to calculate the dividers, and
 252 * the timebase, for udelay())
 253 */
 254
 255int
 256board_postclk_init (void)
 257{
 258        i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 259
 260        /*
 261         * Initialise the FS6377 clock chip
 262         *
 263         * the secondary address is the register number from where to
 264         * start the write - I want to write all the registers
 265         *
 266         * don't bother checking return status - we have no console yet
 267         * to print it on, nor any RAM to store it in - it will be obvious
 268         * if this doesn't work
 269         */
 270        (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
 271                                        sizeof (fs6377_regs));
 272
 273        return (0);
 274}
 275
 276/* ------------------------------------------------------------------------- */
 277
 278/*
 279 * Check Board Identity: Hardwired to HYMOD
 280 */
 281
 282int
 283checkboard (void)
 284{
 285        puts ("Board: HYMOD\n");
 286        return (0);
 287}
 288
 289/* ------------------------------------------------------------------------- */
 290
 291/*
 292 * miscellaneous (early - while running in flash) initialisations.
 293 */
 294
 295#define _NOT_USED_      0xFFFFFFFF
 296
 297uint upmb_table[] = {
 298        /* Read Single Beat (RSS) - offset 0x00 */
 299        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 300        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 301        /* Read Burst (RBS) - offset 0x08 */
 302        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 303        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 304        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 305        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 306        /* Write Single Beat (WSS) - offset 0x18 */
 307        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 308        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 309        /* Write Burst (WSS) - offset 0x20 */
 310        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 311        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 312        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 313        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 314        /* Refresh Timer (PTS) - offset 0x30 */
 315        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 316        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 317        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 318        /* Exception Condition (EXS) - offset 0x3c */
 319        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 320};
 321
 322uint upmc_table[] = {
 323        /* Read Single Beat (RSS) - offset 0x00 */
 324        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 325        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 326        /* Read Burst (RBS) - offset 0x08 */
 327        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 328        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 329        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 330        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 331        /* Write Single Beat (WSS) - offset 0x18 */
 332        0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
 333        0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 334        /* Write Burst (WSS) - offset 0x20 */
 335        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 336        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 337        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 338        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 339        /* Refresh Timer (PTS) - offset 0x30 */
 340        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 341        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 342        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 343        /* Exception Condition (EXS) - offset 0x3c */
 344        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 345};
 346
 347int
 348misc_init_f (void)
 349{
 350        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 351        volatile memctl8260_t *memctl = &immap->im_memctl;
 352
 353        printf ("UPMs:  ");
 354
 355        upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
 356        memctl->memc_mbmr = CONFIG_SYS_MBMR;
 357
 358        upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
 359        memctl->memc_mcmr = CONFIG_SYS_MCMR;
 360
 361        printf ("configured\n");
 362        return (0);
 363}
 364
 365/* ------------------------------------------------------------------------- */
 366
 367phys_size_t
 368initdram (int board_type)
 369{
 370        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 371        volatile memctl8260_t *memctl = &immap->im_memctl;
 372        volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
 373        ulong psdmr = CONFIG_SYS_PSDMR;
 374        int i;
 375
 376        /*
 377         * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 378         *
 379         * "At system reset, initialization software must set up the
 380         *  programmable parameters in the memory controller banks registers
 381         *  (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured,
 382         *  system software should execute the following initialization sequence
 383         *  for each SDRAM device.
 384         *
 385         *  1. Issue a PRECHARGE-ALL-BANKS command
 386         *  2. Issue eight CBR REFRESH commands
 387         *  3. Issue a MODE-SET command to initialize the mode register
 388         *
 389         *  The initial commands are executed by setting P/LSDMR[OP] and
 390         *  accessing the SDRAM with a single-byte transaction."
 391         *
 392         * The appropriate BRx/ORx registers have already been set when we
 393         * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 394         */
 395
 396        memctl->memc_psrt = CONFIG_SYS_PSRT;
 397        memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 398
 399        memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 400        *ramaddr = c;
 401
 402        memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
 403        for (i = 0; i < 8; i++)
 404                *ramaddr = c;
 405
 406        memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
 407        *ramaddr = c;
 408
 409        memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 410        *ramaddr = c;
 411
 412        return (CONFIG_SYS_SDRAM_SIZE << 20);
 413}
 414
 415/* ------------------------------------------------------------------------- */
 416/* miscellaneous initialisations after relocation into ram (misc_init_r)     */
 417/*                                                                           */
 418/* loads the data in the main board and mezzanine board eeproms into         */
 419/* the hymod configuration struct stored in the board information area.      */
 420/*                                                                           */
 421/* if the contents of either eeprom is invalid, prompts for a serial         */
 422/* number (and an ethernet address if required) then fetches a file          */
 423/* containing information to be stored in the eeprom from the tftp server    */
 424/* (the file name is based on the serial number and a built-in path)         */
 425
 426int
 427last_stage_init (void)
 428{
 429        hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 430        int rc;
 431
 432#ifdef CONFIG_BOOT_RETRY_TIME
 433        /*
 434         * we use the readline () function, but we also want
 435         * command timeout enabled
 436         */
 437        init_cmd_timeout ();
 438#endif
 439
 440        memset ((void *) cp, 0, sizeof (*cp));
 441
 442        /* set up main board config info */
 443
 444        rc = hymod_eeprom_read (0, &cp->main.eeprom);
 445
 446        puts ("EEPROM:main...");
 447        if (rc < 0)
 448                puts ("NOT PRESENT\n");
 449        else if (rc == 0)
 450                puts ("INVALID\n");
 451        else {
 452                cp->main.eeprom.valid = 1;
 453
 454                printf ("OK (ver %u)\n", cp->main.eeprom.ver);
 455                hymod_eeprom_print (&cp->main.eeprom);
 456
 457                /*
 458                 * hard-wired assumption here: all hymod main boards will have
 459                 * one xilinx fpga, with the interrupt line connected to IRQ2
 460                 *
 461                 * One day, this might be based on the board type
 462                 */
 463
 464                cp->main.xlx[0].mmap.prog.exists = 1;
 465                cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
 466                cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
 467
 468                cp->main.xlx[0].mmap.reg.exists = 1;
 469                cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
 470                cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
 471
 472                cp->main.xlx[0].mmap.port.exists = 1;
 473                cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
 474                cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
 475
 476                cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
 477                cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
 478                cp->main.xlx[0].iopins.prog_pin.flag = 1;
 479                cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
 480                cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
 481                cp->main.xlx[0].iopins.init_pin.flag = 1;
 482                cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
 483                cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
 484                cp->main.xlx[0].iopins.done_pin.flag = 1;
 485#ifdef FPGA_MAIN_ENABLE_PORT
 486                cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
 487                cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
 488                cp->main.xlx[0].iopins.enable_pin.flag = 1;
 489#endif
 490
 491                cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
 492        }
 493
 494        /* set up mezzanine board config info */
 495
 496        rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
 497
 498        puts ("EEPROM:mezz...");
 499        if (rc < 0)
 500                puts ("NOT PRESENT\n");
 501        else if (rc == 0)
 502                puts ("INVALID\n");
 503        else {
 504                cp->main.eeprom.valid = 1;
 505
 506                printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
 507                hymod_eeprom_print (&cp->mezz.eeprom);
 508        }
 509
 510        cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
 511
 512        hymod_check_env ();
 513
 514        return (0);
 515}
 516
 517#ifdef CONFIG_SHOW_ACTIVITY
 518void board_show_activity (ulong timebase)
 519{
 520#ifdef CONFIG_SYS_HYMOD_DBLEDS
 521        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 522        volatile iop8260_t *iop = &immr->im_ioport;
 523        static int shift = 0;
 524
 525        if ((timestamp % CONFIG_SYS_HZ) == 0) {
 526                if (++shift > 3)
 527                        shift = 0;
 528                iop->iop_pdatd =
 529                                (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
 530        }
 531#endif /* CONFIG_SYS_HYMOD_DBLEDS */
 532}
 533
 534void show_activity(int arg)
 535{
 536}
 537#endif /* CONFIG_SHOW_ACTIVITY */
 538
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.