1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include <common.h>
29#include <ppc4xx.h>
30#include <4xx_i2c.h>
31#include <i2c.h>
32#include <command.h>
33#include "ppc440gx_i2c.h"
34
35#ifdef CONFIG_I2C_BUS1
36
37#define IIC_OK 0
38#define IIC_NOK 1
39#define IIC_NOK_LA 2
40#define IIC_NOK_ICT 3
41#define IIC_NOK_XFRA 4
42#define IIC_NOK_DATA 5
43#define IIC_NOK_TOUT 6
44
45#define IIC_TIMEOUT 1
46#if defined(CONFIG_SYS_I2C_NOPROBES)
47static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
48#endif
49
50static void _i2c_bus1_reset (void)
51{
52 int i, status;
53
54
55
56 out8 (IIC_STS1, 0x0A);
57
58
59 out8 (IIC_EXTSTS1, 0x8F);
60 __asm__ volatile ("eieio");
61
62
63
64
65
66 i = 10;
67 do {
68
69 status = in8 (IIC_STS1);
70 udelay (500);
71 i--;
72 } while ((status & IIC_STS_PT) && (i > 0));
73
74 status = in8 (IIC_XTCNTLSS1);
75 out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
76 __asm__ volatile ("eieio");
77
78
79 out8 (IIC_DIRECTCNTL1, 0xC);
80 for (i = 0; i < 10; i++) {
81 if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
82
83 out8 (IIC_DIRECTCNTL1, 0x8);
84 udelay (100);
85 out8 (IIC_DIRECTCNTL1, 0xC);
86 udelay (100);
87 } else {
88 break;
89 }
90 }
91
92 out8 (IIC_DIRECTCNTL1, 0x4);
93 udelay (1000);
94
95 out8 (IIC_DIRECTCNTL1, 0xC);
96 udelay (1000);
97
98 out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
99 udelay (1000);
100}
101
102void i2c1_init (int speed, int slaveadd)
103{
104 sys_info_t sysInfo;
105 unsigned long freqOPB;
106 int val, divisor;
107
108#ifdef CONFIG_SYS_I2C_INIT_BOARD
109
110
111
112 i2c_init_board();
113#endif
114
115
116
117 _i2c_bus1_reset ();
118
119
120 out8 (IIC_LMADR1, 0);
121
122
123 out8 (IIC_HMADR1, 0);
124
125
126 out8 (IIC_LSADR1, 0);
127
128
129 out8 (IIC_HSADR1, 0);
130
131
132
133 get_sys_info (&sysInfo);
134 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
135
136 divisor = (freqOPB - 1) / 10000000;
137 if (divisor == 0)
138 divisor = 1;
139 out8 (IIC_CLKDIV1, divisor);
140
141
142 out8 (IIC_INTRMSK1, 0);
143
144
145 out8 (IIC_XFRCNT1, 0);
146
147
148
149 out8 (IIC_XTCNTLSS1, 0xF0);
150
151
152
153 out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
154 __asm__ volatile ("eieio");
155
156
157 val = in8(IIC_MDCNTL1);
158 __asm__ volatile ("eieio");
159
160
161
162
163
164
165
166 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
167 if( speed >= 400000 ){
168 val |= IIC_MDCNTL_FSM;
169 }
170 out8 (IIC_MDCNTL1, val);
171
172
173 out8 (IIC_CNTL1, 0x00);
174 __asm__ volatile ("eieio");
175
176}
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203static
204int i2c_transfer1(unsigned char cmd_type,
205 unsigned char chip,
206 unsigned char addr[],
207 unsigned char addr_len,
208 unsigned char data[],
209 unsigned short data_len )
210{
211 unsigned char* ptr;
212 int reading;
213 int tran,cnt;
214 int result;
215 int status;
216 int i;
217 uchar creg;
218
219 if( data == 0 || data_len == 0 ){
220
221 printf( "i2c_transfer: bad call\n" );
222 return IIC_NOK;
223 }
224 if( addr && addr_len ){
225 ptr = addr;
226 cnt = addr_len;
227 reading = 0;
228 }else{
229 ptr = data;
230 cnt = data_len;
231 reading = cmd_type;
232 }
233
234
235 out8(IIC_STS1,IIC_STS_SCMP);
236
237 i=10;
238 do {
239
240 status = in8(IIC_STS1);
241 __asm__ volatile("eieio");
242 i--;
243 } while ((status & IIC_STS_PT) && (i>0));
244
245 if (status & IIC_STS_PT) {
246 result = IIC_NOK_TOUT;
247 return(result);
248 }
249
250 out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
251
252
253
254 out8(IIC_HMADR1,0);
255 out8(IIC_LMADR1, chip);
256 __asm__ volatile("eieio");
257
258 tran = 0;
259 result = IIC_OK;
260 creg = 0;
261
262 while ( tran != cnt && (result == IIC_OK)) {
263 int bc,j;
264
265
266
267
268
269 creg |= IIC_CNTL_PT;
270
271 bc = (cnt - tran) > 4 ? 4 :
272 cnt - tran;
273 creg |= (bc-1)<<4;
274
275 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
276 creg |= IIC_CNTL_CHT;
277
278 if (reading)
279 creg |= IIC_CNTL_READ;
280 else {
281 for(j=0; j<bc; j++) {
282
283 out8(IIC_MDBUF1,ptr[tran+j]);
284 __asm__ volatile("eieio");
285 }
286 }
287 out8(IIC_CNTL1, creg );
288 __asm__ volatile("eieio");
289
290
291
292
293
294
295
296
297 i=2*5*8;
298 do {
299
300 status = in8(IIC_STS1);
301 __asm__ volatile("eieio");
302 udelay (10);
303 i--;
304 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
305 && (i>0));
306
307 if (status & IIC_STS_ERR) {
308 result = IIC_NOK;
309 status = in8 (IIC_EXTSTS1);
310
311 if (status & IIC_EXTSTS_LA)
312 result = IIC_NOK_LA;
313
314 if (status & IIC_EXTSTS_ICT)
315 result = IIC_NOK_ICT;
316
317 if (status & IIC_EXTSTS_XFRA)
318 result = IIC_NOK_XFRA;
319 } else if ( status & IIC_STS_PT) {
320 result = IIC_NOK_TOUT;
321 }
322
323 if ((reading) && (result == IIC_OK)) {
324
325 if (status & IIC_STS_MDBS) {
326
327
328
329
330
331
332 udelay (1);
333 for(j=0;j<bc;j++) {
334 ptr[tran+j] = in8(IIC_MDBUF1);
335 __asm__ volatile("eieio");
336 }
337 } else
338 result = IIC_NOK_DATA;
339 }
340 creg = 0;
341 tran+=bc;
342 if( ptr == addr && tran == cnt ) {
343 ptr = data;
344 cnt = data_len;
345 tran = 0;
346 reading = cmd_type;
347 if( reading )
348 creg = IIC_CNTL_RPST;
349 }
350 }
351 return (result);
352}
353
354int i2c_probe1 (uchar chip)
355{
356 uchar buf[1];
357
358 buf[0] = 0;
359
360
361
362
363
364
365 return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
366}
367
368
369int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
370{
371 uchar xaddr[4];
372 int ret;
373
374 if ( alen > 4 ) {
375 printf ("I2C read: addr len %d not supported\n", alen);
376 return 1;
377 }
378
379 if ( alen > 0 ) {
380 xaddr[0] = (addr >> 24) & 0xFF;
381 xaddr[1] = (addr >> 16) & 0xFF;
382 xaddr[2] = (addr >> 8) & 0xFF;
383 xaddr[3] = addr & 0xFF;
384 }
385
386
387#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
388
389
390
391
392
393
394
395
396
397
398
399 if( alen > 0 )
400 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
401#endif
402 if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
403 printf( "I2c read: failed %d\n", ret);
404 return 1;
405 }
406 return 0;
407}
408
409int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
410{
411 uchar xaddr[4];
412
413 if ( alen > 4 ) {
414 printf ("I2C write: addr len %d not supported\n", alen);
415 return 1;
416
417 }
418 if ( alen > 0 ) {
419 xaddr[0] = (addr >> 24) & 0xFF;
420 xaddr[1] = (addr >> 16) & 0xFF;
421 xaddr[2] = (addr >> 8) & 0xFF;
422 xaddr[3] = addr & 0xFF;
423 }
424
425#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
426
427
428
429
430
431
432
433
434
435
436
437 if( alen > 0 )
438 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
439#endif
440
441 return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
442}
443
444
445
446
447uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
448{
449 uchar buf;
450
451 i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
452
453 return(buf);
454}
455
456
457
458
459void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
460{
461 i2c_write1(i2c_addr, reg, 1, &val, 1);
462}
463
464
465int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
466{
467 int j;
468#if defined(CONFIG_SYS_I2C_NOPROBES)
469 int k, skip;
470#endif
471
472 puts ("Valid chip addresses:");
473 for(j = 0; j < 128; j++) {
474#if defined(CONFIG_SYS_I2C_NOPROBES)
475 skip = 0;
476 for (k = 0; k < sizeof(i2c_no_probes); k++){
477 if (j == i2c_no_probes[k]){
478 skip = 1;
479 break;
480 }
481 }
482 if (skip)
483 continue;
484#endif
485 if(i2c_probe1(j) == 0) {
486 printf(" %02X", j);
487 }
488 }
489 putc ('\n');
490
491#if defined(CONFIG_SYS_I2C_NOPROBES)
492 puts ("Excluded chip addresses:");
493 for( k = 0; k < sizeof(i2c_no_probes); k++ )
494 printf(" %02X", i2c_no_probes[k] );
495 putc ('\n');
496#endif
497
498 return 0;
499}
500
501U_BOOT_CMD(
502 iprobe1, 1, 1, do_i2c1_probe,
503 "iprobe1 - probe to discover valid I2C chip addresses\n",
504 "\n -discover valid I2C chip addresses\n"
505);
506
507#endif
508