LXR uboot/cpu/i386/interrupts.c

   1/*
   2 * (C) Copyright 2002
   3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <malloc.h>
  26#include <asm/io.h>
  27#include <asm/i8259.h>
  28#include <asm/ibmpc.h>
  29
  30
  31struct idt_entry {
  32        u16     base_low;
  33        u16     selector;
  34        u8      res;
  35        u8      access;
  36        u16     base_high;
  37} __attribute__ ((packed));
  38
  39
  40struct idt_entry idt[256];
  41
  42
  43#define MAX_IRQ 16
  44
  45typedef struct irq_handler {
  46        struct irq_handler *next;
  47        interrupt_handler_t* isr_func;
  48        void *isr_data;
  49} irq_handler_t;
  50
  51#define IRQ_DISABLED   1
  52
  53typedef struct {
  54        irq_handler_t *handler;
  55        unsigned long status;
  56} irq_desc_t;
  57
  58static irq_desc_t irq_table[MAX_IRQ];
  59
  60asm ("irq_return:\n"
  61     "     addl  $4, %esp\n"
  62     "     popa\n"
  63     "     iret\n");
  64
  65asm ("exp_return:\n"
  66     "     addl  $12, %esp\n"
  67     "     pop   %esp\n"
  68     "     popa\n"
  69     "     iret\n");
  70
  71char exception_stack[4096];
  72
  73#define DECLARE_INTERRUPT(x) \
  74        asm(".globl irq_"#x"\n" \
  75                    "irq_"#x":\n" \
  76                    "pusha \n" \
  77                    "pushl $"#x"\n" \
  78                    "pushl $irq_return\n" \
  79                    "jmp   do_irq\n"); \
  80        void __attribute__ ((regparm(0))) irq_##x(void)
  81
  82#define DECLARE_EXCEPTION(x, f) \
  83        asm(".globl exp_"#x"\n" \
  84                    "exp_"#x":\n" \
  85                    "pusha \n" \
  86                    "movl     %esp, %ebx\n" \
  87                    "movl     $exception_stack, %eax\n" \
  88                    "movl     %eax, %esp \n" \
  89                    "pushl    %ebx\n" \
  90                    "movl     32(%esp), %ebx\n" \
  91                    "xorl     %edx, %edx\n" \
  92                    "movw     36(%esp), %dx\n" \
  93                    "pushl    %edx\n" \
  94                    "pushl    %ebx\n" \
  95                    "pushl    $"#x"\n" \
  96                    "pushl    $exp_return\n" \
  97                    "jmp      "#f"\n"); \
  98        void __attribute__ ((regparm(0))) exp_##x(void)
  99
 100DECLARE_EXCEPTION(0, divide_exception_entry);      /* Divide exception */
 101DECLARE_EXCEPTION(1, debug_exception_entry);       /* Debug exception */
 102DECLARE_EXCEPTION(2, nmi_entry);                   /* NMI */
 103DECLARE_EXCEPTION(3, unknown_exception_entry);     /* Breakpoint/Coprocessor Error */
 104DECLARE_EXCEPTION(4, unknown_exception_entry);     /* Overflow */
 105DECLARE_EXCEPTION(5, unknown_exception_entry);     /* Bounds */
 106DECLARE_EXCEPTION(6, invalid_instruction_entry);   /* Invalid instruction */
 107DECLARE_EXCEPTION(7, unknown_exception_entry);     /* Device not present */
 108DECLARE_EXCEPTION(8, double_fault_entry);          /* Double fault */
 109DECLARE_EXCEPTION(9, unknown_exception_entry);     /* Co-processor segment overrun */
 110DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
 111DECLARE_EXCEPTION(11, seg_fault_entry);            /* Segment not present */
 112DECLARE_EXCEPTION(12, stack_fault_entry);          /* Stack overflow */
 113DECLARE_EXCEPTION(13, gpf_entry);                  /* GPF */
 114DECLARE_EXCEPTION(14, page_fault_entry);           /* PF */
 115DECLARE_EXCEPTION(15, unknown_exception_entry);    /* Reserved */
 116DECLARE_EXCEPTION(16, fp_exception_entry);         /* Floating point */
 117DECLARE_EXCEPTION(17, alignment_check_entry);      /* alignment check */
 118DECLARE_EXCEPTION(18, machine_check_entry);        /* machine check */
 119DECLARE_EXCEPTION(19, unknown_exception_entry);    /* Reserved */
 120DECLARE_EXCEPTION(20, unknown_exception_entry);    /* Reserved */
 121DECLARE_EXCEPTION(21, unknown_exception_entry);    /* Reserved */
 122DECLARE_EXCEPTION(22, unknown_exception_entry);    /* Reserved */
 123DECLARE_EXCEPTION(23, unknown_exception_entry);    /* Reserved */
 124DECLARE_EXCEPTION(24, unknown_exception_entry);    /* Reserved */
 125DECLARE_EXCEPTION(25, unknown_exception_entry);    /* Reserved */
 126DECLARE_EXCEPTION(26, unknown_exception_entry);    /* Reserved */
 127DECLARE_EXCEPTION(27, unknown_exception_entry);    /* Reserved */
 128DECLARE_EXCEPTION(28, unknown_exception_entry);    /* Reserved */
 129DECLARE_EXCEPTION(29, unknown_exception_entry);    /* Reserved */
 130DECLARE_EXCEPTION(30, unknown_exception_entry);    /* Reserved */
 131DECLARE_EXCEPTION(31, unknown_exception_entry);    /* Reserved */
 132
 133DECLARE_INTERRUPT(0);
 134DECLARE_INTERRUPT(1);
 135DECLARE_INTERRUPT(3);
 136DECLARE_INTERRUPT(4);
 137DECLARE_INTERRUPT(5);
 138DECLARE_INTERRUPT(6);
 139DECLARE_INTERRUPT(7);
 140DECLARE_INTERRUPT(8);
 141DECLARE_INTERRUPT(9);
 142DECLARE_INTERRUPT(10);
 143DECLARE_INTERRUPT(11);
 144DECLARE_INTERRUPT(12);
 145DECLARE_INTERRUPT(13);
 146DECLARE_INTERRUPT(14);
 147DECLARE_INTERRUPT(15);
 148
 149void __attribute__ ((regparm(0))) default_isr(void);
 150asm ("default_isr: iret\n");
 151
 152void disable_irq(int irq)
 153{
 154        if (irq >= MAX_IRQ) {
 155                return;
 156        }
 157        irq_table[irq].status |= IRQ_DISABLED;
 158
 159}
 160
 161void enable_irq(int irq)
 162{
 163        if (irq >= MAX_IRQ) {
 164                return;
 165        }
 166        irq_table[irq].status &= ~IRQ_DISABLED;
 167}
 168
 169/* masks one specific IRQ in the PIC */
 170static void unmask_irq(int irq)
 171{
 172        int imr_port;
 173
 174        if (irq >= MAX_IRQ) {
 175                return;
 176        }
 177        if (irq > 7) {
 178                imr_port = SLAVE_PIC + IMR;
 179        } else {
 180                imr_port = MASTER_PIC + IMR;
 181        }
 182
 183        outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
 184}
 185
 186
 187/* unmasks one specific IRQ in the PIC */
 188static void mask_irq(int irq)
 189{
 190        int imr_port;
 191
 192        if (irq >= MAX_IRQ) {
 193                return;
 194        }
 195        if (irq > 7) {
 196                imr_port = SLAVE_PIC + IMR;
 197        } else {
 198                imr_port = MASTER_PIC + IMR;
 199        }
 200
 201        outb(inb(imr_port)|(1<<(irq&7)), imr_port);
 202}
 203
 204
 205/* issue a Specific End Of Interrupt instruciton */
 206static void specific_eoi(int irq)
 207{
 208        /* If it is on the slave PIC this have to be performed on
 209         * both the master and the slave PICs */
 210        if (irq > 7) {
 211                outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
 212                irq = SEOI_IR2;               /* also do IR2 on master */
 213        }
 214        outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
 215}
 216
 217void __attribute__ ((regparm(0))) do_irq(int irq)
 218{
 219
 220        mask_irq(irq);
 221
 222        if (irq_table[irq].status & IRQ_DISABLED) {
 223                unmask_irq(irq);
 224                specific_eoi(irq);
 225                return;
 226        }
 227
 228
 229        if (NULL != irq_table[irq].handler) {
 230                irq_handler_t *handler;
 231                for (handler = irq_table[irq].handler;
 232                     NULL!= handler; handler = handler->next) {
 233                        handler->isr_func(handler->isr_data);
 234                }
 235        } else {
 236                if ((irq & 7) != 7) {
 237                        printf("Spurious irq %d\n", irq);
 238                }
 239        }
 240        unmask_irq(irq);
 241        specific_eoi(irq);
 242}
 243
 244
 245void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
 246{
 247        printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
 248}
 249
 250void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
 251{
 252        printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
 253        while(1);
 254}
 255
 256void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
 257{
 258        printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
 259}
 260
 261void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
 262{
 263        printf("NMI Interrupt at %04x:%08x\n", seg, ip);
 264}
 265
 266void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
 267{
 268        printf("Invalid Instruction at %04x:%08x\n", seg, ip);
 269        while(1);
 270}
 271
 272void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
 273{
 274        printf("Double fault at %04x:%08x\n", seg, ip);
 275        while(1);
 276}
 277
 278void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
 279{
 280        printf("Invalid TSS at %04x:%08x\n", seg, ip);
 281}
 282
 283void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
 284{
 285        printf("Segmentation fault at %04x:%08x\n", seg, ip);
 286        while(1);
 287}
 288
 289void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
 290{
 291        printf("Stack fault at %04x:%08x\n", seg, ip);
 292        while(1);
 293}
 294
 295void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
 296{
 297        printf("General protection fault at %04x:%08x\n", seg, ip);
 298}
 299
 300void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
 301{
 302        printf("Page fault at %04x:%08x\n", seg, ip);
 303        while(1);
 304}
 305
 306void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
 307{
 308        printf("Floating point exception at %04x:%08x\n", seg, ip);
 309}
 310
 311void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
 312{
 313        printf("Alignment check at %04x:%08x\n", seg, ip);
 314}
 315
 316void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
 317{
 318        printf("Machine check exception at %04x:%08x\n", seg, ip);
 319}
 320
 321
 322void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
 323{
 324        int status;
 325
 326        if (ino>MAX_IRQ) {
 327                return;
 328        }
 329
 330        if (NULL != irq_table[ino].handler) {
 331                return;
 332        }
 333
 334        status = disable_interrupts();
 335        irq_table[ino].handler = malloc(sizeof(irq_handler_t));
 336        if (NULL == irq_table[ino].handler) {
 337                return;
 338        }
 339
 340        memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
 341
 342        irq_table[ino].handler->isr_func = func;
 343        irq_table[ino].handler->isr_data = pdata;
 344        if (status) {
 345                enable_interrupts();
 346        }
 347
 348        unmask_irq(ino);
 349
 350        return;
 351}
 352
 353void irq_free_handler(int ino)
 354{
 355        int status;
 356        if (ino>MAX_IRQ) {
 357                return;
 358        }
 359
 360        status = disable_interrupts();
 361        mask_irq(ino);
 362        if (NULL == irq_table[ino].handler) {
 363                return;
 364        }
 365        free(irq_table[ino].handler);
 366        irq_table[ino].handler=NULL;
 367        if (status) {
 368                enable_interrupts();
 369        }
 370        return;
 371}
 372
 373
 374asm ("idt_ptr:\n"
 375        ".word  0x800\n" /* size of the table 8*256 bytes */
 376        ".long  idt\n"   /* offset */
 377        ".word  0x18\n");/* data segment */
 378
 379static void set_vector(int intnum, void *routine)
 380{
 381        idt[intnum].base_high = (u16)((u32)(routine)>>16);
 382        idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
 383}
 384
 385
 386int interrupt_init(void)
 387{
 388        int i;
 389
 390        /* Just in case... */
 391        disable_interrupts();
 392
 393        /* Initialize the IDT and stuff */
 394
 395
 396        memset(irq_table, 0, sizeof(irq_table));
 397
 398        /* Setup the IDT */
 399        for (i=0;i<256;i++) {
 400                idt[i].access = 0x8e;
 401                idt[i].res = 0;
 402                idt[i].selector = 0x10;
 403                set_vector(i, default_isr);
 404        }
 405
 406        asm ("cs lidt idt_ptr\n");
 407
 408        /* Setup exceptions */
 409        set_vector(0x00, exp_0);
 410        set_vector(0x01, exp_1);
 411        set_vector(0x02, exp_2);
 412        set_vector(0x03, exp_3);
 413        set_vector(0x04, exp_4);
 414        set_vector(0x05, exp_5);
 415        set_vector(0x06, exp_6);
 416        set_vector(0x07, exp_7);
 417        set_vector(0x08, exp_8);
 418        set_vector(0x09, exp_9);
 419        set_vector(0x0a, exp_10);
 420        set_vector(0x0b, exp_11);
 421        set_vector(0x0c, exp_12);
 422        set_vector(0x0d, exp_13);
 423        set_vector(0x0e, exp_14);
 424        set_vector(0x0f, exp_15);
 425        set_vector(0x10, exp_16);
 426        set_vector(0x11, exp_17);
 427        set_vector(0x12, exp_18);
 428        set_vector(0x13, exp_19);
 429        set_vector(0x14, exp_20);
 430        set_vector(0x15, exp_21);
 431        set_vector(0x16, exp_22);
 432        set_vector(0x17, exp_23);
 433        set_vector(0x18, exp_24);
 434        set_vector(0x19, exp_25);
 435        set_vector(0x1a, exp_26);
 436        set_vector(0x1b, exp_27);
 437        set_vector(0x1c, exp_28);
 438        set_vector(0x1d, exp_29);
 439        set_vector(0x1e, exp_30);
 440        set_vector(0x1f, exp_31);
 441
 442
 443        /* Setup interrupts */
 444        set_vector(0x20, irq_0);
 445        set_vector(0x21, irq_1);
 446        set_vector(0x23, irq_3);
 447        set_vector(0x24, irq_4);
 448        set_vector(0x25, irq_5);
 449        set_vector(0x26, irq_6);
 450        set_vector(0x27, irq_7);
 451        set_vector(0x28, irq_8);
 452        set_vector(0x29, irq_9);
 453        set_vector(0x2a, irq_10);
 454        set_vector(0x2b, irq_11);
 455        set_vector(0x2c, irq_12);
 456        set_vector(0x2d, irq_13);
 457        set_vector(0x2e, irq_14);
 458        set_vector(0x2f, irq_15);
 459        /* vectors 0x30-0x3f are reserved for irq 16-31 */
 460
 461
 462        /* Mask all interrupts */
 463        outb(0xff, MASTER_PIC + IMR);
 464        outb(0xff, SLAVE_PIC + IMR);
 465
 466        /* Master PIC */
 467        outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
 468        outb(0x20, MASTER_PIC + ICW2);          /* Place master PIC interrupts at INT20 */
 469        outb(IR2, MASTER_PIC + ICW3);           /* ICW3, One slevc PIC is present */
 470        outb(ICW4_PM, MASTER_PIC + ICW4);
 471
 472        for (i=0;i<8;i++) {
 473                outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
 474        }
 475
 476        /* Slave PIC */
 477        outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
 478        outb(0x28, SLAVE_PIC + ICW2);           /* Place slave PIC interrupts at INT28 */
 479        outb(0x02, SLAVE_PIC + ICW3);           /* Slave ID */
 480        outb(ICW4_PM, SLAVE_PIC + ICW4);
 481
 482        for (i=0;i<8;i++) {
 483                outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
 484        }
 485
 486
 487        /* enable cascade interrerupt */
 488        outb(0xfb, MASTER_PIC + IMR);
 489        outb(0xff, SLAVE_PIC + IMR);
 490
 491        /* It is now safe to enable interrupts */
 492        enable_interrupts();
 493
 494        return 0;
 495}
 496
 497void enable_interrupts(void)
 498{
 499        asm("sti\n");
 500}
 501
 502int disable_interrupts(void)
 503{
 504        long flags;
 505
 506        asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
 507
 508        return (flags&0x200); /* IE flags is bit 9 */
 509}
 510
 511
 512#ifdef CONFIG_SYS_RESET_GENERIC
 513
 514void __attribute__ ((regparm(0))) generate_gpf(void);
 515asm(".globl generate_gpf\n"
 516    "generate_gpf:\n"
 517    "ljmp   $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
 518                                    * exist */
 519void reset_cpu(ulong addr)
 520{
 521        set_vector(13, generate_gpf);  /* general protection fault handler */
 522        set_vector(8, generate_gpf);   /* double fault handler */
 523        generate_gpf();                /* start the show */
 524}
 525#endif
 526