LXR uboot/cpu/mpc85xx/cpu

   1/*
   2 * Copyright 2007 Freescale Semiconductor.
   3 *
   4 * (C) Copyright 2003 Motorola Inc.
   5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6 *
   7 * (C) Copyright 2000
   8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29#include <common.h>
  30#include <watchdog.h>
  31#include <asm/processor.h>
  32#include <ioports.h>
  33#include <asm/io.h>
  34#include <asm/mmu.h>
  35#include <asm/fsl_law.h>
  36#include "mp.h"
  37
  38DECLARE_GLOBAL_DATA_PTR;
  39
  40#ifdef CONFIG_MPC8536
  41extern void fsl_serdes_init(void);
  42#endif
  43
  44#ifdef CONFIG_QE
  45extern qe_iop_conf_t qe_iop_conf_tab[];
  46extern void qe_config_iopin(u8 port, u8 pin, int dir,
  47                                int open_drain, int assign);
  48extern void qe_init(uint qe_base);
  49extern void qe_reset(void);
  50
  51static void config_qe_ioports(void)
  52{
  53        u8      port, pin;
  54        int     dir, open_drain, assign;
  55        int     i;
  56
  57        for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  58                port            = qe_iop_conf_tab[i].port;
  59                pin             = qe_iop_conf_tab[i].pin;
  60                dir             = qe_iop_conf_tab[i].dir;
  61                open_drain      = qe_iop_conf_tab[i].open_drain;
  62                assign          = qe_iop_conf_tab[i].assign;
  63                qe_config_iopin(port, pin, dir, open_drain, assign);
  64        }
  65}
  66#endif
  67
  68#ifdef CONFIG_CPM2
  69void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  70{
  71        int portnum;
  72
  73        for (portnum = 0; portnum < 4; portnum++) {
  74                uint pmsk = 0,
  75                     ppar = 0,
  76                     psor = 0,
  77                     pdir = 0,
  78                     podr = 0,
  79                     pdat = 0;
  80                iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  81                iop_conf_t *eiopc = iopc + 32;
  82                uint msk = 1;
  83
  84                /*
  85                 * NOTE:
  86                 * index 0 refers to pin 31,
  87                 * index 31 refers to pin 0
  88                 */
  89                while (iopc < eiopc) {
  90                        if (iopc->conf) {
  91                                pmsk |= msk;
  92                                if (iopc->ppar)
  93                                        ppar |= msk;
  94                                if (iopc->psor)
  95                                        psor |= msk;
  96                                if (iopc->pdir)
  97                                        pdir |= msk;
  98                                if (iopc->podr)
  99                                        podr |= msk;
 100                                if (iopc->pdat)
 101                                        pdat |= msk;
 102                        }
 103
 104                        msk <<= 1;
 105                        iopc++;
 106                }
 107
 108                if (pmsk != 0) {
 109                        volatile ioport_t *iop = ioport_addr (cpm, portnum);
 110                        uint tpmsk = ~pmsk;
 111
 112                        /*
 113                         * the (somewhat confused) paragraph at the
 114                         * bottom of page 35-5 warns that there might
 115                         * be "unknown behaviour" when programming
 116                         * PSORx and PDIRx, if PPARx = 1, so I
 117                         * decided this meant I had to disable the
 118                         * dedicated function first, and enable it
 119                         * last.
 120                         */
 121                        iop->ppar &= tpmsk;
 122                        iop->psor = (iop->psor & tpmsk) | psor;
 123                        iop->podr = (iop->podr & tpmsk) | podr;
 124                        iop->pdat = (iop->pdat & tpmsk) | pdat;
 125                        iop->pdir = (iop->pdir & tpmsk) | pdir;
 126                        iop->ppar |= ppar;
 127                }
 128        }
 129}
 130#endif
 131
 132/* We run cpu_init_early_f in AS = 1 */
 133void cpu_init_early_f(void)
 134{
 135        /* Pointer is writable since we allocated a register for it */
 136        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 137
 138        /* Clear initial global data */
 139        memset ((void *) gd, 0, sizeof (gd_t));
 140
 141        set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 142                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 143                1, 0, BOOKE_PAGESZ_4K, 0);
 144
 145        /* set up CCSR if we want it moved */
 146#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 147        {
 148                u32 temp;
 149                volatile u32 *ccsr_virt =
 150                        (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
 151
 152                set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
 153                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 154                        1, 1, BOOKE_PAGESZ_4K, 0);
 155
 156                temp = in_be32(ccsr_virt);
 157                out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
 158                temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
 159        }
 160#endif
 161
 162        init_laws();
 163        invalidate_tlb(0);
 164        init_tlbs();
 165}
 166
 167/*
 168 * Breathe some life into the CPU...
 169 *
 170 * Set up the memory map
 171 * initialize a bunch of registers
 172 */
 173
 174void cpu_init_f (void)
 175{
 176        volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 177        extern void m8560_cpm_reset (void);
 178#ifdef CONFIG_MPC8548
 179        ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 180        uint svr = get_svr();
 181
 182        /*
 183         * CPU2 errata workaround: A core hang possible while executing
 184         * a msync instruction and a snoopable transaction from an I/O
 185         * master tagged to make quick forward progress is present.
 186         * Fixed in silicon rev 2.1.
 187         */
 188        if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 189                out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 190#endif
 191
 192        disable_tlb(14);
 193        disable_tlb(15);
 194
 195#ifdef CONFIG_CPM2
 196        config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 197#endif
 198
 199        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 200         * addresses - these have to be modified later when FLASH size
 201         * has been determined
 202         */
 203#if defined(CONFIG_SYS_OR0_REMAP)
 204        memctl->or0 = CONFIG_SYS_OR0_REMAP;
 205#endif
 206#if defined(CONFIG_SYS_OR1_REMAP)
 207        memctl->or1 = CONFIG_SYS_OR1_REMAP;
 208#endif
 209
 210        /* now restrict to preliminary range */
 211        /* if cs1 is already set via debugger, leave cs0/cs1 alone */
 212        if (! memctl->br1 & 1) {
 213#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
 214                memctl->br0 = CONFIG_SYS_BR0_PRELIM;
 215                memctl->or0 = CONFIG_SYS_OR0_PRELIM;
 216#endif
 217
 218#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 219                memctl->or1 = CONFIG_SYS_OR1_PRELIM;
 220                memctl->br1 = CONFIG_SYS_BR1_PRELIM;
 221#endif
 222        }
 223
 224#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 225        memctl->or2 = CONFIG_SYS_OR2_PRELIM;
 226        memctl->br2 = CONFIG_SYS_BR2_PRELIM;
 227#endif
 228
 229#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 230        memctl->or3 = CONFIG_SYS_OR3_PRELIM;
 231        memctl->br3 = CONFIG_SYS_BR3_PRELIM;
 232#endif
 233
 234#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 235        memctl->or4 = CONFIG_SYS_OR4_PRELIM;
 236        memctl->br4 = CONFIG_SYS_BR4_PRELIM;
 237#endif
 238
 239#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 240        memctl->or5 = CONFIG_SYS_OR5_PRELIM;
 241        memctl->br5 = CONFIG_SYS_BR5_PRELIM;
 242#endif
 243
 244#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 245        memctl->or6 = CONFIG_SYS_OR6_PRELIM;
 246        memctl->br6 = CONFIG_SYS_BR6_PRELIM;
 247#endif
 248
 249#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 250        memctl->or7 = CONFIG_SYS_OR7_PRELIM;
 251        memctl->br7 = CONFIG_SYS_BR7_PRELIM;
 252#endif
 253
 254#if defined(CONFIG_CPM2)
 255        m8560_cpm_reset();
 256#endif
 257#ifdef CONFIG_QE
 258        /* Config QE ioports */
 259        config_qe_ioports();
 260#endif
 261#if defined(CONFIG_MPC8536)
 262        fsl_serdes_init();
 263#endif
 264
 265}
 266
 267
 268/*
 269 * Initialize L2 as cache.
 270 *
 271 * The newer 8548, etc, parts have twice as much cache, but
 272 * use the same bit-encoding as the older 8555, etc, parts.
 273 *
 274 */
 275
 276int cpu_init_r(void)
 277{
 278        puts ("L2:    ");
 279
 280#if defined(CONFIG_L2_CACHE)
 281        volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 282        volatile uint cache_ctl;
 283        uint svr, ver;
 284        uint l2srbar;
 285        u32 l2siz_field;
 286
 287        svr = get_svr();
 288        ver = SVR_SOC_VER(svr);
 289
 290        asm("msync;isync");
 291        cache_ctl = l2cache->l2ctl;
 292        l2siz_field = (cache_ctl >> 28) & 0x3;
 293
 294        switch (l2siz_field) {
 295        case 0x0:
 296                printf(" unknown size (0x%08x)\n", cache_ctl);
 297                return -1;
 298                break;
 299        case 0x1:
 300                if (ver == SVR_8540 || ver == SVR_8560   ||
 301                    ver == SVR_8541 || ver == SVR_8541_E ||
 302                    ver == SVR_8555 || ver == SVR_8555_E) {
 303                        puts("128 KB ");
 304                        /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 305                        cache_ctl = 0xc4000000;
 306                } else {
 307                        puts("256 KB ");
 308                        cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 309                }
 310                break;
 311        case 0x2:
 312                if (ver == SVR_8540 || ver == SVR_8560   ||
 313                    ver == SVR_8541 || ver == SVR_8541_E ||
 314                    ver == SVR_8555 || ver == SVR_8555_E) {
 315                        puts("256 KB ");
 316                        /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 317                        cache_ctl = 0xc8000000;
 318                } else {
 319                        puts ("512 KB ");
 320                        /* set L2E=1, L2I=1, & L2SRAM=0 */
 321                        cache_ctl = 0xc0000000;
 322                }
 323                break;
 324        case 0x3:
 325                puts("1024 KB ");
 326                /* set L2E=1, L2I=1, & L2SRAM=0 */
 327                cache_ctl = 0xc0000000;
 328                break;
 329        }
 330
 331        if (l2cache->l2ctl & 0x80000000) {
 332                puts("already enabled");
 333                l2srbar = l2cache->l2srbar0;
 334#ifdef CONFIG_SYS_INIT_L2_ADDR
 335                if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 336                        l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 337                        l2cache->l2srbar0 = l2srbar;
 338                        printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 339                }
 340#endif /* CONFIG_SYS_INIT_L2_ADDR */
 341                puts("\n");
 342        } else {
 343                asm("msync;isync");
 344                l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 345                asm("msync;isync");
 346                puts("enabled\n");
 347        }
 348#else
 349        puts("disabled\n");
 350#endif
 351#ifdef CONFIG_QE
 352        uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 353        qe_init(qe_base);
 354        qe_reset();
 355#endif
 356
 357#if defined(CONFIG_MP)
 358        setup_mp();
 359#endif
 360        return 0;
 361}
 362