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72#include <common.h>
73#include <command.h>
74#if !defined(CONFIG_440)
75#include <asm/4xx_pci.h>
76#endif
77#include <asm/processor.h>
78#include <pci.h>
79
80#ifdef CONFIG_PCI
81
82DECLARE_GLOBAL_DATA_PTR;
83
84
85
86
87
88int __pci_pre_init(struct pci_controller *hose)
89{
90 return 1;
91}
92int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
93
94#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
95
96#if defined(CONFIG_PMC405)
97ushort pmc405_pci_subsys_deviceid(void);
98#endif
99
100
101
102
103
104
105void pci_405gp_init(struct pci_controller *hose)
106{
107 int i, reg_num = 0;
108 bd_t *bd = gd->bd;
109
110 unsigned short temp_short;
111 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
112#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
113 char *ptmla_str, *ptmms_str;
114#endif
115 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
116 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
117#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
118 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
119 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
120 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
121 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
122#else
123 unsigned long pmmla[3] = {0x80000000, 0,0};
124 unsigned long pmmma[3] = {0xC0000001, 0,0};
125 unsigned long pmmpcila[3] = {0x80000000, 0,0};
126 unsigned long pmmpciha[3] = {0x00000000, 0,0};
127#endif
128#ifdef CONFIG_PCI_PNP
129#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
130 char *s;
131#endif
132#endif
133
134#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
135 ptmla_str = getenv("ptm1la");
136 ptmms_str = getenv("ptm1ms");
137 if(NULL != ptmla_str && NULL != ptmms_str ) {
138 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
139 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
140 }
141
142 ptmla_str = getenv("ptm2la");
143 ptmms_str = getenv("ptm2ms");
144 if(NULL != ptmla_str && NULL != ptmms_str ) {
145 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
146 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
147 }
148#endif
149
150
151
152
153 hose->first_busno = 0;
154 hose->last_busno = 0xff;
155
156
157 pci_set_region(hose->regions + reg_num++,
158 MIN_PCI_PCI_IOADDR,
159 MIN_PLB_PCI_IOADDR,
160 0x10000,
161 PCI_REGION_IO);
162
163
164 pci_set_region(hose->regions + reg_num++,
165 0x00800000,
166 0xe8800000,
167 0x03800000,
168 PCI_REGION_IO);
169
170 reg_num = 2;
171
172
173 for (i=0; i<2; i++)
174 if (ptmms[i] & 1)
175 {
176 if (!i) hose->pci_fb = hose->regions + reg_num;
177
178 pci_set_region(hose->regions + reg_num++,
179 ptmpcila[i], ptmla[i],
180 ~(ptmms[i] & 0xfffff000) + 1,
181 PCI_REGION_MEM |
182 PCI_REGION_MEMORY);
183 }
184
185
186 for (i=0; i<3; i++)
187 if (pmmma[i] & 1)
188 {
189 pci_set_region(hose->regions + reg_num++,
190 pmmpcila[i], pmmla[i],
191 ~(pmmma[i] & 0xfffff000) + 1,
192 PCI_REGION_MEM);
193 }
194
195 hose->region_count = reg_num;
196
197 pci_setup_indirect(hose,
198 PCICFGADR,
199 PCICFGDATA);
200
201 if (hose->pci_fb)
202 pciauto_region_init(hose->pci_fb);
203
204
205 if (pci_pre_init (hose) == 0) {
206 printf("PCI: Board-specific initialization failed.\n");
207 printf("PCI: Configuration aborted.\n");
208 return;
209 }
210
211 pci_register_hose(hose);
212
213
214
215
216
217
218
219 out32r(PMM0MA, (pmmma[0]&~0x1));
220 out32r(PMM0LA, pmmla[0]);
221 out32r(PMM0PCILA, pmmpcila[0]);
222 out32r(PMM0PCIHA, pmmpciha[0]);
223 out32r(PMM0MA, pmmma[0]);
224
225
226
227
228 out32r(PMM1MA, (pmmma[1]&~0x1));
229 out32r(PMM1LA, pmmla[1]);
230 out32r(PMM1PCILA, pmmpcila[1]);
231 out32r(PMM1PCIHA, pmmpciha[1]);
232 out32r(PMM1MA, pmmma[1]);
233
234
235
236
237 out32r(PMM2MA, (pmmma[2]&~0x1));
238 out32r(PMM2LA, pmmla[2]);
239 out32r(PMM2PCILA, pmmpcila[2]);
240 out32r(PMM2PCIHA, pmmpciha[2]);
241 out32r(PMM2MA, pmmma[2]);
242
243
244
245
246
247 out32r(PTM1LA, ptmla[0]);
248 out32r(PTM1MS, ptmms[0]);
249 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
250
251
252
253
254 out32r(PTM2LA, ptmla[1]);
255 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
256
257 if (ptmms[1] == 0)
258 {
259 out32r(PTM2MS, 0x00000001);
260 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
261 out32r(PTM2MS, 0x00000000);
262 }
263 else
264 {
265 out32r(PTM2MS, ptmms[1]);
266 }
267
268
269
270
271 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
272#ifdef CONFIG_CPCI405
273 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
274 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
275 else
276 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
277#else
278 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
279#endif
280
281
282
283
284#ifdef CONFIG_SYS_PCI_CLASSCODE
285 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
286#endif
287
288
289
290
291 if (bd->bi_pci_busfreq >= 66000000) {
292 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
293 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
294 }
295
296#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
297#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
298 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
299 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
300#endif
301 {
302
303
304
305
306
307 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
308 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
309 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
310 }
311#endif
312
313#if defined(CONFIG_405EP)
314 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014);
315#endif
316
317
318
319
320 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
321 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
322
323#ifdef CONFIG_PCI_PNP
324
325
326
327#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
328 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
329 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
330#endif
331 {
332#ifdef CONFIG_PCI_SCAN_SHOW
333 printf("PCI: Bus Dev VenId DevId Class Int\n");
334#endif
335 hose->last_busno = pci_hose_scan(hose);
336 }
337#endif
338
339}
340
341
342
343
344
345
346
347
348
349void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
350 struct pci_config_table *entry)
351{
352#ifdef DEBUG
353 printf("405gp_setup_bridge\n");
354#endif
355}
356
357
358
359
360
361void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
362{
363 unsigned char int_line = 0xff;
364
365
366
367
368 switch (PCI_DEV(dev) & 0x03)
369 {
370 case 0:
371 int_line = 27 + 2;
372 break;
373 case 1:
374 int_line = 27 + 3;
375 break;
376 case 2:
377 int_line = 27 + 0;
378 break;
379 case 3:
380 int_line = 27 + 1;
381 break;
382 }
383
384 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
385}
386
387void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
388 struct pci_config_table *entry)
389{
390 unsigned int cmdstat = 0;
391
392 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
393
394
395 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
396 cmdstat |= PCI_COMMAND_IO;
397 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
398}
399
400#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
401
402
403
404
405
406static struct pci_config_table pci_405gp_config_table[] = {
407
408#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
409 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
410 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
411#endif
412 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
413 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
414
415 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
416 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
417
418 { }
419};
420
421static struct pci_controller hose = {
422 fixup_irq: pci_405gp_fixup_irq,
423 config_table: pci_405gp_config_table,
424};
425
426void pci_init_board(void)
427{
428
429 hose.fixup_irq = pci_405gp_fixup_irq;
430 hose.config_table = pci_405gp_config_table;
431 pci_405gp_init(&hose);
432}
433
434#endif
435
436#endif
437
438
439
440
441#if defined(CONFIG_440)
442
443static struct pci_controller ppc440_hose = {0};
444
445
446int pci_440_init (struct pci_controller *hose)
447{
448 int reg_num = 0;
449
450#ifndef CONFIG_DISABLE_PISE_TEST
451
452
453
454
455#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
456 unsigned long strap;
457
458 mfsdr(sdr_sdstp1,strap);
459 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
460 printf("PCI: SDR0_STRP1[PISE] not set.\n");
461 printf("PCI: Configuration aborted.\n");
462 return -1;
463 }
464#elif defined(CONFIG_440GP)
465 unsigned long strap;
466
467 strap = mfdcr(cpc0_strp1);
468 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
469 printf("PCI: CPC0_STRP1[PISE] not set.\n");
470 printf("PCI: Configuration aborted.\n");
471 return -1;
472 }
473#endif
474#endif
475
476
477
478
479 hose->first_busno = 0;
480 hose->last_busno = 0;
481
482
483 pci_set_region(hose->regions + reg_num++,
484 0x00000000,
485 PCIX0_IOBASE,
486 0x10000,
487 PCI_REGION_IO);
488
489
490 pci_set_region(hose->regions + reg_num++,
491 CONFIG_SYS_PCI_TARGBASE,
492 CONFIG_SYS_PCI_MEMBASE,
493#ifdef CONFIG_SYS_PCI_MEMSIZE
494 CONFIG_SYS_PCI_MEMSIZE,
495#else
496 0x10000000,
497#endif
498 PCI_REGION_MEM );
499
500#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
501 defined(CONFIG_PCI_SYS_MEM_SIZE)
502
503 pci_set_region(hose->regions + reg_num++,
504 CONFIG_PCI_SYS_MEM_BUS,
505 CONFIG_PCI_SYS_MEM_PHYS,
506 CONFIG_PCI_SYS_MEM_SIZE,
507 PCI_REGION_MEM | PCI_REGION_MEMORY );
508#endif
509
510 hose->region_count = reg_num;
511
512 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
513
514
515 if (pci_pre_init (hose) == 0) {
516 printf("PCI: Board-specific initialization failed.\n");
517 printf("PCI: Configuration aborted.\n");
518 return -1;
519 }
520
521 pci_register_hose( hose );
522
523
524
525
526#if defined(CONFIG_SYS_PCI_TARGET_INIT)
527 pci_target_init(hose);
528#else
529 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
530 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
531 out16r( PCIX0_CLS, 0x00060000 );
532#endif
533
534#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
535 defined(CONFIG_460EX) || defined(CONFIG_460GT)
536 out32r( PCIX0_BRDGOPT1, 0x04000060 );
537 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 );
538#elif defined(PCIX0_BRDGOPT1)
539 out32r( PCIX0_BRDGOPT1, 0x10000060 );
540 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 );
541#endif
542
543
544
545
546
547#if defined(CONFIG_SYS_PCI_MASTER_INIT)
548 pci_master_init(hose);
549#else
550 out32r( PCIX0_POM0SA, 0 );
551 out32r( PCIX0_POM1SA, 0 );
552 out32r( PCIX0_POM2SA, 0 );
553#if defined(CONFIG_440SPE) || \
554 defined(CONFIG_460EX) || defined(CONFIG_460GT)
555 out32r( PCIX0_POM0LAL, 0x10000000 );
556 out32r( PCIX0_POM0LAH, 0x0000000c );
557#else
558 out32r( PCIX0_POM0LAL, 0x00000000 );
559 out32r( PCIX0_POM0LAH, 0x00000003 );
560#endif
561 out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
562 out32r( PCIX0_POM0PCIAH, 0x00000000 );
563 out32r( PCIX0_POM0SA, 0xf0000001 );
564 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
565#endif
566
567
568
569
570
571
572
573 if (is_pci_host(hose)) {
574#ifdef CONFIG_PCI_SCAN_SHOW
575 printf("PCI: Bus Dev VenId DevId Class Int\n");
576#endif
577#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
578 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
579 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
580#endif
581 hose->last_busno = pci_hose_scan(hose);
582 }
583 return hose->last_busno;
584}
585
586void pci_init_board(void)
587{
588 int busno;
589
590 busno = pci_440_init (&ppc440_hose);
591#if defined(CONFIG_440SPE) || \
592 defined(CONFIG_460EX) || defined(CONFIG_460GT)
593 pcie_setup_hoses(busno + 1);
594#endif
595}
596
597#endif
598
599#if defined(CONFIG_405EX)
600void pci_init_board(void)
601{
602#ifdef CONFIG_PCI_SCAN_SHOW
603 printf("PCI: Bus Dev VenId DevId Class Int\n");
604#endif
605 pcie_setup_hoses(0);
606}
607#endif
608
609#endif
610