uboot/drivers/net/tsi108_eth.c
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   1/***********************************************************************
   2 *
   3 * Copyright (c) 2005 Freescale Semiconductor, Inc.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 *
  23 * Description:
  24 *   Ethernet interface for Tundra TSI108 bridge chip
  25 *
  26 ***********************************************************************/
  27
  28#include <config.h>
  29
  30#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
  31#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
  32#endif
  33
  34#include <common.h>
  35#include <malloc.h>
  36#include <net.h>
  37#include <netdev.h>
  38#include <asm/cache.h>
  39
  40#ifdef DEBUG
  41#define TSI108_ETH_DEBUG 7
  42#else
  43#define TSI108_ETH_DEBUG 0
  44#endif
  45
  46#if TSI108_ETH_DEBUG > 0
  47#define debug_lev(lev, fmt, args...) \
  48if (lev <= TSI108_ETH_DEBUG) \
  49printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
  50#else
  51#define debug_lev(lev, fmt, args...) do{}while(0)
  52#endif
  53
  54#define RX_PRINT_ERRORS
  55#define TX_PRINT_ERRORS
  56
  57#define ETH_BASE        (CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
  58
  59#define ETH_PORT_OFFSET 0x400
  60
  61#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
  62
  63#define reg_MAC_CONFIG_1(base)          __REG32(base, 0x00000000)
  64#define MAC_CONFIG_1_TX_ENABLE          (0x00000001)
  65#define MAC_CONFIG_1_SYNC_TX_ENABLE     (0x00000002)
  66#define MAC_CONFIG_1_RX_ENABLE          (0x00000004)
  67#define MAC_CONFIG_1_SYNC_RX_ENABLE     (0x00000008)
  68#define MAC_CONFIG_1_TX_FLOW_CONTROL    (0x00000010)
  69#define MAC_CONFIG_1_RX_FLOW_CONTROL    (0x00000020)
  70#define MAC_CONFIG_1_LOOP_BACK          (0x00000100)
  71#define MAC_CONFIG_1_RESET_TX_FUNCTION  (0x00010000)
  72#define MAC_CONFIG_1_RESET_RX_FUNCTION  (0x00020000)
  73#define MAC_CONFIG_1_RESET_TX_MAC       (0x00040000)
  74#define MAC_CONFIG_1_RESET_RX_MAC       (0x00080000)
  75#define MAC_CONFIG_1_SIM_RESET          (0x40000000)
  76#define MAC_CONFIG_1_SOFT_RESET         (0x80000000)
  77
  78#define reg_MAC_CONFIG_2(base)          __REG32(base, 0x00000004)
  79#define MAC_CONFIG_2_FULL_DUPLEX        (0x00000001)
  80#define MAC_CONFIG_2_CRC_ENABLE         (0x00000002)
  81#define MAC_CONFIG_2_PAD_CRC            (0x00000004)
  82#define MAC_CONFIG_2_LENGTH_CHECK       (0x00000010)
  83#define MAC_CONFIG_2_HUGE_FRAME         (0x00000020)
  84#define MAC_CONFIG_2_INTERFACE_MODE(val)        (((val) & 0x3) << 8)
  85#define MAC_CONFIG_2_PREAMBLE_LENGTH(val)       (((val) & 0xf) << 12)
  86#define INTERFACE_MODE_NIBBLE           1       /* 10/100 Mb/s MII) */
  87#define INTERFACE_MODE_BYTE             2       /* 1000 Mb/s GMII/TBI */
  88
  89#define reg_MAXIMUM_FRAME_LENGTH(base)          __REG32(base, 0x00000010)
  90
  91#define reg_MII_MGMT_CONFIG(base)               __REG32(base, 0x00000020)
  92#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val)  ((val) & 0x7)
  93#define MII_MGMT_CONFIG_NO_PREAMBLE             (0x00000010)
  94#define MII_MGMT_CONFIG_SCAN_INCREMENT          (0x00000020)
  95#define MII_MGMT_CONFIG_RESET_MGMT              (0x80000000)
  96
  97#define reg_MII_MGMT_COMMAND(base)              __REG32(base, 0x00000024)
  98#define MII_MGMT_COMMAND_READ_CYCLE             (0x00000001)
  99#define MII_MGMT_COMMAND_SCAN_CYCLE             (0x00000002)
 100
 101#define reg_MII_MGMT_ADDRESS(base)              __REG32(base, 0x00000028)
 102#define reg_MII_MGMT_CONTROL(base)              __REG32(base, 0x0000002c)
 103#define reg_MII_MGMT_STATUS(base)               __REG32(base, 0x00000030)
 104
 105#define reg_MII_MGMT_INDICATORS(base)           __REG32(base, 0x00000034)
 106#define MII_MGMT_INDICATORS_BUSY                (0x00000001)
 107#define MII_MGMT_INDICATORS_SCAN                (0x00000002)
 108#define MII_MGMT_INDICATORS_NOT_VALID           (0x00000004)
 109
 110#define reg_INTERFACE_STATUS(base)              __REG32(base, 0x0000003c)
 111#define INTERFACE_STATUS_LINK_FAIL              (0x00000008)
 112#define INTERFACE_STATUS_EXCESS_DEFER           (0x00000200)
 113
 114#define reg_STATION_ADDRESS_1(base)             __REG32(base, 0x00000040)
 115#define reg_STATION_ADDRESS_2(base)             __REG32(base, 0x00000044)
 116
 117#define reg_PORT_CONTROL(base)                  __REG32(base, 0x00000200)
 118#define PORT_CONTROL_PRI                (0x00000001)
 119#define PORT_CONTROL_BPT                (0x00010000)
 120#define PORT_CONTROL_SPD                (0x00040000)
 121#define PORT_CONTROL_RBC                (0x00080000)
 122#define PORT_CONTROL_PRB                (0x00200000)
 123#define PORT_CONTROL_DIS                (0x00400000)
 124#define PORT_CONTROL_TBI                (0x00800000)
 125#define PORT_CONTROL_STE                (0x10000000)
 126#define PORT_CONTROL_ZOR                (0x20000000)
 127#define PORT_CONTROL_CLR                (0x40000000)
 128#define PORT_CONTROL_SRT                (0x80000000)
 129
 130#define reg_TX_CONFIG(base)             __REG32(base, 0x00000220)
 131#define TX_CONFIG_START_Q               (0x00000003)
 132#define TX_CONFIG_EHP                   (0x00400000)
 133#define TX_CONFIG_CHP                   (0x00800000)
 134#define TX_CONFIG_RST                   (0x80000000)
 135
 136#define reg_TX_CONTROL(base)            __REG32(base, 0x00000224)
 137#define TX_CONTROL_GO                   (0x00008000)
 138#define TX_CONTROL_MP                   (0x01000000)
 139#define TX_CONTROL_EAI                  (0x20000000)
 140#define TX_CONTROL_ABT                  (0x40000000)
 141#define TX_CONTROL_EII                  (0x80000000)
 142
 143#define reg_TX_STATUS(base)             __REG32(base, 0x00000228)
 144#define TX_STATUS_QUEUE_USABLE          (0x0000000f)
 145#define TX_STATUS_CURR_Q                (0x00000300)
 146#define TX_STATUS_ACT                   (0x00008000)
 147#define TX_STATUS_QUEUE_IDLE            (0x000f0000)
 148#define TX_STATUS_EOQ_PENDING           (0x0f000000)
 149
 150#define reg_TX_EXTENDED_STATUS(base)            __REG32(base, 0x0000022c)
 151#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION               (0x0000000f)
 152#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION               (0x00000f00)
 153#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION       (0x000f0000)
 154#define TX_EXTENDED_STATUS_ERROR_FLAG                           (0x0f000000)
 155
 156#define reg_TX_THRESHOLDS(base)                 __REG32(base, 0x00000230)
 157
 158#define reg_TX_DIAGNOSTIC_ADDR(base)           __REG32(base, 0x00000270)
 159#define TX_DIAGNOSTIC_ADDR_INDEX                (0x0000007f)
 160#define TX_DIAGNOSTIC_ADDR_DFR                  (0x40000000)
 161#define TX_DIAGNOSTIC_ADDR_AI                   (0x80000000)
 162
 163#define reg_TX_DIAGNOSTIC_DATA(base)            __REG32(base, 0x00000274)
 164
 165#define reg_TX_ERROR_STATUS(base)               __REG32(base, 0x00000278)
 166#define TX_ERROR_STATUS                         (0x00000278)
 167#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE  (0x0000000f)
 168#define TX_ERROR_STATUS_TEA_ON_QUEUE_0          (0x00000010)
 169#define TX_ERROR_STATUS_RER_ON_QUEUE_0          (0x00000020)
 170#define TX_ERROR_STATUS_TER_ON_QUEUE_0          (0x00000040)
 171#define TX_ERROR_STATUS_DER_ON_QUEUE_0          (0x00000080)
 172#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE  (0x00000f00)
 173#define TX_ERROR_STATUS_TEA_ON_QUEUE_1          (0x00001000)
 174#define TX_ERROR_STATUS_RER_ON_QUEUE_1          (0x00002000)
 175#define TX_ERROR_STATUS_TER_ON_QUEUE_1          (0x00004000)
 176#define TX_ERROR_STATUS_DER_ON_QUEUE_1          (0x00008000)
 177#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE  (0x000f0000)
 178#define TX_ERROR_STATUS_TEA_ON_QUEUE_2          (0x00100000)
 179#define TX_ERROR_STATUS_RER_ON_QUEUE_2          (0x00200000)
 180#define TX_ERROR_STATUS_TER_ON_QUEUE_2          (0x00400000)
 181#define TX_ERROR_STATUS_DER_ON_QUEUE_2          (0x00800000)
 182#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE  (0x0f000000)
 183#define TX_ERROR_STATUS_TEA_ON_QUEUE_3          (0x10000000)
 184#define TX_ERROR_STATUS_RER_ON_QUEUE_3          (0x20000000)
 185#define TX_ERROR_STATUS_TER_ON_QUEUE_3          (0x40000000)
 186#define TX_ERROR_STATUS_DER_ON_QUEUE_3          (0x80000000)
 187
 188#define reg_TX_QUEUE_0_CONFIG(base)             __REG32(base, 0x00000280)
 189#define TX_QUEUE_0_CONFIG_OCN_PORT              (0x0000003f)
 190#define TX_QUEUE_0_CONFIG_BSWP                  (0x00000400)
 191#define TX_QUEUE_0_CONFIG_WSWP                  (0x00000800)
 192#define TX_QUEUE_0_CONFIG_AM                    (0x00004000)
 193#define TX_QUEUE_0_CONFIG_GVI                   (0x00008000)
 194#define TX_QUEUE_0_CONFIG_EEI                   (0x00010000)
 195#define TX_QUEUE_0_CONFIG_ELI                   (0x00020000)
 196#define TX_QUEUE_0_CONFIG_ENI                   (0x00040000)
 197#define TX_QUEUE_0_CONFIG_ESI                   (0x00080000)
 198#define TX_QUEUE_0_CONFIG_EDI                   (0x00100000)
 199
 200#define reg_TX_QUEUE_0_BUF_CONFIG(base)         __REG32(base, 0x00000284)
 201#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT          (0x0000003f)
 202#define TX_QUEUE_0_BUF_CONFIG_BURST             (0x00000300)
 203#define TX_QUEUE_0_BUF_CONFIG_BSWP              (0x00000400)
 204#define TX_QUEUE_0_BUF_CONFIG_WSWP              (0x00000800)
 205
 206#define OCN_PORT_HLP                    0       /* HLP Interface */
 207#define OCN_PORT_PCI_X                  1       /* PCI-X Interface */
 208#define OCN_PORT_PROCESSOR_MASTER       2       /* Processor Interface (master) */
 209#define OCN_PORT_PROCESSOR_SLAVE        3       /* Processor Interface (slave) */
 210#define OCN_PORT_MEMORY                 4       /* Memory Controller */
 211#define OCN_PORT_DMA                    5       /* DMA Controller */
 212#define OCN_PORT_ETHERNET               6       /* Ethernet Controller */
 213#define OCN_PORT_PRINT                  7       /* Print Engine Interface */
 214
 215#define reg_TX_QUEUE_0_PTR_LOW(base)            __REG32(base, 0x00000288)
 216
 217#define reg_TX_QUEUE_0_PTR_HIGH(base)           __REG32(base, 0x0000028c)
 218#define TX_QUEUE_0_PTR_HIGH_VALID               (0x80000000)
 219
 220#define reg_RX_CONFIG(base)                     __REG32(base, 0x00000320)
 221#define RX_CONFIG_DEF_Q                         (0x00000003)
 222#define RX_CONFIG_EMF                           (0x00000100)
 223#define RX_CONFIG_EUF                           (0x00000200)
 224#define RX_CONFIG_BFE                           (0x00000400)
 225#define RX_CONFIG_MFE                           (0x00000800)
 226#define RX_CONFIG_UFE                           (0x00001000)
 227#define RX_CONFIG_SE                            (0x00002000)
 228#define RX_CONFIG_ABF                           (0x00200000)
 229#define RX_CONFIG_APE                           (0x00400000)
 230#define RX_CONFIG_CHP                           (0x00800000)
 231#define RX_CONFIG_RST                           (0x80000000)
 232
 233#define reg_RX_CONTROL(base)                    __REG32(base, 0x00000324)
 234#define GE_E0_RX_CONTROL_QUEUE_ENABLES          (0x0000000f)
 235#define GE_E0_RX_CONTROL_GO                     (0x00008000)
 236#define GE_E0_RX_CONTROL_EAI                    (0x20000000)
 237#define GE_E0_RX_CONTROL_ABT                    (0x40000000)
 238#define GE_E0_RX_CONTROL_EII                    (0x80000000)
 239
 240#define reg_RX_EXTENDED_STATUS(base)            __REG32(base, 0x0000032c)
 241#define RX_EXTENDED_STATUS                      (0x0000032c)
 242#define RX_EXTENDED_STATUS_EOQ                  (0x0000000f)
 243#define RX_EXTENDED_STATUS_EOQ_0                (0x00000001)
 244#define RX_EXTENDED_STATUS_EOF                  (0x00000f00)
 245#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION       (0x000f0000)
 246#define RX_EXTENDED_STATUS_ERROR_FLAG                           (0x0f000000)
 247
 248#define reg_RX_THRESHOLDS(base)                 __REG32(base, 0x00000330)
 249
 250#define reg_RX_DIAGNOSTIC_ADDR(base)            __REG32(base, 0x00000370)
 251#define RX_DIAGNOSTIC_ADDR_INDEX                (0x0000007f)
 252#define RX_DIAGNOSTIC_ADDR_DFR                  (0x40000000)
 253#define RX_DIAGNOSTIC_ADDR_AI                   (0x80000000)
 254
 255#define reg_RX_DIAGNOSTIC_DATA(base)            __REG32(base, 0x00000374)
 256
 257#define reg_RX_QUEUE_0_CONFIG(base)             __REG32(base, 0x00000380)
 258#define RX_QUEUE_0_CONFIG_OCN_PORT              (0x0000003f)
 259#define RX_QUEUE_0_CONFIG_BSWP                  (0x00000400)
 260#define RX_QUEUE_0_CONFIG_WSWP                  (0x00000800)
 261#define RX_QUEUE_0_CONFIG_AM                    (0x00004000)
 262#define RX_QUEUE_0_CONFIG_EEI                   (0x00010000)
 263#define RX_QUEUE_0_CONFIG_ELI                   (0x00020000)
 264#define RX_QUEUE_0_CONFIG_ENI                   (0x00040000)
 265#define RX_QUEUE_0_CONFIG_ESI                   (0x00080000)
 266#define RX_QUEUE_0_CONFIG_EDI                   (0x00100000)
 267
 268#define reg_RX_QUEUE_0_BUF_CONFIG(base)         __REG32(base, 0x00000384)
 269#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT          (0x0000003f)
 270#define RX_QUEUE_0_BUF_CONFIG_BURST             (0x00000300)
 271#define RX_QUEUE_0_BUF_CONFIG_BSWP              (0x00000400)
 272#define RX_QUEUE_0_BUF_CONFIG_WSWP              (0x00000800)
 273
 274#define reg_RX_QUEUE_0_PTR_LOW(base)            __REG32(base, 0x00000388)
 275
 276#define reg_RX_QUEUE_0_PTR_HIGH(base)           __REG32(base, 0x0000038c)
 277#define RX_QUEUE_0_PTR_HIGH_VALID               (0x80000000)
 278
 279/*
 280 *  PHY register definitions
 281 */
 282/* the first 15 PHY registers are standard. */
 283#define PHY_CTRL_REG            0       /* Control Register */
 284#define PHY_STATUS_REG          1       /* Status Regiser */
 285#define PHY_ID1_REG             2       /* Phy Id Reg (word 1) */
 286#define PHY_ID2_REG             3       /* Phy Id Reg (word 2) */
 287#define PHY_AN_ADV_REG          4       /* Autoneg Advertisement */
 288#define PHY_LP_ABILITY_REG      5       /* Link Partner Ability (Base Page) */
 289#define PHY_AUTONEG_EXP_REG     6       /* Autoneg Expansion Reg */
 290#define PHY_NEXT_PAGE_TX_REG    7       /* Next Page TX */
 291#define PHY_LP_NEXT_PAGE_REG    8       /* Link Partner Next Page */
 292#define PHY_1000T_CTRL_REG      9       /* 1000Base-T Control Reg */
 293#define PHY_1000T_STATUS_REG    10      /* 1000Base-T Status Reg */
 294#define PHY_EXT_STATUS_REG      11      /* Extended Status Reg */
 295
 296/*
 297 * PHY Register bit masks.
 298 */
 299#define PHY_CTRL_RESET          (1 << 15)
 300#define PHY_CTRL_LOOPBACK       (1 << 14)
 301#define PHY_CTRL_SPEED0         (1 << 13)
 302#define PHY_CTRL_AN_EN          (1 << 12)
 303#define PHY_CTRL_PWR_DN         (1 << 11)
 304#define PHY_CTRL_ISOLATE        (1 << 10)
 305#define PHY_CTRL_RESTART_AN     (1 << 9)
 306#define PHY_CTRL_FULL_DUPLEX    (1 << 8)
 307#define PHY_CTRL_CT_EN          (1 << 7)
 308#define PHY_CTRL_SPEED1         (1 << 6)
 309
 310#define PHY_STAT_100BASE_T4     (1 << 15)
 311#define PHY_STAT_100BASE_X_FD   (1 << 14)
 312#define PHY_STAT_100BASE_X_HD   (1 << 13)
 313#define PHY_STAT_10BASE_T_FD    (1 << 12)
 314#define PHY_STAT_10BASE_T_HD    (1 << 11)
 315#define PHY_STAT_100BASE_T2_FD  (1 << 10)
 316#define PHY_STAT_100BASE_T2_HD  (1 << 9)
 317#define PHY_STAT_EXT_STAT       (1 << 8)
 318#define PHY_STAT_RESERVED       (1 << 7)
 319#define PHY_STAT_MFPS           (1 << 6)        /* Management Frames Preamble Suppression */
 320#define PHY_STAT_AN_COMPLETE    (1 << 5)
 321#define PHY_STAT_REM_FAULT      (1 << 4)
 322#define PHY_STAT_AN_CAP         (1 << 3)
 323#define PHY_STAT_LINK_UP        (1 << 2)
 324#define PHY_STAT_JABBER         (1 << 1)
 325#define PHY_STAT_EXT_CAP        (1 << 0)
 326
 327#define TBI_CONTROL_2                                   0x11
 328#define TBI_CONTROL_2_ENABLE_COMMA_DETECT               0x0001
 329#define TBI_CONTROL_2_ENABLE_WRAP                       0x0002
 330#define TBI_CONTROL_2_G_MII_MODE                        0x0010
 331#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT              0x0020
 332#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE            0x0100
 333#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY        0x1000
 334#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY         0x2000
 335#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER                       0x4000
 336#define TBI_CONTROL_2_SOFT_RESET                                0x8000
 337
 338/* marvel specific */
 339#define MV1111_EXT_CTRL1_REG    16      /* PHY Specific Control Reg */
 340#define MV1111_SPEC_STAT_REG    17      /* PHY Specific Status Reg */
 341#define MV1111_EXT_CTRL2_REG    20      /* Extended PHY Specific Control Reg */
 342
 343/*
 344 * MARVELL 88E1111 PHY register bit masks
 345 */
 346/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
 347
 348#define SPEC_STAT_SPEED_MASK    (3 << 14)
 349#define SPEC_STAT_FULL_DUP      (1 << 13)
 350#define SPEC_STAT_PAGE_RCVD     (1 << 12)
 351#define SPEC_STAT_RESOLVED      (1 << 11)       /* Speed and Duplex Resolved */
 352#define SPEC_STAT_LINK_UP       (1 << 10)
 353#define SPEC_STAT_CABLE_LEN_MASK        (7 << 7)/* Cable Length (100/1000 modes only) */
 354#define SPEC_STAT_MDIX          (1 << 6)
 355#define SPEC_STAT_POLARITY      (1 << 1)
 356#define SPEC_STAT_JABBER        (1 << 0)
 357
 358#define SPEED_1000              (2 << 14)
 359#define SPEED_100               (1 << 14)
 360#define SPEED_10                (0 << 14)
 361
 362#define TBI_ADDR        0x1E    /* Ten Bit Interface address */
 363
 364/* negotiated link parameters */
 365#define LINK_SPEED_UNKNOWN      0
 366#define LINK_SPEED_10           1
 367#define LINK_SPEED_100          2
 368#define LINK_SPEED_1000         3
 369
 370#define LINK_DUPLEX_UNKNOWN     0
 371#define LINK_DUPLEX_HALF        1
 372#define LINK_DUPLEX_FULL        2
 373
 374static unsigned int phy_address[] = { 8, 9 };
 375
 376#define vuint32 volatile u32
 377
 378/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
 379 * This structure is accessed by the ethernet DMA engine which means it
 380 * MUST be in LITTLE ENDIAN format */
 381struct dma_descriptor {
 382        vuint32 start_addr0;    /* buffer address, least significant bytes. */
 383        vuint32 start_addr1;    /* buffer address, most significant bytes. */
 384        vuint32 next_descr_addr0;/* next descriptor address, least significant bytes.  Must be 64-bit aligned. */
 385        vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
 386        vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
 387        vuint32 config_status;  /* Configuration/Status. */
 388        vuint32 reserved1;      /* reserved to make the descriptor cache line aligned. */
 389        vuint32 reserved2;      /* reserved to make the descriptor cache line aligned. */
 390};
 391
 392/* last next descriptor address flag */
 393#define DMA_DESCR_LAST          (1 << 31)
 394
 395/* TX DMA descriptor config status bits */
 396#define DMA_DESCR_TX_EOF        (1 <<  0)       /* end of frame */
 397#define DMA_DESCR_TX_SOF        (1 <<  1)       /* start of frame */
 398#define DMA_DESCR_TX_PFVLAN     (1 <<  2)
 399#define DMA_DESCR_TX_HUGE       (1 <<  3)
 400#define DMA_DESCR_TX_PAD        (1 <<  4)
 401#define DMA_DESCR_TX_CRC        (1 <<  5)
 402#define DMA_DESCR_TX_DESCR_INT  (1 << 14)
 403#define DMA_DESCR_TX_RETRY_COUNT        0x000F0000
 404#define DMA_DESCR_TX_ONE_COLLISION      (1 << 20)
 405#define DMA_DESCR_TX_LATE_COLLISION     (1 << 24)
 406#define DMA_DESCR_TX_UNDERRUN           (1 << 25)
 407#define DMA_DESCR_TX_RETRY_LIMIT        (1 << 26)
 408#define DMA_DESCR_TX_OK                 (1 << 30)
 409#define DMA_DESCR_TX_OWNER              (1 << 31)
 410
 411/* RX DMA descriptor status bits */
 412#define DMA_DESCR_RX_EOF                (1 <<  0)
 413#define DMA_DESCR_RX_SOF                (1 <<  1)
 414#define DMA_DESCR_RX_VTF                (1 <<  2)
 415#define DMA_DESCR_RX_FRAME_IS_TYPE      (1 <<  3)
 416#define DMA_DESCR_RX_SHORT_FRAME        (1 <<  4)
 417#define DMA_DESCR_RX_HASH_MATCH         (1 <<  7)
 418#define DMA_DESCR_RX_BAD_FRAME          (1 <<  8)
 419#define DMA_DESCR_RX_OVERRUN            (1 <<  9)
 420#define DMA_DESCR_RX_MAX_FRAME_LEN      (1 << 11)
 421#define DMA_DESCR_RX_CRC_ERROR          (1 << 12)
 422#define DMA_DESCR_RX_DESCR_INT          (1 << 13)
 423#define DMA_DESCR_RX_OWNER              (1 << 15)
 424
 425#define RX_BUFFER_SIZE  PKTSIZE
 426#define NUM_RX_DESC     PKTBUFSRX
 427
 428static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
 429
 430static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
 431        __attribute__ ((aligned(32)));
 432
 433static struct dma_descriptor *rx_descr_current;
 434
 435static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
 436static int tsi108_eth_send (struct eth_device *dev,
 437                           volatile void *packet, int length);
 438static int tsi108_eth_recv (struct eth_device *dev);
 439static void tsi108_eth_halt (struct eth_device *dev);
 440static unsigned int read_phy (unsigned int base,
 441                             unsigned int phy_addr, unsigned int phy_reg);
 442static void write_phy (unsigned int base,
 443                      unsigned int phy_addr,
 444                      unsigned int phy_reg, unsigned int phy_data);
 445
 446#if TSI108_ETH_DEBUG > 100
 447/*
 448 * print phy debug infomation
 449 */
 450static void dump_phy_regs (unsigned int phy_addr)
 451{
 452        int i;
 453
 454        printf ("PHY %d registers\n", phy_addr);
 455        for (i = 0; i <= 30; i++) {
 456                printf ("%2d  0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
 457        }
 458        printf ("\n");
 459
 460}
 461#else
 462#define dump_phy_regs(base) do{}while(0)
 463#endif
 464
 465#if TSI108_ETH_DEBUG > 100
 466/*
 467 * print debug infomation
 468 */
 469static void tx_diag_regs (unsigned int base)
 470{
 471        int i;
 472        unsigned long dummy;
 473
 474        printf ("TX diagnostics registers\n");
 475        reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
 476        udelay (1000);
 477        dummy = reg_TX_DIAGNOSTIC_DATA(base);
 478        for (i = 0x00; i <= 0x05; i++) {
 479                udelay (1000);
 480                printf ("0x%02x  0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
 481        }
 482        reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
 483        udelay (1000);
 484        dummy = reg_TX_DIAGNOSTIC_DATA(base);
 485        for (i = 0x40; i <= 0x47; i++) {
 486                udelay (1000);
 487                printf ("0x%02x  0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
 488        }
 489        printf ("\n");
 490
 491}
 492#else
 493#define tx_diag_regs(base) do{}while(0)
 494#endif
 495
 496#if TSI108_ETH_DEBUG > 100
 497/*
 498 * print debug infomation
 499 */
 500static void rx_diag_regs (unsigned int base)
 501{
 502        int i;
 503        unsigned long dummy;
 504
 505        printf ("RX diagnostics registers\n");
 506        reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
 507        udelay (1000);
 508        dummy = reg_RX_DIAGNOSTIC_DATA(base);
 509        for (i = 0x00; i <= 0x05; i++) {
 510                udelay (1000);
 511                printf ("0x%02x  0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
 512        }
 513        reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
 514        udelay (1000);
 515        dummy = reg_RX_DIAGNOSTIC_DATA(base);
 516        for (i = 0x08; i <= 0x0a; i++) {
 517                udelay (1000);
 518                printf ("0x%02x  0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
 519        }
 520        printf ("\n");
 521
 522}
 523#else
 524#define rx_diag_regs(base) do{}while(0)
 525#endif
 526
 527#if TSI108_ETH_DEBUG > 100
 528/*
 529 * print debug infomation
 530 */
 531static void debug_mii_regs (unsigned int base)
 532{
 533        printf ("MII_MGMT_CONFIG     0x%08x\n", reg_MII_MGMT_CONFIG(base));
 534        printf ("MII_MGMT_COMMAND    0x%08x\n", reg_MII_MGMT_COMMAND(base));
 535        printf ("MII_MGMT_ADDRESS    0x%08x\n", reg_MII_MGMT_ADDRESS(base));
 536        printf ("MII_MGMT_CONTROL    0x%08x\n", reg_MII_MGMT_CONTROL(base));
 537        printf ("MII_MGMT_STATUS     0x%08x\n", reg_MII_MGMT_STATUS(base));
 538        printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
 539        printf ("\n");
 540
 541}
 542#else
 543#define debug_mii_regs(base) do{}while(0)
 544#endif
 545
 546/*
 547 * Wait until the phy bus is non-busy
 548 */
 549static void phy_wait (unsigned int base, unsigned int condition)
 550{
 551        int timeout;
 552
 553        timeout = 0;
 554        while (reg_MII_MGMT_INDICATORS(base) & condition) {
 555                udelay (10);
 556                if (++timeout > 10000) {
 557                        printf ("ERROR: timeout waiting for phy bus (%d)\n",
 558                               condition);
 559                        break;
 560                }
 561        }
 562}
 563
 564/*
 565 * read phy register
 566 */
 567static unsigned int read_phy (unsigned int base,
 568                             unsigned int phy_addr, unsigned int phy_reg)
 569{
 570        unsigned int value;
 571
 572        phy_wait (base, MII_MGMT_INDICATORS_BUSY);
 573
 574        reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
 575
 576        /* Ensure that the Read Cycle bit is cleared prior to next read cycle */
 577        reg_MII_MGMT_COMMAND(base) = 0;
 578
 579        /* start the read */
 580        reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
 581
 582        /* wait for the read to complete */
 583        phy_wait (base,
 584                 MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
 585
 586        value = reg_MII_MGMT_STATUS(base);
 587
 588        reg_MII_MGMT_COMMAND(base) = 0;
 589
 590        return value;
 591}
 592
 593/*
 594 * write phy register
 595 */
 596static void write_phy (unsigned int base,
 597                      unsigned int phy_addr,
 598                      unsigned int phy_reg, unsigned int phy_data)
 599{
 600        phy_wait (base, MII_MGMT_INDICATORS_BUSY);
 601
 602        reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
 603
 604        /* Ensure that the Read Cycle bit is cleared prior to next cycle */
 605        reg_MII_MGMT_COMMAND(base) = 0;
 606
 607        /* start the write */
 608        reg_MII_MGMT_CONTROL(base) = phy_data;
 609}
 610
 611/*
 612 * configure the marvell 88e1111 phy
 613 */
 614static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
 615                                  int *duplex)
 616{
 617        unsigned long base;
 618        unsigned long phy_addr;
 619        unsigned int phy_status;
 620        unsigned int phy_spec_status;
 621        int timeout;
 622        int phy_speed;
 623        int phy_duplex;
 624        unsigned int value;
 625
 626        phy_speed = LINK_SPEED_UNKNOWN;
 627        phy_duplex = LINK_DUPLEX_UNKNOWN;
 628
 629        base = dev->iobase;
 630        phy_addr = (unsigned long)dev->priv;
 631
 632        /* Take the PHY out of reset. */
 633        write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
 634
 635        /* Wait for the reset process to complete. */
 636        udelay (10);
 637        timeout = 0;
 638        while ((phy_status =
 639                read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
 640                udelay (10);
 641                if (++timeout > 10000) {
 642                        printf ("ERROR: timeout waiting for phy reset\n");
 643                        break;
 644                }
 645        }
 646
 647        /* TBI Configuration. */
 648        write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
 649                  TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
 650        /* Wait for the link to be established. */
 651        timeout = 0;
 652        do {
 653                udelay (20000);
 654                phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
 655                if (++timeout > 100) {
 656                        debug_lev(1, "ERROR: unable to establish link!!!\n");
 657                        break;
 658                }
 659        } while ((phy_status & PHY_STAT_LINK_UP) == 0);
 660
 661        if ((phy_status & PHY_STAT_LINK_UP) == 0)
 662                return 0;
 663
 664        value = 0;
 665        phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
 666        if (phy_spec_status & SPEC_STAT_RESOLVED) {
 667                switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
 668                case SPEED_1000:
 669                        phy_speed = LINK_SPEED_1000;
 670                        value |= PHY_CTRL_SPEED1;
 671                        break;
 672                case SPEED_100:
 673                        phy_speed = LINK_SPEED_100;
 674                        value |= PHY_CTRL_SPEED0;
 675                        break;
 676                case SPEED_10:
 677                        phy_speed = LINK_SPEED_10;
 678                        break;
 679                }
 680                if (phy_spec_status & SPEC_STAT_FULL_DUP) {
 681                        phy_duplex = LINK_DUPLEX_FULL;
 682                        value |= PHY_CTRL_FULL_DUPLEX;
 683                } else
 684                        phy_duplex = LINK_DUPLEX_HALF;
 685        }
 686        /* set TBI speed */
 687        write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
 688        write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
 689
 690#if TSI108_ETH_DEBUG > 0
 691        printf ("%s link is up", dev->name);
 692        phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
 693        if (phy_spec_status & SPEC_STAT_RESOLVED) {
 694                switch (phy_speed) {
 695                case LINK_SPEED_1000:
 696                        printf (", 1000 Mbps");
 697                        break;
 698                case LINK_SPEED_100:
 699                        printf (", 100 Mbps");
 700                        break;
 701                case LINK_SPEED_10:
 702                        printf (", 10 Mbps");
 703                        break;
 704                }
 705                if (phy_duplex == LINK_DUPLEX_FULL)
 706                        printf (", Full duplex");
 707                else
 708                        printf (", Half duplex");
 709        }
 710        printf ("\n");
 711#endif
 712
 713        dump_phy_regs (TBI_ADDR);
 714        if (speed)
 715                *speed = phy_speed;
 716        if (duplex)
 717                *duplex = phy_duplex;
 718
 719        return 1;
 720}
 721
 722/*
 723 * External interface
 724 *
 725 * register the tsi108 ethernet controllers with the multi-ethernet system
 726 */
 727int tsi108_eth_initialize (bd_t * bis)
 728{
 729        struct eth_device *dev;
 730        int index;
 731
 732        for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
 733                dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 734
 735                sprintf (dev->name, "TSI108_eth%d", index);
 736
 737                dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
 738                dev->priv = (void *)(phy_address[index]);
 739                dev->init = tsi108_eth_probe;
 740                dev->halt = tsi108_eth_halt;
 741                dev->send = tsi108_eth_send;
 742                dev->recv = tsi108_eth_recv;
 743
 744                eth_register(dev);
 745        }
 746        return index;
 747}
 748
 749/*
 750 * probe for and initialize a single ethernet interface
 751 */
 752static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
 753{
 754        unsigned long base;
 755        unsigned long value;
 756        int index;
 757        struct dma_descriptor *tx_descr;
 758        struct dma_descriptor *rx_descr;
 759        int speed;
 760        int duplex;
 761
 762        base = dev->iobase;
 763
 764        reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
 765
 766        /* Bring DMA/FIFO out of reset. */
 767        reg_TX_CONFIG(base) = 0x00000000;
 768        reg_RX_CONFIG(base) = 0x00000000;
 769
 770        reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
 771        reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
 772
 773        /* Bring MAC out of reset. */
 774        reg_MAC_CONFIG_1(base) = 0x00000000;
 775
 776        /* DMA MAC configuration. */
 777        reg_MAC_CONFIG_1(base) =
 778            MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
 779
 780        reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
 781        reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
 782
 783        /* Note: Early tsi108 manual did not have correct byte order
 784         * for the station address.*/
 785        reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
 786            (dev->enetaddr[4] << 16) |
 787            (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
 788
 789        reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
 790            (dev->enetaddr[0] << 16);
 791
 792        if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
 793                return -1;
 794
 795        value =
 796            MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
 797            MAC_CONFIG_2_CRC_ENABLE;
 798        if (speed == LINK_SPEED_1000)
 799                value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
 800        else {
 801                value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
 802                reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
 803        }
 804        if (duplex == LINK_DUPLEX_FULL) {
 805                value |= MAC_CONFIG_2_FULL_DUPLEX;
 806                reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
 807        } else
 808                reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
 809        reg_MAC_CONFIG_2(base) = value;
 810
 811        reg_RX_CONFIG(base) = RX_CONFIG_SE;
 812        reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
 813        reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
 814
 815        /* initialize the RX DMA descriptors */
 816        rx_descr = &rx_descr_array[0];
 817        rx_descr_current = rx_descr;
 818        for (index = 0; index < NUM_RX_DESC; index++) {
 819                /* make sure the receive buffers are not in cache */
 820                invalidate_dcache_range((unsigned long)NetRxPackets[index],
 821                                        (unsigned long)NetRxPackets[index] +
 822                                        RX_BUFFER_SIZE);
 823                rx_descr->start_addr0 =
 824                    cpu_to_le32((vuint32) NetRxPackets[index]);
 825                rx_descr->start_addr1 = 0;
 826                rx_descr->next_descr_addr0 =
 827                    cpu_to_le32((vuint32) (rx_descr + 1));
 828                rx_descr->next_descr_addr1 = 0;
 829                rx_descr->vlan_byte_count = 0;
 830                rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
 831                                                      DMA_DESCR_RX_OWNER);
 832                rx_descr++;
 833        }
 834        rx_descr--;
 835        rx_descr->next_descr_addr0 = 0;
 836        rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
 837        /* Push the descriptors to RAM so the ethernet DMA can see them */
 838        invalidate_dcache_range((unsigned long)rx_descr_array,
 839                                (unsigned long)rx_descr_array +
 840                                sizeof(rx_descr_array));
 841
 842        /* enable RX queue */
 843        reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
 844        reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
 845        /* enable receive DMA */
 846        reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
 847
 848        reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
 849        reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
 850
 851        /* initialize the TX DMA descriptor */
 852        tx_descr = &tx_descriptor;
 853
 854        tx_descr->start_addr0 = 0;
 855        tx_descr->start_addr1 = 0;
 856        tx_descr->next_descr_addr0 = 0;
 857        tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
 858        tx_descr->vlan_byte_count = 0;
 859        tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
 860                                              DMA_DESCR_TX_SOF |
 861                                              DMA_DESCR_TX_EOF);
 862        /* enable TX queue */
 863        reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
 864
 865        return 0;
 866}
 867
 868/*
 869 * send a packet
 870 */
 871static int tsi108_eth_send (struct eth_device *dev,
 872                           volatile void *packet, int length)
 873{
 874        unsigned long base;
 875        int timeout;
 876        struct dma_descriptor *tx_descr;
 877        unsigned long status;
 878
 879        base = dev->iobase;
 880        tx_descr = &tx_descriptor;
 881
 882        /* Wait until the last packet has been transmitted. */
 883        timeout = 0;
 884        do {
 885                /* make sure we see the changes made by the DMA engine */
 886                invalidate_dcache_range((unsigned long)tx_descr,
 887                                        (unsigned long)tx_descr +
 888                                        sizeof(struct dma_descriptor));
 889
 890                if (timeout != 0)
 891                        udelay (15);
 892                if (++timeout > 10000) {
 893                        tx_diag_regs(base);
 894                        debug_lev(1,
 895                                  "ERROR: timeout waiting for last transmit packet to be sent\n");
 896                        return 0;
 897                }
 898        } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
 899
 900        status = le32_to_cpu(tx_descr->config_status);
 901        if ((status & DMA_DESCR_TX_OK) == 0) {
 902#ifdef TX_PRINT_ERRORS
 903                printf ("TX packet error: 0x%08lx\n    %s%s%s%s\n", status,
 904                       status & DMA_DESCR_TX_OK ? "tx error, " : "",
 905                       status & DMA_DESCR_TX_RETRY_LIMIT ?
 906                       "retry limit reached, " : "",
 907                       status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
 908                       status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
 909                       : "");
 910#endif
 911        }
 912
 913        debug_lev (9, "sending packet %d\n", length);
 914        tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
 915        tx_descr->start_addr1 = 0;
 916        tx_descr->next_descr_addr0 = 0;
 917        tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
 918        tx_descr->vlan_byte_count = cpu_to_le32(length);
 919        tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
 920                                              DMA_DESCR_TX_CRC |
 921                                              DMA_DESCR_TX_PAD |
 922                                              DMA_DESCR_TX_SOF |
 923                                              DMA_DESCR_TX_EOF);
 924
 925        invalidate_dcache_range((unsigned long)tx_descr,
 926                                (unsigned long)tx_descr +
 927                                sizeof(struct dma_descriptor));
 928
 929        invalidate_dcache_range((unsigned long)packet,
 930                                (unsigned long)packet + length);
 931
 932        reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
 933        reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
 934
 935        return length;
 936}
 937
 938/*
 939 * Check for received packets and send them up the protocal stack
 940 */
 941static int tsi108_eth_recv (struct eth_device *dev)
 942{
 943        struct dma_descriptor *rx_descr;
 944        unsigned long base;
 945        int length = 0;
 946        unsigned long status;
 947        volatile uchar *buffer;
 948
 949        base = dev->iobase;
 950
 951        /* make sure we see the changes made by the DMA engine */
 952        invalidate_dcache_range ((unsigned long)rx_descr_array,
 953                                (unsigned long)rx_descr_array +
 954                                sizeof(rx_descr_array));
 955
 956        /* process all of the received packets */
 957        rx_descr = rx_descr_current;
 958        while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
 959                /* check for error */
 960                status = le32_to_cpu(rx_descr->config_status);
 961                if (status & DMA_DESCR_RX_BAD_FRAME) {
 962#ifdef RX_PRINT_ERRORS
 963                        printf ("RX packet error: 0x%08lx\n    %s%s%s%s%s%s\n",
 964                               status,
 965                               status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
 966                               : "",
 967                               status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
 968                               : "",
 969                               status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
 970                               "",
 971                               status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
 972                               status & DMA_DESCR_RX_MAX_FRAME_LEN ?
 973                               "max length, " : "",
 974                               status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
 975                               "");
 976#endif
 977                } else {
 978                        length =
 979                            le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
 980
 981                        /*** process packet ***/
 982                        buffer =
 983                            (volatile uchar
 984                             *)(le32_to_cpu (rx_descr->start_addr0));
 985                        NetReceive (buffer, length);
 986
 987                        invalidate_dcache_range ((unsigned long)buffer,
 988                                                (unsigned long)buffer +
 989                                                RX_BUFFER_SIZE);
 990                }
 991                /* Give this buffer back to the DMA engine */
 992                rx_descr->vlan_byte_count = 0;
 993                rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
 994                                                      DMA_DESCR_RX_OWNER);
 995                /* move descriptor pointer forward */
 996                rx_descr =
 997                    (struct dma_descriptor
 998                     *)(le32_to_cpu (rx_descr->next_descr_addr0));
 999                if (rx_descr == 0)
1000                        rx_descr = &rx_descr_array[0];
1001        }
1002        /* remember where we are for next time */
1003        rx_descr_current = rx_descr;
1004
1005        /* If the DMA engine has reached the end of the queue
1006         * start over at the begining */
1007        if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
1008
1009                reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
1010                reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
1011                reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
1012        }
1013
1014        return length;
1015}
1016
1017/*
1018 * disable an ethernet interface
1019 */
1020static void tsi108_eth_halt (struct eth_device *dev)
1021{
1022        unsigned long base;
1023
1024        base = dev->iobase;
1025
1026        /* Put DMA/FIFO into reset state. */
1027        reg_TX_CONFIG(base) = TX_CONFIG_RST;
1028        reg_RX_CONFIG(base) = RX_CONFIG_RST;
1029
1030        /* Put MAC into reset state. */
1031        reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
1032}
1033